diff options
Diffstat (limited to 'include')
155 files changed, 7580 insertions, 1001 deletions
diff --git a/include/ahci.h b/include/ahci.h index e8dee53575..6d917121c6 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -151,7 +151,7 @@ struct ahci_probe_ent { u32 hard_port_no; u32 host_flags; u32 host_set_flags; - u32 mmio_base; + void __iomem *mmio_base; u32 pio_mask; u32 udma_mask; u32 flags; @@ -160,7 +160,7 @@ struct ahci_probe_ent { u32 link_port_map; /*linkup port map*/ }; -int ahci_init(u32 base); -int ahci_reset(u32 base); +int ahci_init(void __iomem *base); +int ahci_reset(void __iomem *base); #endif diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h index fa8aa29454..6993128b1b 100644 --- a/include/atmel_lcd.h +++ b/include/atmel_lcd.h @@ -13,7 +13,8 @@ typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ - u_long vl_clk; /* pixel clock in ps */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ + u_long vl_clk; /* pixel clock in ps */ /* LCD configuration register */ u_long vl_sync; /* Horizontal / vertical sync */ diff --git a/include/axp152.h b/include/axp152.h index 3e5ccbd0d8..9d205f8d3a 100644 --- a/include/axp152.h +++ b/include/axp152.h @@ -3,6 +3,18 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + +enum axp152_reg { + AXP152_CHIP_VERSION = 0x3, + AXP152_DCDC2_VOLTAGE = 0x23, + AXP152_DCDC3_VOLTAGE = 0x27, + AXP152_DCDC4_VOLTAGE = 0x2B, + AXP152_LDO2_VOLTAGE = 0x2A, + AXP152_SHUTDOWN = 0x32, +}; + +#define AXP152_POWEROFF (1 << 7) + int axp152_set_dcdc2(int mvolt); int axp152_set_dcdc3(int mvolt); int axp152_set_dcdc4(int mvolt); diff --git a/include/axp209.h b/include/axp209.h index 043624953a..d36da41a5e 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -4,6 +4,44 @@ * SPDX-License-Identifier: GPL-2.0+ */ +enum axp209_reg { + AXP209_POWER_STATUS = 0x00, + AXP209_CHIP_VERSION = 0x03, + AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_DCDC3_VOLTAGE = 0x27, + AXP209_LDO24_VOLTAGE = 0x28, + AXP209_LDO3_VOLTAGE = 0x29, + AXP209_IRQ_ENABLE1 = 0x40, + AXP209_IRQ_ENABLE2 = 0x41, + AXP209_IRQ_ENABLE3 = 0x42, + AXP209_IRQ_ENABLE4 = 0x43, + AXP209_IRQ_ENABLE5 = 0x44, + AXP209_IRQ_STATUS5 = 0x4c, + AXP209_SHUTDOWN = 0x32, + AXP209_GPIO0_CTRL = 0x90, + AXP209_GPIO1_CTRL = 0x92, + AXP209_GPIO2_CTRL = 0x93, + AXP209_GPIO_STATE = 0x94, + AXP209_GPIO3_CTRL = 0x95, +}; + +#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) +#define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4) + +#define AXP209_IRQ5_PEK_UP (1 << 6) +#define AXP209_IRQ5_PEK_DOWN (1 << 5) + +#define AXP209_POWEROFF (1 << 7) + +#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP209_GPIO_INPUT 0x02 /* Float pin */ + +/* GPIO3 is different from the others */ +#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */ +#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */ +#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */ + #define AXP_GPIO extern int axp209_set_dcdc2(int mvolt); diff --git a/include/axp221.h b/include/axp221.h index be6058e439..0aac04dfeb 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -62,11 +62,7 @@ /* Page 1 addresses */ #define AXP221_SID 0x20 -/* We support vbus detection */ -#define AXP_VBUS_DETECT - -/* We support drivebus control */ -#define AXP_DRIVEBUS +#define AXP_GPIO int axp221_set_dcdc1(unsigned int mvolt); int axp221_set_dcdc2(unsigned int mvolt); @@ -83,6 +79,8 @@ int axp221_set_aldo3(unsigned int mvolt); int axp221_set_eldo(int eldo_num, unsigned int mvolt); int axp221_init(void); int axp221_get_sid(unsigned int *sid); -int axp_get_vbus(void); -int axp_drivebus_enable(void); -int axp_drivebus_disable(void); + +int axp_gpio_direction_input(unsigned int pin); +int axp_gpio_direction_output(unsigned int pin, unsigned int val); +int axp_gpio_get_value(unsigned int pin); +int axp_gpio_set_value(unsigned int pin, unsigned int val); diff --git a/include/bootstage.h b/include/bootstage.h index 0276cb3f60..be440148dd 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -11,7 +11,7 @@ #ifndef _BOOTSTAGE_H #define _BOOTSTAGE_H -/* The number of boot stage records available for the user */ +/* Define this for host tools */ #ifndef CONFIG_BOOTSTAGE_USER_COUNT #define CONFIG_BOOTSTAGE_USER_COUNT 20 #endif diff --git a/include/common.h b/include/common.h index 6df05b8bb1..cde3474b18 100644 --- a/include/common.h +++ b/include/common.h @@ -253,6 +253,17 @@ int update_flash_size(int flash_size); int arch_early_init_r(void); /** + * arch_cpu_init_dm() - init CPU after driver model is available + * + * This is called immediately after driver model is available before + * relocation. This is similar to arch_cpu_init() but is able to reference + * devices + * + * @return 0 if OK, -ve on error + */ +int arch_cpu_init_dm(void); + +/** * Reserve all necessary stacks * * This is used in generic board init sequence in common/board_f.c. Each @@ -471,7 +482,6 @@ int testdram(void); defined(CONFIG_8xx) uint get_immr (uint); #endif -uint get_pir (void); #if defined(CONFIG_MPC5xxx) uint get_svr (void); #endif @@ -733,6 +743,45 @@ int gunzip(void *, int, unsigned char *, unsigned long *); int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset); +/** + * gzwrite progress indicators: defined weak to allow board-specific + * overrides: + * + * gzwrite_progress_init called on startup + * gzwrite_progress called during decompress/write loop + * gzwrite_progress_finish called at end of loop to + * indicate success (retcode=0) or failure + */ +void gzwrite_progress_init(u64 expected_size); + +void gzwrite_progress(int iteration, + u64 bytes_written, + u64 total_bytes); + +void gzwrite_progress_finish(int retcode, + u64 totalwritten, + u64 totalsize, + u32 expected_crc, + u32 calculated_crc); + +/** + * decompress and write gzipped image from memory to block device + * + * @param src compressed image address + * @param len compressed image length in bytes + * @param dev block device descriptor + * @param szwritebuf bytes per write (pad to erase size) + * @param startoffs offset in bytes of first write + * @param szexpected expected uncompressed length + * may be zero to use gzip trailer + * for files under 4GiB + */ +int gzwrite(unsigned char *src, int len, + struct block_dev_desc *dev, + unsigned long szwritebuf, + u64 startoffs, + u64 szexpected); + /* lib/qsort.c */ void qsort(void *base, size_t nmemb, size_t size, int(*compar)(const void *, const void *)); @@ -815,7 +864,7 @@ int zzip(void *dst, unsigned long *lenp, unsigned char *src, /* lib/net_utils.c */ #include <net.h> -static inline IPaddr_t getenv_IPaddr(char *var) +static inline struct in_addr getenv_ip(char *var) { return string_to_ip(getenv(var)); } @@ -847,23 +896,6 @@ int cpu_disable(int nr); int cpu_release(int nr, int argc, char * const argv[]); #endif -/* Define a null map_sysmem() if the architecture doesn't use it */ -# ifndef CONFIG_ARCH_MAP_SYSMEM -static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) -{ - return (void *)(uintptr_t)paddr; -} - -static inline void unmap_sysmem(const void *vaddr) -{ -} - -static inline phys_addr_t map_to_sysmem(const void *ptr) -{ - return (phys_addr_t)(uintptr_t)ptr; -} -# endif - #endif /* __ASSEMBLY__ */ #ifdef CONFIG_PPC diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index d71e58dae1..3a360ca49a 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -48,6 +48,18 @@ #define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ #devtypel #instance " " +#ifdef CONFIG_SANDBOX +#define BOOTENV_SHARED_HOST BOOTENV_SHARED_BLKDEV(host) +#define BOOTENV_DEV_HOST BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_HOST BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_HOST +#define BOOTENV_DEV_HOST \ + BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX +#define BOOTENV_DEV_NAME_HOST \ + BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX +#endif + #ifdef CONFIG_CMD_MMC #define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV @@ -167,6 +179,7 @@ #define BOOTENV_DEV(devtypeu, devtypel, instance) \ BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance) #define BOOTENV \ + BOOTENV_SHARED_HOST \ BOOTENV_SHARED_MMC \ BOOTENV_SHARED_USB \ BOOTENV_SHARED_SATA \ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 8237239c00..5eea5cf900 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -29,6 +29,10 @@ #else #define CONFIG_BOOTP_VCI_STRING "U-boot.arm" #endif +#elif defined(__i386__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x0 +#elif defined(__x86_64__) +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x9 #endif #define CONFIG_OF_LIBFDT diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h new file mode 100644 index 0000000000..050b157902 --- /dev/null +++ b/include/config_fsl_secboot.h @@ -0,0 +1,89 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_FSL_SECBOOT_H +#define __CONFIG_FSL_SECBOOT_H + +#ifdef CONFIG_SECURE_BOOT + +#ifndef CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_ESBC_VALIDATE +#endif + +#ifndef CONFIG_EXTRA_ENV +#define CONFIG_EXTRA_ENV "" +#endif + +/* + * Control should not reach back to uboot after validation of images + * for secure boot flow and therefore bootscript should have + * the bootm command. If control reaches back to uboot anyhow + * after validating images, core should just spin. + */ + +/* + * Define the key hash for boot script here if public/private key pair used to + * sign bootscript are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_BOOTSCRIPT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ + +#ifdef CONFIG_BOOTSCRIPT_KEY_HASH +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr " \ + __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ + "source $img_addr;" \ + "esbc_halt\0" +#else +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr;" \ + "source $img_addr;" \ + "esbc_halt\0" +#endif + +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined(CONFIG_RAMBOOT_NAND) +#undef CONFIG_ENV_IS_IN_NAND +#elif defined(CONFIG_RAMBOOT_SDCARD) +#undef CONFIG_ENV_IS_IN_MMC +#endif +#else /*CONFIG_SYS_RAMBOOT*/ +#undef CONFIG_ENV_IS_IN_FLASH +#endif + +#define CONFIG_ENV_IS_NOWHERE + +/* + * We don't want boot delay for secure boot flow + * before autoboot starts + */ +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 0 +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT + +/* + * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for + * secure boot flow as defining this would enable a user to + * reach uboot prompt by pressing some key before start of + * autoboot + */ +#undef CONFIG_ZERO_BOOTDELAY_CHECK + +#endif +#endif diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index a9106f4f3b..38cb0e8aba 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -31,6 +31,7 @@ #undef CONFIG_DM_WARN #undef CONFIG_DM_DEVICE_REMOVE +#undef CONFIG_DM_SEQ_ALIAS #undef CONFIG_DM_STDIO #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 9390464b10..7eac03baaf 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -180,6 +180,10 @@ #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index e9424b4a07..ce33ba429f 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -267,6 +267,10 @@ # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } #endif +#define LDS_BOARD_TEXT \ + arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ + arch/m68k/lib/built-in.o (.text*) + /* * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 883347b0fd..4bba81544f 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -199,6 +199,11 @@ * Environment is embedded in u-boot in the second sector of the flash */ #define CONFIG_ENV_IS_IN_FLASH 1 + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); + #ifdef NORFLASH_PS32BIT # define CONFIG_ENV_OFFSET (0x8000) # define CONFIG_ENV_SIZE 0x4000 diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 60e5b45942..6167ea1ed5 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -91,6 +91,11 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_ENV_IS_IN_FLASH 1 + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); + #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 7421b57b0f..5d978747fe 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -32,6 +32,10 @@ # define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /* * Command line configuration. */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 8fd3907ad8..64dc64de2b 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -33,6 +33,11 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text) + + /* * BOOTP options */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2c056b114b..159d2f8ced 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -41,6 +41,10 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); + /* * BOOTP options */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 7eb31722da..14ccddb28d 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -42,6 +42,10 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); + /* * BOOTP options */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 569ad4201e..bc740ae905 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -32,6 +32,10 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /* * BOOTP options */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index e3fa85655b..0829708412 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -205,6 +205,10 @@ #define CONFIG_ENV_SECT_SIZE 0x8000 #define CONFIG_ENV_IS_IN_FLASH 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*) + /*----------------------------------------------------------------------- * Cache Configuration */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 795f3592b6..a42b5f6b47 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -209,6 +209,10 @@ #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /*----------------------------------------------------------------------- * Cache Configuration */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index d75b43cdd3..c142dfbe23 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -209,6 +209,10 @@ #define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_IS_IN_FLASH 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /*----------------------------------------------------------------------- * Cache Configuration */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a0d7d52627..9f755e50fc 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -255,7 +255,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -602,7 +602,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #else #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index faaf22c9bf..107efdc1f0 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -140,6 +140,11 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST + #ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -448,6 +453,17 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa + +#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_IR36021_READ +/* The lowest and highest voltage allowed for T208xRDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 /* * RapidIO @@ -646,8 +662,8 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G +#define CONFIG_PHY_AQUANTIA #define CONFIG_PHY_CORTINA -#define CONFIG_PHY_AQ1202 #define CONFIG_PHY_REALTEK #define CONFIG_CORTINA_FW_LENGTH 0x40000 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c1ad35a018..957a436374 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -638,6 +638,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_VITESSE #define CONFIG_PHY_CORTINA +#define CONFIG_SYS_CORTINA_FW_IN_NOR #define CONFIG_CORTINA_FW_ADDR 0xefe00000 #define CONFIG_CORTINA_FW_LENGTH 0x40000 #define CONFIG_PHY_TERANETICS diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 229fa5a6c2..5a06311d60 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -98,6 +98,10 @@ #define CONFIG_ENV_SIZE 0x1000 #define CONFIG_ENV_SECT_SIZE 0x1000 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*); + /* memory map space for linux boot data */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index 3066fd030e..cc26790776 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -262,6 +262,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index de837cfe08..7b9ff8fb23 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -343,6 +343,10 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text*) + #if ENABLE_JFFS /* JFFS Partition offset set */ #define CONFIG_SYS_JFFS2_FIRST_BANK 0 diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 8a7095c5b2..389f75bca8 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -116,7 +116,6 @@ /* * Ethernet configuration */ -#define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG #define CONFIG_NET_MULTI diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 878009ff66..7507d57527 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -71,7 +71,6 @@ #define CONFIG_NETCONSOLE #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" -#define CONFIG_DESIGNWARE_ETH #define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 #define CONFIG_DW_ALTDESCRIPTOR diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7b460e83c4..52657878c6 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -14,65 +14,6 @@ #define __CONFIG_H #include <configs/x86-common.h> - - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R - -#define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512 - -#define CONFIG_X86_SERIAL - -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} - -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - -#define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_PCI_PNP - -#define CONFIG_BIOSEMU -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R - -#undef CONFIG_ENV_IS_NOWHERE -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ - "stdout=vga,serial\0" \ - "stderr=vga,serial\0" +#include <configs/x86-chromebook.h> #endif /* __CONFIG_H */ diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h new file mode 100644 index 0000000000..00fe26da29 --- /dev/null +++ b/include/configs/chromebox_panther.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> +#include <configs/x86-chromebook.h> + +#define CONFIG_RTL8169 +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 4207504464..d6e5a2b243 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -245,6 +245,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index b9f0b0b123..38fcc40d9f 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -104,6 +104,9 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #endif +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); /* * BOOTP options diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h new file mode 100644 index 0000000000..414600ac43 --- /dev/null +++ b/include/configs/colibri_vf.h @@ -0,0 +1,271 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Configuration settings for the Toradex VF50/VF61 module. + * + * Based on vf610twr.h: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <config_cmd_default.h> + +#define CONFIG_VF610 +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_FSL_LPUART +#define LPUART_BASE UART0_BASE + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_VERSION_VARIABLE +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CMD_ASKENV + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_VF610_NFC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=vf610_nfc" +#define MTDPARTS_DEFAULT "mtdparts=vf610_nfc:" \ + "128k(vf-bcb)ro," \ + "1408k(u-boot)ro," \ + "512k(u-boot-env)," \ + "-(ubi)" + +#undef CONFIG_CMD_IMLS + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT3 +#define CONFIG_CMD_EXT4 +#define CONFIG_DOS_PARTITION + +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_UBI +#define CONFIG_MTD_UBI_FASTMAP +#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET1_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_LOADADDR 0x80008000 +#define CONFIG_FDTADDR 0x84000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 + +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ + "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "ubi part ubi && ubifsmount ubi0:rootfs && " \ + "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \ + "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" + +#define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x84000000\0" \ + "kernel_file=zImage\0" \ + "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ + "fdt_board=eval-v3\0" \ + "defargs=\0" \ + "console=ttyLP0\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs}\0" \ + "setsdupdate=mmc rescan && set interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setusbupdate=usb start && set interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setupdate=run setsdupdate || run setusbupdate\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ + SD_BOOTCMD \ + NFS_BOOTCMD \ + UBI_BOOTCMD + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Colibri VFxx # " +#undef CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE (64 * 2048) +#define CONFIG_ENV_RANGE (4 * 64 * 2048) +#define CONFIG_ENV_OFFSET (12 * 64 * 2048) +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* USB Host Support */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_VF +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* USB Client Support */ +#define CONFIG_USB_GADGET +#define CONFIG_CI_UDC +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_TRDX_VID 0x1B67 +#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016 +#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017 +#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018 +#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019 +#define CONFIG_G_DNL_MANUFACTURER "Toradex" +#define CONFIG_G_DNL_VENDOR_NUM CONFIG_TRDX_VID +#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_VF50 + +/* USB DFU */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_CMD_DFU +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_NAND +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024) + +/* USB Storage */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE + +#endif /* __CONFIG_H */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 1683a1582f..4dd7b11fb4 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -37,7 +37,7 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e78cc69af6..d79612b8bf 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -84,6 +84,14 @@ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_RAM +/* Fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x2F000000 +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 + #include <configs/ti_omap5_common.h> /* Enhance our eMMC support / experience. */ @@ -182,8 +190,8 @@ #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xd022 #define CONFIG_USB_GADGET_DUALSPEED /* USB Device Firmware Update support */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 5ce01fb2ae..bd0874065c 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -208,7 +208,7 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 #endif diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index b4b3ae842f..e9f5bed9ff 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -55,6 +55,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* USB Configs */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index ae0e5ff47b..95e96ecde4 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -28,16 +28,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* Sound */ -#define CONFIG_CMD_SOUND -#ifdef CONFIG_CMD_SOUND -#define CONFIG_SOUND -#define CONFIG_I2S_SAMSUNG -#define CONFIG_I2S -#define CONFIG_SOUND_MAX98095 -#define CONFIG_SOUND_WM8994 -#endif - /* I2C */ #define CONFIG_MAX_I2C_NUM 8 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index b42dab7a7f..3b1ac2cecd 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -15,8 +15,6 @@ #include <configs/exynos5-common.h> -#define CONFIG_ARCH_EARLY_INIT_R - #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 854ae90bd4..5f7cad8346 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -52,6 +52,7 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ #define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe #define CONFIG_MXC_SPI diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 620f9501d2..fcfc1b3603 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -95,9 +95,11 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 #define CONFIG_I2C_PMIC 1 +#define CONFIG_I2C_EDID /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -111,15 +113,12 @@ /* Filesystem support */ #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_UBIFS #define CONFIG_DOS_PARTITION -/* Network config - Allow larger/faster download for TFTP/NFS */ -#define CONFIG_IP_DEFRAG -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 - /* * SATA Configs */ @@ -179,10 +178,10 @@ /* Ethernet support */ #define CONFIG_FEC_MXC +#define CONFIG_E1000 #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB #define CONFIG_ARP_TIMEOUT 200UL @@ -208,6 +207,18 @@ #define CONFIG_NETCONSOLE #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +/* USB Mass Storage Gadget */ +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Netchip IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Gateworks" + /* Framebuffer and LCD */ #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 @@ -316,6 +327,7 @@ "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ HWCONFIG_DEFAULT \ @@ -326,28 +338,30 @@ \ "fdt_high=0xffffffff\0" \ "fdt_addr=0x18000000\0" \ + "initrd_high=0xffffffff\0" \ + "bootdir=boot\0" \ "loadfdt=" \ - "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ - "echo Loaded DTB from boot/${fdt_file}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ - "echo Loaded DTB from boot/${fdt_file1}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ - "echo Loaded DTB from boot/${fdt_file2}; " \ + "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ "fi\0" \ \ - "script=boot/6x_bootscript-ventana\0" \ + "script=6x_bootscript-ventana\0" \ "loadscript=" \ - "if ${fsload} ${loadaddr} ${script}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ "source; " \ "fi\0" \ \ - "uimage=boot/uImage\0" \ + "uimage=uImage\0" \ "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ "mmc_boot=" \ "setenv fsload 'ext2load mmc 0:1'; " \ "mmc dev 0 && mmc rescan && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/mmcblk0p1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -361,7 +375,7 @@ "sata_boot=" \ "setenv fsload 'ext2load sata 0:1'; sata init && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -374,7 +388,7 @@ "usb_boot=" \ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -417,8 +431,8 @@ #else #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ "tftp ${loadaddr} ${image_rootfs} && " \ "nand erase.part rootfs && " \ @@ -426,12 +440,21 @@ \ "flash_boot=" \ "setenv fsload 'ubifsload'; " \ - "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "ubi part rootfs; " \ + "if ubi check boot; then " \ + "ubifsmount ubi0:boot; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=squashfs,ubifs; " \ + "setenv bootdir; " \ + "elif ubi check rootfs; then " \ + "ubifsmount ubi0:rootfs; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs; " \ + "fi; " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ - "root=ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs ${video} ${extra}; " \ + "root=${root} ${video} ${extra}; " \ "if run loadfdt && fdt addr ${fdt_addr}; then " \ "ubifsumount; " \ "bootm ${loadaddr} - ${fdt_addr}; " \ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 49039d6dfb..db197f340c 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -38,6 +38,7 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET #define CONFIG_MXC_UART diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 4362925ae1..12c7382c17 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -7,8 +7,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#define CONFIG_INTEGRATOR - #define CONFIG_SYS_TEXT_BASE 0x01000000 #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END 0x10000000 diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index e168c8c9ba..8439db7818 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -18,7 +18,6 @@ #include "integrator-common.h" /* Integrator/AP-specific configuration */ -#define CONFIG_ARCH_INTEGRATOR #define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ /* diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 7c1ef2483e..7518b60fb2 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -18,7 +18,6 @@ #include "integrator-common.h" /* Integrator CP-specific configuration */ -#define CONFIG_ARCH_CINTEGRATOR #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ /* diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5de416d117..9a8fd5007e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -389,6 +389,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* * I2C bus multiplexer @@ -655,6 +656,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB +#include <asm/fsl_secure_boot.h> #endif #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b550..729205f712 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -205,6 +205,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ #ifndef CONFIG_SD_BOOT diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index e0435cc0a7..e270fc8c19 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -19,8 +19,20 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 +#include <asm/arch-fsl-lsch3/config.h> +#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) +#define CONFIG_SYS_HAS_SERDES +#endif + +/* We need architecture specific misc initializations */ +#define CONFIG_ARCH_MISC_INIT + /* Link Definitions */ -#define CONFIG_SYS_TEXT_BASE 0x30001000 +#ifdef CONFIG_SPL +#define CONFIG_SYS_TEXT_BASE 0x80400000 +#else +#define CONFIG_SYS_TEXT_BASE 0x30100000 +#endif #ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH @@ -39,13 +51,13 @@ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ @@ -69,23 +81,26 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS 1 -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 /* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 12000000 /* 12MHz */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ -#define CONFIG_CONS_INDEX 2 +#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -96,131 +111,98 @@ /* IFC */ #define CONFIG_FSL_IFC -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + /* - * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC - * address 0. But this region is limited to 256MB. To accommodate bigger NOR - * flash and other devices, we will map CS0 to 0x580000000 after relocation. + * During booting, IFC is mapped at the region of 0x30000000. + * But this region is limited to 256MB. To accommodate NOR, promjet + * and FPGA. This region is divided as below: + * 0x30000000 - 0x37ffffff : 128MB : NOR flash + * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet + * 0x3C000000 - 0x40000000 : 64MB : FPGA etc + * + * To accommodate bigger NOR flash and other devices, we will map IFC + * chip selects to as below: + * 0x5_1000_0000..0x5_1fff_ffff Memory Hole + * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) + * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB + * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) + * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) + * + * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. * CONFIG_SYS_FLASH_BASE has the final address (core view) * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting */ + #define CONFIG_SYS_FLASH_BASE 0x580000000ULL #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#endif -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#ifndef __ASSEMBLY__ +unsigned long long get_qixis_addr(void); #endif +#define QIXIS_BASE get_qixis_addr() +#define QIXIS_BASE_PHYS 0x20000000 +#define QIXIS_BASE_PHYS_EARLY 0xC000000 +#define QIXIS_STAT_PRES1 0xb +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 + +#define CONFIG_SYS_NAND_BASE 0x530000000ULL +#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0x520000000 -#define CONFIG_SYS_NAND_BASE_PHYS 0x20000000 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +/* 2 sec timeout */ +#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) /* MC firmware */ #define CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size() +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 + +/* Carve out a DDR region which will not be used by u-boot/Linux */ +#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) +#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() #endif +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define FSL_PCIE_COMPAT "fsl,20851a-pcie" + +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ + /* Command line configuration */ #define CONFIG_CMD_CACHE #define CONFIG_CMD_BDI @@ -228,6 +210,7 @@ #define CONFIG_CMD_ENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -237,8 +220,6 @@ #define CONFIG_CMD_BOOTD #define CONFIG_CMD_ECHO #define CONFIG_CMD_SOURCE -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) @@ -247,9 +228,6 @@ /* Physical Memory Map */ /* fixme: these need to be checked against the board */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - #define CONFIG_NR_DRAM_BANKS 3 @@ -265,7 +243,7 @@ "kernel_addr=0x100000\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ + "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581200000\0" \ "kernel_load=0xa0000000\0" \ @@ -278,15 +256,11 @@ "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" -#define CONFIG_BOOTDELAY 1 - -/* Store environment at top of flash */ -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_HUSH_PARSER @@ -294,10 +268,36 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ #ifndef __ASSEMBLY__ -unsigned long mc_get_dram_block_size(void); +unsigned long get_dram_size_to_hide(void); #endif +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MAX_SIZE 0x16000 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_TEXT_BASE 0x1800a000 + +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index a02d69450b..2d68e1bf7e 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -12,6 +12,12 @@ #define CONFIG_IDENT_STRING " LS2085A-EMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 + #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -19,6 +25,65 @@ #define SPD_EEPROM_ADDRESS3 0x53 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_FSL_DDR_SYNC_REFRESH + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* + * NOR Flash Timing Params + */ +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL + +/* + * This trick allows users to load MC images into DDR directly without + * copying from NOR flash. It dramatically improves speed. + */ +#define CONFIG_SYS_LS_MC_FW_IN_DDR +#define CONFIG_SYS_LS_MC_DPL_IN_DDR +#define CONFIG_SYS_LS_MC_DPC_IN_DDR + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + #endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index af34f3f95d..d0d2eedb6d 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -12,10 +12,112 @@ #define CONFIG_IDENT_STRING " LS2085A-SIMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 + /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x2210000) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) + +/* + * NOR Flash Timing Params + */ +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK @@ -25,4 +127,24 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_FW_IN_NOR +#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL + +#define CONFIG_SYS_LS_MC_DPL_IN_NOR +#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL + +#define CONFIG_SYS_LS_MC_DPC_IN_NOR +#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + #endif /* __LS2_SIMU_H */ diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h new file mode 100644 index 0000000000..711d529624 --- /dev/null +++ b/include/configs/ls2085aqds.h @@ -0,0 +1,359 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_QDS_H +#define __LS2_QDS_H + +#include "ls2085a_common.h" +#include <config_cmd_default.h> + +#define CONFIG_IDENT_STRING " LS2085A-QDS" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-QDS" + +#define CONFIG_DISPLAY_BOARDINFO + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ + +/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0x0) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (896 * 1024) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#endif + +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_FW_IN_NOR +#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL + +#define CONFIG_SYS_LS_MC_DPL_IN_NOR +#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL + +#define CONFIG_SYS_LS_MC_DPC_IN_NOR +#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* + * I2C + */ +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ + QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) +#endif + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_FSL_MEMAC +#define CONFIG_PCI /* Enable PCIE */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Initial environment variables */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x1000000\0" + +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_FSL_MEMAC +#define CONFIG_PHYLIB +#define CONFIG_PHYLIB_10G +#define CONFIG_CMD_MII +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1d +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "DPNI1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif + +#endif /* __LS2_QDS_H */ diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h new file mode 100644 index 0000000000..d1c2548a23 --- /dev/null +++ b/include/configs/ls2085ardb.h @@ -0,0 +1,305 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_RDB_H +#define __LS2_RDB_H + +#include "ls2085a_common.h" +#include <config_cmd_default.h> + +#define CONFIG_IDENT_STRING " LS2085A-RDB" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-RDB" + +#undef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 2 + +#define CONFIG_DISPLAY_BOARDINFO + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ 133333333 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x54 +#define SPD_EEPROM_ADDRESS4 0x53 /* Board error */ +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ + +/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ + FTIM0_NAND_TWP(0x30) | \ + FTIM0_NAND_TWCHT(0x0e) | \ + FTIM0_NAND_TWH(0x14)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ + FTIM1_NAND_TWBE(0xab) | \ + FTIM1_NAND_TRR(0x1c) | \ + FTIM1_NAND_TRP(0x30)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ + FTIM2_NAND_TREH(0x14) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_LBMAP_SWITCH 0x06 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RCW_SRC_NAND 0x119 +#define QIXIS_RST_FORCE_MEM 0x01 + +#define CONFIG_SYS_CSPR3_EXT (0x0) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (2048 * 1024) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SPL_PAD_TO 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x2000 +#endif + +/* Debug Server firmware */ +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_FW_IN_NOR +#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL + +#define CONFIG_SYS_LS_MC_DPL_IN_NOR +#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL + +#define CONFIG_SYS_LS_MC_DPC_IN_NOR +#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* + * I2C + */ +#define I2C_MUX_PCA_ADDR 0x77 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ + +/* I2C bus multiplexer */ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_FSL_MEMAC +#define CONFIG_PCI /* Enable PCIE */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Initial environment variables */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x1000000\0" + +#endif /* __LS2_RDB_H */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index c133ba9d03..c348d38c32 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -176,6 +176,7 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ #endif diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 5999d60146..e9096234af 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -35,7 +35,7 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index f8cd39d74d..244a9ab56b 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -42,6 +42,7 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 9b003fc4e6..7c3dc20bc3 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -48,6 +48,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index fb2072d2f0..22a9fc4bab 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -41,6 +41,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Configs */ #define CONFIG_POWER diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 3551e02276..a56e72e271 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -76,6 +76,7 @@ /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Controller */ #define CONFIG_POWER diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 3da0ef4bd0..0785491cf1 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -38,6 +38,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h new file mode 100644 index 0000000000..b569f344eb --- /dev/null +++ b/include/configs/mx6cuboxi.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the SolidRun mx6 based boards + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6CUBOXI_CONFIG_H +#define __MX6CUBOXI_CONFIG_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include "mx6_common.h" + +#define CONFIG_MX6 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_IMX6_THERMAL +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_NO_FLASH + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdtfile=undefined\0" \ + "fdt_addr_r=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-hummingboard.dtb; fi; " \ + "if test $board_name = HUMMINGBOARD && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-hummingboard.dtb; fi; " \ + "if test $board_name = CUBOXI && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-cubox-i.dtb; fi; " \ + "if test $board_name = CUBOXI && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-cubox-i.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_CACHE + +#endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 51042ca72e..22603442d7 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* NAND flash command */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 99d9d4d7cf..dab2fd2ea2 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -52,6 +52,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index dad49f96df..cd023de287 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -52,6 +52,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index a29d62f023..248303c321 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -176,6 +176,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 8ef4b733ca..eaa2c2cd36 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -63,6 +63,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID @@ -142,6 +143,9 @@ #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) #define CONFIG_BMP_16BPP #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT diff --git a/include/configs/novena.h b/include/configs/novena.h index 3809c6c59b..5f834690f3 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -141,6 +141,7 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h new file mode 100644 index 0000000000..68b401066e --- /dev/null +++ b/include/configs/omapl138_lcdk.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#undef CONFIG_USE_SPIFLASH +#undef CONFIG_SYS_USE_NOR +#define CONFIG_USE_NAND + +/* + * SoC Configuration + */ +#define CONFIG_MACH_OMAPL138_LCDK +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0xc1080000 + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 + +#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL1_PLLM 21 + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#ifdef CONFIG_USE_SPIFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 +#endif + +/* + * I2C Configuration + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 + +/* + * Flash & Environment + */ +#ifdef CONFIG_USE_NAND +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_ENV_SIZE (128 << 9) +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_NAND_BUSWIDTH_16_BIT +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#undef CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#endif + +#ifdef CONFIG_SYS_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ +#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ + + 3) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_OFFSET (256 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) +#define CONFIG_SYS_NO_FLASH +#endif + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 7 +#define CONFIG_MII +#undef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_OF_LIBFDT + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" +#define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" +#define CONFIG_BOOTDELAY 3 + +/* + * U-Boot commands + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +#ifdef CONFIG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND + +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_LZO +#define CONFIG_RBTREE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SAVEENV +#endif + +#if !defined(CONFIG_USE_NAND) && \ + !defined(CONFIG_SYS_USE_NOR) && \ + !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE (16 << 10) +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ENV +#endif + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC + +#ifdef CONFIG_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#undef CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ +#undef CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_NAND +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#endif + +#ifndef CONFIG_DIRECT_NOR_BOOT +/* defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_TEXT_BASE 0x80000000 +#define CONFIG_SPL_MAX_FOOTPRINT 32768 +#define CONFIG_SPL_PAD_TO 32768 +#endif + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + GENERATED_GBL_DATA_SIZE) +#endif /* __CONFIG_H */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 3c60b4f12b..200f40af31 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -62,6 +62,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* OCOTP Configs */ diff --git a/include/configs/platinum.h b/include/configs/platinum.h index 134bb45887..91ffc7c068 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -62,6 +62,7 @@ /* I2C config */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* MMC config */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 763a47ac3d..70718497fb 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -50,8 +50,14 @@ /* Physical address should be a function call */ #ifndef __ASSEMBLY__ extern unsigned long long get_phys_ccsrbar_addr_early(void); +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #endif -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE + +#define CONFIG_PHYS_64BIT /* Virtual address range for PCI region maps */ #define CONFIG_SYS_PCI_MAP_START 0x80000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index febbfb69f6..3bf45a224d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -21,9 +21,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_BOOTSTAGE -#define CONFIG_BOOTSTAGE_REPORT - #define CONFIG_SYS_STDIO_DEREGISTER /* Number of bits in a C 'long' on this architecture */ @@ -34,6 +31,10 @@ #define CONFIG_CMD_FDT #define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_IO + #define CONFIG_FS_FAT #define CONFIG_FAT_WRITE #define CONFIG_FS_EXT4 @@ -47,15 +48,12 @@ #define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_MD5SUM -#define CONFIG_SYS_VSNPRINTF - #define CONFIG_CMD_GPIO -#define CONFIG_SANDBOX_GPIO -#define CONFIG_SANDBOX_GPIO_COUNT 128 #define CONFIG_CMD_GPT #define CONFIG_PARTITION_UUIDS #define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION /* * Size of malloc() pool, before and after relocation @@ -75,13 +73,11 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY #define CONFIG_AUTO_COMPLETE -#define CONFIG_BOOTDELAY 3 #define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_IS_NOWHERE /* SPI - enable all SPI flash types for testing purposes */ -#define CONFIG_SANDBOX_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI @@ -90,14 +86,12 @@ #define CONFIG_SPI_FLASH_EON #define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_SANDBOX #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SANDBOX #define CONFIG_I2C_EDID #define CONFIG_I2C_EEPROM @@ -125,29 +119,42 @@ /* include default commands */ #include <config_cmd_default.h> - -/* We don't have networking support yet */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS +#include <config_distro_defaults.h> + +#define BOOT_TARGET_DEVICES(func) \ + func(HOST, host, 1) \ + func(HOST, host, 0) + +#include <config_distro_bootcmd.h> + +#define CONFIG_KEEP_SERVERADDR +#define CONFIG_UDP_CHECKSUM +#define CONFIG_CMD_LINK_LOCAL +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DNS +#define CONFIG_CMD_SNTP +#define CONFIG_TIMESTAMP +#define CONFIG_CMD_RARP +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_IP_DEFRAG + +/* Can't boot elf images */ +#undef CONFIG_CMD_ELF #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY #define CONFIG_SHA1 #define CONFIG_SHA256 -#define CONFIG_TPM_TIS_SANDBOX - #define CONFIG_CMD_SANDBOX #define CONFIG_BOOTARGS "" -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT -#define CONFIG_SOUND -#define CONFIG_SOUND_SANDBOX -#define CONFIG_CMD_SOUND - #ifndef SANDBOX_NO_SDL #define CONFIG_SANDBOX_SDL #endif @@ -165,23 +172,40 @@ #define CONFIG_KEYBOARD -#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ +#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb\0" \ "stdout=serial,lcd\0" \ "stderr=serial,lcd\0" #else - -#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \ +#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ "stdout=serial,lcd\0" \ "stderr=serial,lcd\0" #endif +#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth1addr=00:00:11:22:33:45\0" \ + "eth5addr=00:00:11:22:33:46\0" \ + "ipaddr=1.2.3.4\0" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x1000000\0" \ + "fdt_addr_r=0xc00000\0" \ + "ramdisk_addr_r=0x2000000\0" \ + "scriptaddr=0x1000\0" \ + "pxefile_addr_r=0x2000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + SANDBOX_SERIAL_SETTINGS \ + SANDBOX_ETH_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS + #define CONFIG_GZIP_COMPRESSED #define CONFIG_BZIP2 #define CONFIG_LZO #define CONFIG_LZMA -#define CONFIG_TPM_TIS_SANDBOX - #define CONFIG_CMD_LZMADEC +#define CONFIG_CMD_USB #endif diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 3b06d305db..08381e3418 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -22,7 +22,6 @@ #define CONFIG_POWER_MAX77686 #define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/snow.h b/include/configs/snow.h index fe802f253c..a2fb3f9808 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -23,10 +23,11 @@ #define CONFIG_POWER_TPS65090_I2C #define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_USB_XHCI +#define CONFIG_USB_EHCI #define CONFIG_USB_XHCI_EXYNOS +#define CONFIG_USB_EHCI_EXYNOS #define CONFIG_SYS_PROMPT "snow # " #define CONFIG_IDENT_STRING " for snow" diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6d9347204b..41bb52bc8c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) @@ -99,7 +99,6 @@ * Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define CONFIG_DESIGNWARE_ETH #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII @@ -293,6 +292,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024) #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ #define CONFIG_CRC32_VERIFY @@ -305,6 +305,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +/* + * Stack setup + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + #ifdef CONFIG_SPL_BUILD #undef CONFIG_PARTITIONS #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 16281f5ba8..409cf54172 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -18,7 +18,6 @@ /* Ethernet driver configuration */ #define CONFIG_MII -#define CONFIG_DESIGNWARE_ETH #define CONFIG_NET_MULTI #define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h new file mode 100644 index 0000000000..7f569fdac8 --- /dev/null +++ b/include/configs/stm32f429-discovery.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2015 + * Kamil Lulko, <rev13@wp.pl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_STM32F4 +#define CONFIG_STM32F4DISCOVERY +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_OF_LIBFDT + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_FLASH_BASE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_SIZE (8 << 20) +#define CONFIG_SYS_RAM_CS 1 +#define CONFIG_SYS_RAM_FREQ_DIV 2 +#define CONFIG_SYS_RAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0xD0400000 +#define CONFIG_LOADADDR 0xD0400000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET (256 << 10) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_RED_LED 110 +#define CONFIG_GREEN_LED 109 + +#define CONFIG_STM32_GPIO +#define CONFIG_STM32_SERIAL + +#define CONFIG_STM32_USART1 + +#define CONFIG_STM32_HSE_HZ 8000000 + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_MAXARGS 16 + +#define CONFIG_SYS_MALLOC_LEN (2 << 20) + +#define CONFIG_STACKSIZE (64 << 10) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttystm0,115200 earlyprintk consoleblank=0 ignore_loglevel" +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_romfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ + "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ + "bootm 0x08044000 - 0x08042000\0" + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_AUTOBOOT + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEM +#define CONFIG_CMD_MISC +#define CONFIG_CMD_TIMER + +#endif /* __CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 156e0fa8e1..ab1e61cf89 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -55,7 +55,6 @@ #define CONFIG_MII #define CONFIG_PHYLIB #define CONFIG_CMD_NET -#define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_PHY_MICREL diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1f7a1cb1f4..365d9a50b5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -196,7 +196,11 @@ #endif #define CONFIG_SYS_I2C +#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ + defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ + defined CONFIG_I2C4_ENABLE #define CONFIG_SYS_I2C_MVTWSI +#endif #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x7f @@ -284,7 +288,6 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_SUNXI_GMAC -#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ #define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 501449a581..b2b4b1037f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -62,7 +62,6 @@ /* * Ethernet configuration */ -#define CONFIG_DESIGNWARE_ETH #define ETH0_BASE_ADDRESS 0xFE100000 #define ETH1_BASE_ADDRESS 0xFE110000 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7089378c96..3a88f22bbf 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -199,6 +199,7 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID #endif diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 7957a73384..f2be8d583e 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -144,13 +144,20 @@ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ DFUARGS \ + #define CONFIG_BOOTCOMMAND \ + "if test ${dofastboot} -eq 1; then " \ + "echo Boot fastboot requested, resetting dofastboot ...;" \ + "setenv dofastboot 0; saveenv;" \ + "echo Booting into fastboot ...; fastboot;" \ + "fi;" \ "run findfdt; " \ "run mmcboot;" \ "setenv mmcdev 1; " \ "setenv bootpart 1:2; " \ "setenv mmcroot /dev/mmcblk0p2 rw; " \ "run mmcboot;" \ + "" /* diff --git a/include/configs/titanium.h b/include/configs/titanium.h index f9e00c5b8b..320d76cac6 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -44,6 +44,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* MMC Configs */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a099687d46..012fa1c242 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -35,16 +35,6 @@ #define PHYS_SDRAM_SIZE (1024u * SZ_1M) #endif -#if defined(CONFIG_MBA6) - -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) -#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" -#endif - -#endif - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_GENERIC_BOARD @@ -80,16 +70,12 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 /* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 -#if defined(CONFIG_MBA6) -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif #define CONFIG_DTT_MAX_TEMP 70 #define CONFIG_DTT_MIN_TEMP -30 #define CONFIG_DTT_HYSTERESIS 3 @@ -147,38 +133,12 @@ #define CONFIG_PHYLIB #define CONFIG_MII -#if defined(CONFIG_MBA6) - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_FEC_MXC_PHYADDR 0x03 -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_KSZ9031 - -#else - -#error "define PHY to use for your baseboard" - -#endif - #define CONFIG_ARP_TIMEOUT 200UL /* Network config - Allow larger/faster download for TFTP/NFS */ #define CONFIG_IP_DEFRAG #define CONFIG_TFTP_BLOCKSIZE 4096 #define CONFIG_NFS_READ_SIZE 4096 -#if defined(CONFIG_MBA6) - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_CONSOLE_DEV "ttymxc1" - -#else - -#error "define baseboard specific things (uart, number of SD-card slots)" - -#endif - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -492,4 +452,20 @@ #define CONFIG_CMD_CACHE #endif +/* + * All the defines above are for the TQMa6 SoM + * + * Now include the baseboard specific configuration + */ +#ifdef CONFIG_MBA6 +#include "tqma6_mba6.h" +#else +#error "No baseboard for the TQMa6 defined!" +#endif + +/* Support at least the sensor on TQMa6 SOM */ +#if !defined(CONFIG_DTT_SENSORS) +#define CONFIG_DTT_SENSORS { 0 } +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h new file mode 100644 index 0000000000..88c00679b6 --- /dev/null +++ b/include/configs/tqma6_mba6.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * + * Configuration settings for the TQ Systems TQMa6<Q,S> module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TQMA6_MBA6_H +#define __CONFIG_TQMA6_MBA6_H + +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" +#endif + +#define CONFIG_DTT_SENSORS { 0, 1 } + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index a6c7d5f136..1e41a12a6c 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -23,6 +23,8 @@ #define CONFIG_HW_WATCHDOG #define CONFIG_OMAP_WATCHDOG #define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT /* Bootcount using the RTC block */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 #define CONFIG_BOOTCOUNT_LIMIT @@ -103,15 +105,16 @@ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandimgsize=0x500000\0" \ - "nandboot=echo Booting from nand ...; " \ + "root=mtd6 " \ + "rootfstype=jffs2\0" \ + "kernelsize=0x400000\0" \ + "nandboot=echo booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} kernel ${nandimgsize}; " \ - "bootz ${loadaddr}\0" + "nand read ${loadaddr} kernel ${kernelsize}; " \ + "bootz ${loadaddr} - ${dtbaddr}\0" \ + "defboot=run nandboot\0" \ + "bootlimit=1\0" \ + "altbootcmd=run usbscript\0" #else #define NANDARGS "" #endif /* CONFIG_NAND */ @@ -231,15 +234,15 @@ MMCARGS #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ - "128k(SPL)," \ - "128k(SPL.backup1)," \ - "128k(SPL.backup2)," \ - "128k(SPL.backup3)," \ - "512k(u-boot)," \ - "128k(u-boot-spl-os)," \ + "128k(MLO)," \ + "128k(MLO.backup)," \ + "128k(dtb)," \ "128k(u-boot-env)," \ - "5m(kernel),"\ - "-(rootfs)" + "512k(u-boot)," \ + "4m(kernel),"\ + "128m(rootfs),"\ + "-(user)" +#define CONFIG_NAND_OMAP_GPMC_WSCFG 1 #endif /* CONFIG_NAND */ /* USB configuration */ @@ -298,7 +301,7 @@ MMCARGS #else #define CONFIG_ENV_IS_IN_NAND #endif -#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE #else #error "no storage for Environment defined!" diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 3fda20a8f6..032010bb9e 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -8,10 +8,9 @@ #ifndef __VEXPRESS_AEMV8A_H #define __VEXPRESS_AEMV8A_H -#define CONFIG_DM - -/* We use generic board for v8 Versatile Express */ +/* We use generic board and device manager for v8 Versatile Express */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #ifndef CONFIG_SEMIHOSTING @@ -134,27 +133,16 @@ #endif /* PL011 Serial Configuration */ -#define CONFIG_BAUDRATE 115200 -#ifdef CONFIG_DM #define CONFIG_DM_SERIAL -#define CONFIG_PL01X_SERIAL -#else -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_INDEX 0 +#define CONFIG_PL01X_SERIAL #define CONFIG_PL011_SERIAL #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_PL011_CLOCK 7273800 #else #define CONFIG_PL011_CLOCK 24000000 #endif -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 /* Command line configuration */ #define CONFIG_MENU diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b586803916..b2c36148ba 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -62,6 +62,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 /* MMC Configuration */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 48b869268b..d0895cfdac 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -47,6 +47,7 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/x600.h b/include/configs/x600.h index 241bf65f30..27a66a53e8 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -74,7 +74,6 @@ /* Ethernet config options */ #define CONFIG_MII -#define CONFIG_DESIGNWARE_ETH #define CONFIG_NET_MULTI #define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h new file mode 100644 index 0000000000..b6a76fe075 --- /dev/null +++ b/include/configs/x86-chromebook.h @@ -0,0 +1,68 @@ +/* + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_CHROMEBOOK_H +#define _X86_CHROMEBOOK_H + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512 + +#define CONFIG_X86_SERIAL + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} + +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index b7dd63e060..9571c656be 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -16,7 +16,6 @@ * (easy to change) */ #define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_SYS_VSNPRINTF #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -204,7 +203,6 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI -#define CONFIG_OF_SPI_FLASH /*----------------------------------------------------------------------- * Environment configuration @@ -238,9 +236,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTSTAGE -#define CONFIG_CMD_BOOTSTAGE - #define CONFIG_CMD_USB /* Default environment */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 511ecca0b8..880d29ca71 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -36,7 +36,7 @@ #define CPU_RELEASE_ADDR 0xFFFFFF0 /* Cache Definitions */ -#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_IDENT_STRING " Xilinx ZynqMP" @@ -61,13 +61,25 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_ZYNQ_SDHCI0 + /* Command line configuration */ #define CONFIG_CMD_ENV #define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT4 #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_MEMORY #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_ELF +#define CONFIG_MP + +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -90,8 +102,8 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \ - "fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" + "sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \ + "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" #define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ "earlycon=cdns,mmio,0xff000000,${baudrate}n8" @@ -117,6 +129,29 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_SYS_I2C_ZYNQ + +/* I2C */ +#if defined(CONFIG_SYS_I2C_ZYNQ) +# define CONFIG_CMD_I2C +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 +#endif + +#define CONFIG_ZYNQMP_EEPROM + +/* EEPROM */ +#ifdef CONFIG_ZYNQMP_EEPROM +# define CONFIG_CMD_EEPROM +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +# define CONFIG_SYS_EEPROM_SIZE (64 * 1024) +#endif + #define CONFIG_FIT #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index a7c6dce1c4..926b381580 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -38,6 +38,9 @@ # define CONFIG_ZYNQ_SERIAL #endif +#define CONFIG_ZYNQ_GPIO +#define CONFIG_CMD_GPIO + /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) # define CONFIG_NET_MULTI @@ -290,7 +293,7 @@ # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif -#define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds" +#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" /* Commands */ #include <config_cmd_default.h> @@ -308,7 +311,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds" /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI0 diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h new file mode 100644 index 0000000000..d116e05ac7 --- /dev/null +++ b/include/configs/zynq_picozed.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 Xilinx, Inc. + * + * Configuration for PicoZed + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_PICOZED_H +#define __CONFIG_ZYNQ_PICOZED_H + +#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_ZYNQ_USB +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include <configs/zynq-common.h> + +#endif /* __CONFIG_ZYNQ_PICOZED_H */ diff --git a/include/cros_ec.h b/include/cros_ec.h index 8457c80c5e..3b2be2c2fa 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -15,31 +15,9 @@ #include <cros_ec_message.h> #include <asm/gpio.h> -#ifndef CONFIG_DM_CROS_EC -/* Which interface is the device on? */ -enum cros_ec_interface_t { - CROS_EC_IF_NONE, - CROS_EC_IF_SPI, - CROS_EC_IF_I2C, - CROS_EC_IF_LPC, /* Intel Low Pin Count interface */ - CROS_EC_IF_SANDBOX, -}; -#endif - /* Our configuration information */ struct cros_ec_dev { -#ifdef CONFIG_DM_CROS_EC struct udevice *dev; /* Transport device */ -#else - enum cros_ec_interface_t interface; - struct spi_slave *spi; /* Our SPI slave, if using SPI */ - int node; /* Our node */ - int parent_node; /* Our parent node (interface) */ - unsigned int cs; /* Our chip select */ - unsigned int addr; /* Device address (for I2C) */ - unsigned int bus_num; /* Bus number (for I2C) */ - unsigned int max_frequency; /* Maximum interface frequency */ -#endif struct gpio_desc ec_int; /* GPIO used as EC interrupt line */ int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ @@ -240,8 +218,6 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, */ struct cros_ec_dev *board_get_cros_ec_dev(void); -#ifdef CONFIG_DM_CROS_EC - struct dm_cros_ec_ops { int (*check_version)(struct udevice *dev); int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version, @@ -255,112 +231,6 @@ struct dm_cros_ec_ops { int cros_ec_register(struct udevice *dev); -#else /* !CONFIG_DM_CROS_EC */ - -/* Internal interfaces */ -int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob); -int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the i2c cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the spi cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Read information from the fdt for the sandbox cros_ec interface - * - * @param dev CROS-EC device - * @param blob Device tree blob - * @return 0 if ok, -1 if we failed to read all required information - */ -int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob); - -/** - * Check whether the LPC interface supports new-style commands. - * - * LPC has its own way of doing this, which involves checking LPC values - * visible to the host. Do this, and update dev->protocol_version accordingly. - * - * @param dev CROS-EC device to check - */ -int cros_ec_lpc_check_version(struct cros_ec_dev *dev); - -/** - * Send a command to an I2C CROS-EC device and return the reply. - * - * This rather complicated function deals with sending both old-style and - * new-style commands. The old ones have just a command byte and arguments. - * The new ones have version, command, arg-len, [args], chksum so are 3 bytes - * longer. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS-EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Returns pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -/** - * Send a command to a LPC CROS-EC device and return the reply. - * - * The device's internal input/output buffers are used. - * - * @param dev CROS-EC device - * @param cmd Command to send (EC_CMD_...) - * @param cmd_version Version of command to send (EC_VER_...) - * @param dout Output data (may be NULL If dout_len=0) - * @param dout_len Size of output data in bytes - * @param dinp Returns pointer to response data - * @param din_len Maximum size of response in bytes - * @return number of bytes in response, or -1 on error - */ -int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, - const uint8_t *dout, int dout_len, - uint8_t **dinp, int din_len); - -/** - * Send a packet to a CROS-EC device and return the response packet. - * - * Expects the request packet to be stored in dev->dout. Stores the response - * packet in dev->din. - * - * @param dev CROS-EC device - * @param out_bytes Size of request packet to output - * @param in_bytes Maximum size of response packet to receive - * @return number of bytes in response packet, or <0 on error - */ -int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); -int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, - int in_bytes); -#endif - /** * Dump a block of data for a command. * @@ -493,13 +363,6 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state); int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state); /** - * Initialize the Chrome OS EC at board initialization time. - * - * @return 0 if ok, -ve on error - */ -int cros_ec_board_init(void); - -/** * Get access to the error reported when cros_ec_board_init() was called * * This permits delayed reporting of the EC error if it failed during diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index e2418fedb9..687462b093 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -34,7 +34,7 @@ struct udevice; * @devp: Returns a pointer to the bound device * @return 0 if OK, -ve on error */ -int device_bind(struct udevice *parent, struct driver *drv, +int device_bind(struct udevice *parent, const struct driver *drv, const char *name, void *platdata, int of_offset, struct udevice **devp); diff --git a/include/dm/device.h b/include/dm/device.h index 7a48eb88b8..18296bb686 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -30,6 +30,12 @@ struct driver_info; /* DM is responsible for allocating and freeing parent_platdata */ #define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3) +/* DM is responsible for allocating and freeing uclass_platdata */ +#define DM_FLAG_ALLOC_UCLASS_PDATA (1 << 4) + +/* Allocate driver private data on a DMA boundary */ +#define DM_FLAG_ALLOC_PRIV_DMA (1 << 5) + /** * struct udevice - An instance of a driver * @@ -51,8 +57,10 @@ struct driver_info; * @name: Name of device, typically the FDT node name * @platdata: Configuration data for this device * @parent_platdata: The parent bus's configuration data for this device + * @uclass_platdata: The uclass's configuration data for this device * @of_offset: Device tree node offset for this device (- for none) - * @of_id: Pointer to the udevice_id structure which created the device + * @driver_data: Driver data word for the entry that matched this device with + * its driver * @parent: Parent of this device, or NULL for the top level device * @priv: Private data for this device * @uclass: Pointer to uclass for this device @@ -67,12 +75,13 @@ struct driver_info; * when the device is probed and will be unique within the device's uclass. */ struct udevice { - struct driver *driver; + const struct driver *driver; const char *name; void *platdata; void *parent_platdata; + void *uclass_platdata; int of_offset; - const struct udevice_id *of_id; + ulong driver_data; struct udevice *parent; void *priv; struct uclass *uclass; @@ -206,6 +215,16 @@ void *dev_get_platdata(struct udevice *dev); void *dev_get_parent_platdata(struct udevice *dev); /** + * dev_get_uclass_platdata() - Get the uclass platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return uclass's platform data, or NULL if none + */ +void *dev_get_uclass_platdata(struct udevice *dev); + +/** * dev_get_parentdata() - Get the parent data for a device * * The parent data is data stored in the device but owned by the parent. @@ -238,13 +257,39 @@ void *dev_get_priv(struct udevice *dev); struct udevice *dev_get_parent(struct udevice *child); /** - * dev_get_of_data() - get the device tree data used to bind a device + * dev_get_uclass_priv() - Get the private uclass data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return private uclass data for this device, or NULL if none + */ +void *dev_get_uclass_priv(struct udevice *dev); + +/** + * dev_get_driver_data() - get the driver data used to bind a device * * When a device is bound using a device tree node, it matches a * particular compatible string as in struct udevice_id. This function - * returns the associated data value for that compatible string + * returns the associated data value for that compatible string. This is + * the 'data' field in struct udevice_id. + * + * For USB devices, this is the driver_info field in struct usb_device_id. + * + * @dev: Device to check */ -ulong dev_get_of_data(struct udevice *dev); +ulong dev_get_driver_data(struct udevice *dev); + +/** + * dev_get_driver_ops() - get the device's driver's operations + * + * This checks that dev is not NULL, and returns the pointer to device's + * driver's operations. + * + * @dev: Device to check + * @return void pointer to driver's operations or NULL for NULL-dev or NULL-ops + */ +const void *dev_get_driver_ops(struct udevice *dev); /* * device_get_uclass_id() - return the uclass ID of a device @@ -254,6 +299,16 @@ ulong dev_get_of_data(struct udevice *dev); */ enum uclass_id device_get_uclass_id(struct udevice *dev); +/* + * dev_get_uclass_name() - return the uclass name of a device + * + * This checks that dev is not NULL. + * + * @dev: Device to check + * @return pointer to the uclass name for the device + */ +const char *dev_get_uclass_name(struct udevice *dev); + /** * device_get_child() - Get the child of a device by index * @@ -361,4 +416,34 @@ int device_find_next_child(struct udevice **devp); */ fdt_addr_t dev_get_addr(struct udevice *dev); +/** + * device_has_children() - check if a device has any children + * + * @dev: Device to check + * @return true if the device has one or more children + */ +bool device_has_children(struct udevice *dev); + +/** + * device_has_active_children() - check if a device has any active children + * + * @dev: Device to check + * @return true if the device has one or more children and at least one of + * them is active (probed). + */ +bool device_has_active_children(struct udevice *dev); + +/** + * device_is_last_sibling() - check if a device is the last sibling + * + * This function can be useful for display purposes, when special action needs + * to be taken when displaying the last sibling. This can happen when a tree + * view of devices is being displayed. + * + * @dev: Device to check + * @return true if there are no more siblings after this one - i.e. is it + * last in the list. + */ +bool device_is_last_sibling(struct udevice *dev); + #endif diff --git a/include/dm/test.h b/include/dm/test.h index 707c69e07f..f03fbcb1cd 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -44,6 +44,7 @@ enum { /* For uclass */ DM_TEST_OP_POST_BIND, DM_TEST_OP_PRE_UNBIND, + DM_TEST_OP_PRE_PROBE, DM_TEST_OP_POST_PROBE, DM_TEST_OP_PRE_REMOVE, DM_TEST_OP_INIT, @@ -97,6 +98,26 @@ struct dm_test_parent_data { int flag; }; +/* Test values for test device's uclass platform data */ +enum { + TEST_UC_PDATA_INTVAL1 = 2, + TEST_UC_PDATA_INTVAL2 = 334, + TEST_UC_PDATA_INTVAL3 = 789452, +}; + +/** + * struct dm_test_uclass_platda - uclass's information on each device + * + * @intval1: set to TEST_UC_PDATA_INTVAL1 in .post_bind method of test uclass + * @intval2: set to TEST_UC_PDATA_INTVAL2 in .post_bind method of test uclass + * @intval3: set to TEST_UC_PDATA_INTVAL3 in .post_bind method of test uclass + */ +struct dm_test_perdev_uc_pdata { + int intval1; + int intval2; + int intval3; +}; + /* * Operation counts for the test driver, used to check that each method is * called correctly @@ -204,12 +225,13 @@ void dm_leak_check_start(struct dm_test_state *dms); /** - * dm_test_main() - Run all the tests + * dm_test_main() - Run all or one of the tests * - * This runs all available driver model tests + * This runs all available driver model tests, or a selected one * + * @test_name: Name of test to run, or NULL for all * @return 0 if OK, -ve on error */ -int dm_test_main(void); +int dm_test_main(const char *test_name); #endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 91bb90dcfb..fddfd35f1f 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -20,6 +20,8 @@ enum uclass_id { UCLASS_TEST_BUS, UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ + UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ + UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ UCLASS_SIMPLE_BUS, /* U-Boot uclasses start here */ @@ -34,6 +36,15 @@ enum uclass_id { UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_PCI, /* PCI bus */ + UCLASS_PCI_GENERIC, /* Generic PCI bus device */ + UCLASS_PCH, /* x86 platform controller hub */ + UCLASS_ETH, /* Ethernet device */ + UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_USB, /* USB bus */ + UCLASS_USB_HUB, /* USB hub */ + UCLASS_USB_DEV_GENERIC, /* USB generic device */ + UCLASS_MASS_STORAGE, /* Mass storage device */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index f2f254a825..9b68508667 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -11,12 +11,25 @@ #define _DM_UCLASS_INTERNAL_H /** + * uclass_get_device_tail() - handle the end of a get_device call + * + * This handles returning an error or probing a device as needed. + * + * @dev: Device that needs to be probed + * @ret: Error to return. If non-zero then the device is not probed + * @devp: Returns the value of 'dev' if there is no error + * @return ret, if non-zero, else the result of the device_probe() call + */ +int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp); + +/** * uclass_find_device() - Return n-th child of uclass * @id: Id number of the uclass * @index: Position of the child in uclass's list * #devp: Returns pointer to device, or NULL on error * - * The device is not prepared for use - this is an internal function + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. * * @return the uclass pointer of a child at the given index or * return NULL on error. @@ -24,6 +37,68 @@ int uclass_find_device(enum uclass_id id, int index, struct udevice **devp); /** + * uclass_find_first_device() - Return the first device in a uclass + * @id: Id number of the uclass + * #devp: Returns pointer to device, or NULL on error + * + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. + * + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_find_first_device(enum uclass_id id, struct udevice **devp); + +/** + * uclass_find_next_device() - Return the next device in a uclass + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the same uclass, or NULL if none + * + * The device is not prepared for use - this is an internal function. + * The function uclass_get_device_tail() can be used to probe the device. + * + * @return 0 if OK (found or not found), -1 on error + */ +int uclass_find_next_device(struct udevice **devp); + +/** + * uclass_find_device_by_name() - Find uclass device based on ID and name + * + * This searches for a device with the exactly given name. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @name: name of a device to find + * @devp: Returns pointer to device (the first one with the name) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_name(enum uclass_id id, const char *name, + struct udevice **devp); + +/** + * uclass_find_device_by_seq() - Find uclass device based on ID and sequence + * + * This searches for a device with the given seq or req_seq. + * + * For seq, if an active device has this sequence it will be returned. + * If there is no such device then this will return -ENODEV. + * + * For req_seq, if a device (whether activated or not) has this req_seq + * value, that device will be returned. This is a strong indication that + * the device will receive that sequence when activated. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @seq_or_req_seq: Sequence number to find (0=first) + * @find_req_seq: true to find req_seq, false to find seq + * @devp: Returns pointer to device (there is only one per for each seq) + * @return 0 if OK, -ve on error + */ +int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, + bool find_req_seq, struct udevice **devp); + +/** * uclass_bind_device() - Associate device with a uclass * * Connect the device into uclass's list of devices. @@ -41,18 +116,23 @@ int uclass_bind_device(struct udevice *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ +#ifdef CONFIG_DM_DEVICE_REMOVE int uclass_unbind_device(struct udevice *dev); +#else +static inline int uclass_unbind_device(struct udevice *dev) { return 0; } +#endif /** - * uclass_pre_probe_child() - Deal with a child that is about to be probed + * uclass_pre_probe_device() - Deal with a device that is about to be probed * * Perform any pre-processing that is needed by the uclass before it can be - * probed. + * probed. This includes the uclass' pre-probe() method and the parent + * uclass' child_pre_probe() method. * * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_pre_probe_child(struct udevice *dev); +int uclass_pre_probe_device(struct udevice *dev); /** * uclass_post_probe_device() - Deal with a device that has just been probed @@ -73,7 +153,11 @@ int uclass_post_probe_device(struct udevice *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ +#ifdef CONFIG_DM_DEVICE_REMOVE int uclass_pre_remove_device(struct udevice *dev); +#else +static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; } +#endif /** * uclass_find() - Find uclass by its id @@ -93,27 +177,4 @@ struct uclass *uclass_find(enum uclass_id key); */ int uclass_destroy(struct uclass *uc); -/** - * uclass_find_device_by_seq() - Find uclass device based on ID and sequence - * - * This searches for a device with the given seq or req_seq. - * - * For seq, if an active device has this sequence it will be returned. - * If there is no such device then this will return -ENODEV. - * - * For req_seq, if a device (whether activated or not) has this req_seq - * value, that device will be returned. This is a strong indication that - * the device will receive that sequence when activated. - * - * The device is NOT probed, it is merely returned. - * - * @id: ID to look up - * @seq_or_req_seq: Sequence number to find (0=first) - * @find_req_seq: true to find req_seq, false to find seq - * @devp: Returns pointer to device (there is only one per for each seq) - * @return 0 if OK, -ve on error - */ -int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, - bool find_req_seq, struct udevice **devp); - #endif diff --git a/include/dm/uclass.h b/include/dm/uclass.h index d6c40c60dd..4cfc0df84c 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -53,6 +53,7 @@ struct udevice; * @id: ID number of this uclass * @post_bind: Called after a new device is bound to this uclass * @pre_unbind: Called before a device is unbound from this uclass + * @pre_probe: Called before a new device is probed * @post_probe: Called after a new device is probed * @pre_remove: Called before a device is removed * @child_post_bind: Called after a child is bound to a device in this uclass @@ -64,6 +65,9 @@ struct udevice; * @per_device_auto_alloc_size: Each device can hold private data owned * by the uclass. If required this will be automatically allocated if this * value is non-zero. + * @per_device_platdata_auto_alloc_size: Each device can hold platform data + * owned by the uclass as 'dev->uclass_platdata'. If the value is non-zero, + * then this will be automatically allocated. * @per_child_auto_alloc_size: Each child device (of a parent in this * uclass) can hold parent data for the device/uclass. This value is only * used as a falback if this member is 0 in the driver. @@ -80,6 +84,7 @@ struct uclass_driver { enum uclass_id id; int (*post_bind)(struct udevice *dev); int (*pre_unbind)(struct udevice *dev); + int (*pre_probe)(struct udevice *dev); int (*post_probe)(struct udevice *dev); int (*pre_remove)(struct udevice *dev); int (*child_post_bind)(struct udevice *dev); @@ -88,6 +93,7 @@ struct uclass_driver { int (*destroy)(struct uclass *class); int priv_auto_alloc_size; int per_device_auto_alloc_size; + int per_device_platdata_auto_alloc_size; int per_child_auto_alloc_size; int per_child_platdata_auto_alloc_size; const void *ops; @@ -124,6 +130,21 @@ int uclass_get(enum uclass_id key, struct uclass **ucp); int uclass_get_device(enum uclass_id id, int index, struct udevice **devp); /** + * uclass_get_device_by_name() - Get a uclass device by it's name + * + * This searches the devices in the uclass for one with the exactly given name. + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @name: name of a device to get + * @devp: Returns pointer to device (the first one with the name) + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_name(enum uclass_id id, const char *name, + struct udevice **devp); + +/** * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence * * If an active device has this sequence it will be returned. If there is no diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h index cf389dac69..3969a6a066 100644 --- a/include/exynos_lcd.h +++ b/include/exynos_lcd.h @@ -25,6 +25,7 @@ enum exynos_fb_rgb_mode_t { typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ ushort vl_width; /* Width of display area in millimeters */ ushort vl_height; /* Height of display area in millimeters */ diff --git a/include/fdt_support.h b/include/fdt_support.h index ae5e8a3ef6..5d4f28dc78 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -47,6 +47,19 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); void fdt_fixup_qe_firmware(void *fdt); +/** + * Update native-mode property of display-timings node to the phandle + * of the timings matching a display by name (case insensitive). + * + * see kernel Documentation/devicetree/bindings/video/display-timing.txt + * + * @param blob FDT blob to update + * @param path path within dt + * @param display name of display timing to match + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_fixup_display(void *blob, const char *path, const char *display); + #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) void fdt_fixup_dr_usb(void *blob, bd_t *bd); #else diff --git a/include/fdtdec.h b/include/fdtdec.h index 11a7b86007..659047097a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -41,6 +41,16 @@ struct fdt_memory { fdt_addr_t end; }; +#ifdef CONFIG_OF_CONTROL +# if defined(CONFIG_SPL_BUILD) && defined(SPL_DISABLE_OF_CONTROL) +# define OF_CONTROL 0 +# else +# define OF_CONTROL 1 +# endif +#else +# define OF_CONTROL 0 +#endif + /* * Information about a resource. start is the first address of the resource * and end is the last address (inclusive). The length of the resource will @@ -134,7 +144,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */ COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ COMPAT_SAMSUNG_EXYNOS5_XHCI, /* Exynos5 XHCI controller */ @@ -153,13 +162,11 @@ enum fdt_compat_id { COMPAT_INFINEON_SLB9635_TPM, /* Infineon SLB9635 TPM */ COMPAT_INFINEON_SLB9645_TPM, /* Infineon SLB9645 TPM */ COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ - COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */ COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */ COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */ COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ - COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ COMPAT_MEMORY_SPD, /* Memory SPD information */ COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ @@ -169,6 +176,7 @@ enum fdt_compat_id { COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ + COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_COUNT, }; @@ -327,7 +335,9 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, * @param type pci address type (FDT_PCI_SPACE_xxx) * @param prop_name name of property to find * @param addr returns pci address in the form of fdt_pci_addr - * @return 0 if ok, negative on error + * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the + * format of the property was invalid, -ENXIO if the requested + * address type was not found */ int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, const char *prop_name, struct fdt_pci_addr *addr); @@ -389,6 +399,17 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val); /** + * Get a variable-sized number from a property + * + * This reads a number from one or more cells. + * + * @param ptr Pointer to property + * @param cells Number of cells containing the number + * @return the value in the cells + */ +u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells); + +/** * Look up a 64-bit integer property in a node and return it. The property * must have at least 8 bytes of data (2 cells). The first two cells are * concatenated to form a 8 bytes value, where the first cell is top half and @@ -782,4 +803,10 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property, int fdtdec_decode_memory_region(const void *blob, int node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep); + +/** + * Set up the device tree ready for use + */ +int fdtdec_setup(void); + #endif diff --git a/include/flash.h b/include/flash.h index 30aa080b88..48aa3a5f8e 100644 --- a/include/flash.h +++ b/include/flash.h @@ -459,6 +459,8 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ #define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ +#define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */ + #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ diff --git a/include/fsl-mc/fsl_dpaa_fd.h b/include/fsl-mc/fsl_dpaa_fd.h new file mode 100644 index 0000000000..6d0ffa8265 --- /dev/null +++ b/include/fsl-mc/fsl_dpaa_fd.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_DPAA_FD_H +#define __FSL_DPAA_FD_H + +/* Place-holder for FDs, we represent it via the simplest form that we need for + * now. Different overlays may be needed to support different options, etc. (It + * is impractical to define One True Struct, because the resulting encoding + * routines (lots of read-modify-writes) would be worst-case performance whether + * or not circumstances required them.) */ +struct dpaa_fd { + union { + u32 words[8]; + struct dpaa_fd_simple { + u32 addr_lo; + u32 addr_hi; + u32 len; + /* offset in the MS 16 bits, BPID in the LS 16 bits */ + u32 bpid_offset; + u32 frc; /* frame context */ + /* "err", "va", "cbmt", "asal", [...] */ + u32 ctrl; + /* flow context */ + u32 flc_lo; + u32 flc_hi; + } simple; + }; +}; + +enum dpaa_fd_format { + dpaa_fd_single = 0, + dpaa_fd_list, + dpaa_fd_sg +}; + +static inline u64 ldpaa_fd_get_addr(const struct dpaa_fd *fd) +{ + return (u64)((((uint64_t)fd->simple.addr_hi) << 32) + + fd->simple.addr_lo); +} + +static inline void ldpaa_fd_set_addr(struct dpaa_fd *fd, u64 addr) +{ + fd->simple.addr_hi = upper_32_bits(addr); + fd->simple.addr_lo = lower_32_bits(addr); +} + +static inline u32 ldpaa_fd_get_len(const struct dpaa_fd *fd) +{ + return fd->simple.len; +} + +static inline void ldpaa_fd_set_len(struct dpaa_fd *fd, u32 len) +{ + fd->simple.len = len; +} + +static inline uint16_t ldpaa_fd_get_offset(const struct dpaa_fd *fd) +{ + return (uint16_t)(fd->simple.bpid_offset >> 16) & 0x0FFF; +} + +static inline void ldpaa_fd_set_offset(struct dpaa_fd *fd, uint16_t offset) +{ + fd->simple.bpid_offset &= 0xF000FFFF; + fd->simple.bpid_offset |= (u32)offset << 16; +} + +static inline uint16_t ldpaa_fd_get_bpid(const struct dpaa_fd *fd) +{ + return (uint16_t)(fd->simple.bpid_offset & 0xFFFF); +} + +static inline void ldpaa_fd_set_bpid(struct dpaa_fd *fd, uint16_t bpid) +{ + fd->simple.bpid_offset &= 0xFFFF0000; + fd->simple.bpid_offset |= (u32)bpid; +} + +/* When frames are dequeued, the FDs show up inside "dequeue" result structures + * (if at all, not all dequeue results contain valid FDs). This structure type + * is intentionally defined without internal detail, and the only reason it + * isn't declared opaquely (without size) is to allow the user to provide + * suitably-sized (and aligned) memory for these entries. */ +struct ldpaa_dq { + uint32_t dont_manipulate_directly[16]; +}; + +/* Parsing frame dequeue results */ +#define LDPAA_DQ_STAT_FQEMPTY 0x80 +#define LDPAA_DQ_STAT_HELDACTIVE 0x40 +#define LDPAA_DQ_STAT_FORCEELIGIBLE 0x20 +#define LDPAA_DQ_STAT_VALIDFRAME 0x10 +#define LDPAA_DQ_STAT_ODPVALID 0x04 +#define LDPAA_DQ_STAT_VOLATILE 0x02 +#define LDPAA_DQ_STAT_EXPIRED 0x01 +uint32_t ldpaa_dq_flags(const struct ldpaa_dq *); +static inline int ldpaa_dq_is_pull(const struct ldpaa_dq *dq) +{ + return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_VOLATILE); +} +static inline int ldpaa_dq_is_pull_complete( + const struct ldpaa_dq *dq) +{ + return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_EXPIRED); +} +/* seqnum/odpid are valid only if VALIDFRAME and ODPVALID flags are TRUE */ +uint16_t ldpaa_dq_seqnum(const struct ldpaa_dq *); +uint16_t ldpaa_dq_odpid(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqid(const struct ldpaa_dq *); +uint32_t ldpaa_dq_byte_count(const struct ldpaa_dq *); +uint32_t ldpaa_dq_frame_count(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqd_ctx_hi(const struct ldpaa_dq *); +uint32_t ldpaa_dq_fqd_ctx_lo(const struct ldpaa_dq *); +/* get the Frame Descriptor */ +const struct dpaa_fd *ldpaa_dq_fd(const struct ldpaa_dq *); + +#endif /* __FSL_DPAA_FD_H */ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h new file mode 100644 index 0000000000..7f0075c71f --- /dev/null +++ b/include/fsl-mc/fsl_dpbp.h @@ -0,0 +1,143 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Author: German Rivera <German.Rivera@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/*! + * @file fsl_dpbp.h + * @brief Data Path Buffer Pool API + */ +#ifndef __FSL_DPBP_H +#define __FSL_DPBP_H + +/* DPBP Version */ +#define DPBP_VER_MAJOR 2 +#define DPBP_VER_MINOR 0 + +/* Command IDs */ +#define DPBP_CMDID_CLOSE 0x800 +#define DPBP_CMDID_OPEN 0x804 + +#define DPBP_CMDID_ENABLE 0x002 +#define DPBP_CMDID_DISABLE 0x003 +#define DPBP_CMDID_GET_ATTR 0x004 +#define DPBP_CMDID_RESET 0x005 + +/* cmd, param, offset, width, type, arg_name */ +#define DPBP_CMD_OPEN(cmd, dpbp_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ + MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ +} while (0) + +/* Data Path Buffer Pool API + * Contains initialization APIs and runtime control APIs for DPBP + */ + +struct fsl_mc_io; + +/** + * dpbp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @dpbp_id: DPBP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpbp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_open(struct fsl_mc_io *mc_io, int dpbp_id, uint16_t *token); + +/** + * dpbp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPBP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_close(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpbp_enable() - Enable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ + +int dpbp_enable(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpbp_disable() - Disable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_disable(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpbp_reset() - Reset the DPBP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_reset(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * struct dpbp_attr - Structure representing DPBP attributes + * @id: DPBP object ID + * @version: DPBP version + * @bpid: Hardware buffer pool ID; should be used as an argument in + * acquire/release operations on buffers + */ +struct dpbp_attr { + int id; + /** + * struct version - Structure representing DPBP version + * @major: DPBP major version + * @minor: DPBP minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; + uint16_t bpid; +}; + + +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_attributes(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpbp_attr *attr); + +/** @} */ + +#endif /* __FSL_DPBP_H */ diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h new file mode 100644 index 0000000000..e84b419afe --- /dev/null +++ b/include/fsl-mc/fsl_dpio.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_DPIO_H +#define _FSL_DPIO_H + +/* DPIO Version */ +#define DPIO_VER_MAJOR 2 +#define DPIO_VER_MINOR 1 + +/* Command IDs */ +#define DPIO_CMDID_CLOSE 0x800 +#define DPIO_CMDID_OPEN 0x803 + +#define DPIO_CMDID_ENABLE 0x002 +#define DPIO_CMDID_DISABLE 0x003 +#define DPIO_CMDID_GET_ATTR 0x004 +#define DPIO_CMDID_RESET 0x005 + +/* cmd, param, offset, width, type, arg_name */ +#define DPIO_CMD_OPEN(cmd, dpio_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPIO_RSP_GET_ATTR(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ + MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ + MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_paddr);\ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_paddr);\ + MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ +} while (0) + +/* Data Path I/O Portal API + * Contains initialization APIs and runtime control APIs for DPIO + */ + +struct fsl_mc_io; +/** + * dpio_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @dpio_id: DPIO unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpio_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_open(struct fsl_mc_io *mc_io, int dpio_id, uint16_t *token); + +/** + * dpio_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @dpio_id: DPIO unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpio_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_close(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * enum dpio_channel_mode - DPIO notification channel mode + * @DPIO_NO_CHANNEL: No support for notification channel + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a + * dedicated channel in the DPIO; user should point the queue's + * destination in the relevant interface to this DPIO + */ +enum dpio_channel_mode { + DPIO_NO_CHANNEL = 0, + DPIO_LOCAL_CHANNEL = 1, +}; + +/** + * dpio_enable() - Enable the DPIO, allow I/O portal operations. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_enable(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpio_disable() - Disable the DPIO, stop any I/O portal operation. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_disable(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpio_reset() - Reset the DPIO, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_reset(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * struct dpio_attr - Structure representing DPIO attributes + * @id: DPIO object ID + * @version: DPIO version + * @qbman_portal_ce_paddr: Physical address of the software portal + * cache-enabled area + * @qbman_portal_ci_paddr: Physical address of the software portal + * cache-inhibited area + * @qbman_portal_id: Software portal ID + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + */ +struct dpio_attr { + int id; + /** + * struct version - DPIO version + * @major: DPIO major version + * @minor: DPIO minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; + uint64_t qbman_portal_ce_paddr; + uint64_t qbman_portal_ci_paddr; + uint16_t qbman_portal_id; + enum dpio_channel_mode channel_mode; + uint8_t num_priorities; +}; + +/** + * dpio_get_attributes() - Retrieve DPIO attributes + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPIO object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_get_attributes(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpio_attr *attr); + +#endif /* _FSL_DPIO_H */ diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index c2e1ddd18b..986e7c8338 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -1,121 +1,44 @@ -/* Copyright 2014 Freescale Semiconductor Inc. +/* Copyright 2013-2015 Freescale Semiconductor Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -/*! - * @file fsl_dpmng.h - * @brief Management Complex General API - */ - #ifndef __FSL_DPMNG_H #define __FSL_DPMNG_H -/*! - * @Group grp_dpmng Management Complex General API - * - * @brief Contains general API for the Management Complex firmware - * @{ +/* Management Complex General API + * Contains general API for the Management Complex firmware */ struct fsl_mc_io; /** - * @brief Management Complex firmware version information + * Management Complex firmware version information */ -#define MC_VER_MAJOR 4 +#define MC_VER_MAJOR 6 #define MC_VER_MINOR 0 +/** + * struct mc_versoin + * @major: Major version number: incremented on API compatibility changes + * @minor: Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + * @revision: Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ struct mc_version { uint32_t major; - /*!< Major version number: incremented on API compatibility changes */ uint32_t minor; - /*!< Minor version number: incremented on API additions (that are - * backward compatible); reset when major version is incremented - */ uint32_t revision; - /*!< Internal revision number: incremented on implementation changes - * and/or bug fixes that have no impact on API - */ }; /** - * @brief Retrieves the Management Complex firmware version information - * - * @param[in] mc_io Pointer to opaque I/O object - * @param[out] mc_ver_info Pointer to version information structure + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @mc_ver_info: Returned version information structure * - * @returns '0' on Success; Error code otherwise. + * Return: '0' on Success; Error code otherwise. */ int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info); -/** - * @brief Resets an AIOP tile - * - * @param[in] mc_io Pointer to opaque I/O object - * @param[in] container_id AIOP container ID - * @param[in] aiop_tile_id AIOP tile ID to reset - * - * @returns '0' on Success; Error code otherwise. - */ -int dpmng_reset_aiop(struct fsl_mc_io *mc_io, - int container_id, - int aiop_tile_id); - -/** - * @brief Loads an image to AIOP tile - * - * @param[in] mc_io Pointer to opaque I/O object - * @param[in] container_id AIOP container ID - * @param[in] aiop_tile_id AIOP tile ID to reset - * @param[in] img_iova I/O virtual address of AIOP ELF image - * @param[in] img_size Size of AIOP ELF image in memory (in bytes) - * - * @returns '0' on Success; Error code otherwise. - */ -int dpmng_load_aiop(struct fsl_mc_io *mc_io, - int container_id, - int aiop_tile_id, - uint64_t img_iova, - uint32_t img_size); - -/** - * @brief AIOP run configuration - */ -struct dpmng_aiop_run_cfg { - uint32_t cores_mask; - /*!< Mask of AIOP cores to run (core 0 in most significant bit) */ - uint64_t options; - /*!< Execution options (currently none defined) */ -}; - -/** - * @brief Starts AIOP tile execution - * - * @param[in] mc_io Pointer to MC portal's I/O object - * @param[in] container_id AIOP container ID - * @param[in] aiop_tile_id AIOP tile ID to reset - * @param[in] cfg AIOP run configuration - * - * @returns '0' on Success; Error code otherwise. - */ -int dpmng_run_aiop(struct fsl_mc_io *mc_io, - int container_id, - int aiop_tile_id, - const struct dpmng_aiop_run_cfg *cfg); - -/** - * @brief Resets MC portal - * - * This function closes all object handles (tokens) that are currently - * open in the MC portal on which the command is submitted. This allows - * cleanup of stale handles that belong to non-functional user processes. - * - * @param[in] mc_io Pointer to MC portal's I/O object - * - * @returns '0' on Success; Error code otherwise. - */ -int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io); - -/** @} */ - #endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h new file mode 100644 index 0000000000..67c087d469 --- /dev/null +++ b/include/fsl-mc/fsl_dpni.h @@ -0,0 +1,1093 @@ +/* + * Copyright (C) 2013-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_DPNI_H +#define _FSL_DPNI_H + +/* DPNI Version */ +#define DPNI_VER_MAJOR 4 +#define DPNI_VER_MINOR 0 + +/* Command IDs */ +#define DPNI_CMDID_OPEN 0x801 +#define DPNI_CMDID_CLOSE 0x800 + +#define DPNI_CMDID_ENABLE 0x002 +#define DPNI_CMDID_DISABLE 0x003 +#define DPNI_CMDID_GET_ATTR 0x004 +#define DPNI_CMDID_RESET 0x005 + +#define DPNI_CMDID_SET_POOLS 0x200 +#define DPNI_CMDID_GET_RX_BUFFER_LAYOUT 0x201 +#define DPNI_CMDID_SET_RX_BUFFER_LAYOUT 0x202 +#define DPNI_CMDID_GET_TX_BUFFER_LAYOUT 0x203 +#define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 +#define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 +#define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 + +#define DPNI_CMDID_GET_QDID 0x210 +#define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 +#define DPNI_CMDID_GET_COUNTER 0x213 +#define DPNI_CMDID_SET_COUNTER 0x214 +#define DPNI_CMDID_GET_LINK_STATE 0x215 +#define DPNI_CMDID_SET_LINK_CFG 0x21A + +#define DPNI_CMDID_SET_PRIM_MAC 0x224 +#define DPNI_CMDID_GET_PRIM_MAC 0x225 +#define DPNI_CMDID_ADD_MAC_ADDR 0x226 +#define DPNI_CMDID_REMOVE_MAC_ADDR 0x227 + +#define DPNI_CMDID_SET_TX_FLOW 0x236 +#define DPNI_CMDID_GET_TX_FLOW 0x237 +#define DPNI_CMDID_SET_RX_FLOW 0x238 +#define DPNI_CMDID_GET_RX_FLOW 0x239 + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_OPEN(cmd, dpni_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) + + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_POOLS(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ + MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ + MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ + MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ + MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ + MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ + MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ + MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ + MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ + MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ + MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ + MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ + MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ + MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ + MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ + MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ + MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_ATTR(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_tcs); \ + MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_senders); \ + MC_RSP_OP(cmd, 0, 48, 8, enum net_prot, attr->start_hdr); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->options); \ + MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_unicast_filters); \ + MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_multicast_filters);\ + MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->max_vlan_filters); \ + MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ + MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ + MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ + MC_RSP_OP(cmd, 3, 0, 8, uint8_t, attr->max_dist_per_tc[0]); \ + MC_RSP_OP(cmd, 3, 8, 8, uint8_t, attr->max_dist_per_tc[1]); \ + MC_RSP_OP(cmd, 3, 16, 8, uint8_t, attr->max_dist_per_tc[2]); \ + MC_RSP_OP(cmd, 3, 24, 8, uint8_t, attr->max_dist_per_tc[3]); \ + MC_RSP_OP(cmd, 3, 32, 8, uint8_t, attr->max_dist_per_tc[4]); \ + MC_RSP_OP(cmd, 3, 40, 8, uint8_t, attr->max_dist_per_tc[5]); \ + MC_RSP_OP(cmd, 3, 48, 8, uint8_t, attr->max_dist_per_tc[6]); \ + MC_RSP_OP(cmd, 3, 56, 8, uint8_t, attr->max_dist_per_tc[7]); \ + MC_RSP_OP(cmd, 4, 0, 16, uint16_t, \ + attr->ipr_cfg.max_reass_frm_size); \ + MC_RSP_OP(cmd, 4, 16, 16, uint16_t, \ + attr->ipr_cfg.min_frag_size_ipv4); \ + MC_RSP_OP(cmd, 4, 32, 16, uint16_t, \ + attr->ipr_cfg.min_frag_size_ipv6); \ + MC_RSP_OP(cmd, 5, 0, 16, uint16_t, \ + attr->ipr_cfg.max_open_frames_ipv4); \ + MC_RSP_OP(cmd, 5, 16, 16, uint16_t, \ + attr->ipr_cfg.max_open_frames_ipv6); \ + MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_RX_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ + MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_TX_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_TX_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ + MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_RSP_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_RSP_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_RSP_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_RSP_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_TX_CONF_BUFFER_LAYOUT(cmd, layout) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, layout->data_align); \ + MC_CMD_OP(cmd, 0, 32, 32, uint32_t, layout->options); \ + MC_CMD_OP(cmd, 1, 0, 1, int, layout->pass_timestamp); \ + MC_CMD_OP(cmd, 1, 1, 1, int, layout->pass_parser_result); \ + MC_CMD_OP(cmd, 1, 2, 1, int, layout->pass_frame_status); \ + MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_head_room); \ + MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_tail_room); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_QDID(cmd, qdid) \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ + MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_COUNTER(cmd, counter) \ + MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_COUNTER(cmd, value) \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, value) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_COUNTER(cmd, counter, value) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 16, enum dpni_counter, counter); \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, value); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->rate);\ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, state->rate);\ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ +} while (0) + + + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, \ + cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_id);\ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, \ + cfg->conf_err_cfg.queue_cfg.dest_cfg.priority);\ + MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ + cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_type);\ + MC_CMD_OP(cmd, 0, 42, 1, int, cfg->conf_err_cfg.errors_only);\ + MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ + MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ + MC_CMD_OP(cmd, 0, 45, 1, int, \ + cfg->conf_err_cfg.use_default_queue);\ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, \ + cfg->conf_err_cfg.queue_cfg.user_ctx);\ + MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ + MC_CMD_OP(cmd, 2, 32, 32, uint32_t, \ + cfg->conf_err_cfg.queue_cfg.options);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_SET_TX_FLOW(cmd, flow_id) \ + MC_RSP_OP(cmd, 0, 48, 16, uint16_t, flow_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_TX_FLOW(cmd, flow_id) \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, \ + attr->conf_err_attr.queue_attr.dest_cfg.dest_id);\ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ + attr->conf_err_attr.queue_attr.dest_cfg.priority);\ + MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ + attr->conf_err_attr.queue_attr.dest_cfg.dest_type);\ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->conf_err_attr.errors_only);\ + MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ + MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ + MC_RSP_OP(cmd, 0, 45, 1, int, \ + attr->conf_err_attr.use_default_queue);\ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, \ + attr->conf_err_attr.queue_attr.user_ctx);\ + MC_RSP_OP(cmd, 2, 32, 32, uint32_t, \ + attr->conf_err_attr.queue_attr.fqid);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_RX_FLOW(cmd, tc_id, flow_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\ + MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, cfg->dest_cfg.dest_type);\ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ + MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ + MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_RX_FLOW(cmd, tc_id, flow_id) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_RSP_GET_RX_FLOW(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ + MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ + MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ +} while (0) + +enum net_prot { + NET_PROT_NONE = 0, + NET_PROT_PAYLOAD, + NET_PROT_ETH, + NET_PROT_VLAN, + NET_PROT_IPV4, + NET_PROT_IPV6, + NET_PROT_IP, + NET_PROT_TCP, + NET_PROT_UDP, + NET_PROT_UDP_LITE, + NET_PROT_IPHC, + NET_PROT_SCTP, + NET_PROT_SCTP_CHUNK_DATA, + NET_PROT_PPPOE, + NET_PROT_PPP, + NET_PROT_PPPMUX, + NET_PROT_PPPMUX_SUBFRM, + NET_PROT_L2TPV2, + NET_PROT_L2TPV3_CTRL, + NET_PROT_L2TPV3_SESS, + NET_PROT_LLC, + NET_PROT_LLC_SNAP, + NET_PROT_NLPID, + NET_PROT_SNAP, + NET_PROT_MPLS, + NET_PROT_IPSEC_AH, + NET_PROT_IPSEC_ESP, + NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ + NET_PROT_MACSEC, + NET_PROT_GRE, + NET_PROT_MINENCAP, + NET_PROT_DCCP, + NET_PROT_ICMP, + NET_PROT_IGMP, + NET_PROT_ARP, + NET_PROT_CAPWAP_DATA, + NET_PROT_CAPWAP_CTRL, + NET_PROT_RFC2684, + NET_PROT_ICMPV6, + NET_PROT_FCOE, + NET_PROT_FIP, + NET_PROT_ISCSI, + NET_PROT_GTP, + NET_PROT_USER_DEFINED_L2, + NET_PROT_USER_DEFINED_L3, + NET_PROT_USER_DEFINED_L4, + NET_PROT_USER_DEFINED_L5, + NET_PROT_USER_DEFINED_SHIM1, + NET_PROT_USER_DEFINED_SHIM2, + + NET_PROT_DUMMY_LAST +}; + +/* Data Path Network Interface API + * Contains initialization APIs and runtime control APIs for DPNI + */ + +struct fsl_mc_io; + +/* General DPNI macros */ + +/* Maximum number of traffic classes */ +#define DPNI_MAX_TC 8 +/* Maximum number of buffer pools per DPNI */ +#define DPNI_MAX_DPBP 8 + +/* All traffic classes considered; see dpni_set_rx_flow() */ +#define DPNI_ALL_TCS (uint8_t)(-1) +/* All flows within traffic class considered; see dpni_set_rx_flow() */ +#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) +/* Generate new flow ID; see dpni_set_tx_flow() */ +#define DPNI_NEW_FLOW_ID (uint16_t)(-1) + +/** + * dpni_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @dpni_id: DPNI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpni_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_open(struct fsl_mc_io *mc_io, int dpni_id, uint16_t *token); + +/** + * dpni_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_close(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * struct dpni_ipr_cfg - Structure representing IP reassembly configuration + * @max_reass_frm_size: Maximum size of the reassembled frame + * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments + * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments + * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly process + * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly process + */ +struct dpni_ipr_cfg { + uint16_t max_reass_frm_size; + uint16_t min_frag_size_ipv4; + uint16_t min_frag_size_ipv6; + uint16_t max_open_frames_ipv4; + uint16_t max_open_frames_ipv6; +}; + +/** + * struct dpni_pools_cfg - Structure representing buffer pools configuration + * @num_dpbp: Number of DPBPs + * @pools: Array of buffer pools parameters; The number of valid entries + * must match 'num_dpbp' value + */ +struct dpni_pools_cfg { + uint8_t num_dpbp; + /** + * struct pools - Buffer pools parameters + * @dpbp_id: DPBP object ID + * @buffer_size: Buffer size + */ + struct { + int dpbp_id; + uint16_t buffer_size; + } pools[DPNI_MAX_DPBP]; +}; + +/** + * dpni_set_pools() - Set buffer pools configuration + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @cfg: Buffer pools configuration + * + * mandatory for DPNI operation + * warning:Allowed only when DPNI is disabled + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_pools(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dpni_pools_cfg *cfg); + +/** + * dpni_enable() - Enable the DPNI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_enable(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * dpni_disable() - Disable the DPNI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_disable(struct fsl_mc_io *mc_io, uint16_t token); + + +/** + * @dpni_reset() - Reset the DPNI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_reset(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * struct dpni_attr - Structure representing DPNI attributes + * @id: DPNI object ID + * @version: DPNI version + * @start_hdr: Indicates the packet starting header for parsing + * @options: Mask of available options; reflects the value as was given in + * object's creation + * @max_senders: Maximum number of different senders; used as the number + * of dedicated Tx flows; + * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) + * @max_dist_per_tc: Maximum distribution size per Rx traffic class; + * Set to the required value minus 1 + * @max_unicast_filters: Maximum number of unicast filters + * @max_multicast_filters: Maximum number of multicast filters + * @max_vlan_filters: Maximum number of VLAN filters + * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table + * @max_qos_key_size: Maximum key size for the QoS look-up + * @max_dist_key_size: Maximum key size for the distribution look-up + * @ipr_cfg: IP reassembly configuration + */ +struct dpni_attr { + int id; + /** + * struct version - DPNI version + * @major: DPNI major version + * @minor: DPNI minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; + enum net_prot start_hdr; + uint64_t options; + uint8_t max_senders; + uint8_t max_tcs; + uint8_t max_dist_per_tc[DPNI_MAX_TC]; + uint8_t max_unicast_filters; + uint8_t max_multicast_filters; + uint8_t max_vlan_filters; + uint8_t max_qos_entries; + uint8_t max_qos_key_size; + uint8_t max_dist_key_size; + struct dpni_ipr_cfg ipr_cfg; +}; +/** + * dpni_get_attributes() - Retrieve DPNI attributes. + * @mc_io: Pointer to MC portal's I/O objec + * @token: Token of DPNI object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_attributes(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_attr *attr); + +/* DPNI buffer layout modification options */ + +/* Select to modify the time-stamp setting */ +#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001 +/* Select to modify the parser-result setting; not applicable for Tx */ +#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002 +/* Select to modify the frame-status setting */ +#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004 +/* Select to modify the private-data-size setting */ +#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008 +/* Select to modify the data-alignment setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010 +/* Select to modify the data-head-room setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 +/*!< Select to modify the data-tail-room setting */ +#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 + +/** + * struct dpni_buffer_layout - Structure representing DPNI buffer layout + * @options: Flags representing the suggested modifications to the buffer + * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags + * @pass_timestamp: Pass timestamp value + * @pass_parser_result: Pass parser results + * @pass_frame_status: Pass frame status + * @private_data_size: Size kept for private data (in bytes) + * @data_align: Data alignment + * @data_head_room: Data head room + * @data_tail_room: Data tail room + */ +struct dpni_buffer_layout { + uint32_t options; + int pass_timestamp; + int pass_parser_result; + int pass_frame_status; + uint16_t private_data_size; + uint16_t data_align; + uint16_t data_head_room; + uint16_t data_tail_room; +}; + +/** + * dpni_get_rx_buffer_layout() - Retrieve Rx buffer layout attributes. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @layout: Returns buffer layout attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_buffer_layout *layout); +/** + * dpni_set_rx_buffer_layout() - Set Rx buffer layout configuration. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @layout: Buffer layout configuration + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_rx_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dpni_buffer_layout *layout); + +/** + * dpni_get_tx_buffer_layout() - Retrieve Tx buffer layout attributes. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @layout: Returns buffer layout attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_buffer_layout *layout); + +/** + * @brief Set Tx buffer layout configuration. + * + * @param[in] mc_io Pointer to MC portal's I/O object + * @param[in] token Token of DPNI object + * @param[in] layout Buffer layout configuration + * + * @returns '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_tx_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dpni_buffer_layout *layout); +/** + * dpni_get_tx_conf_buffer_layout() - Retrieve Tx confirmation buffer layout + * attributes. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @layout: Returns buffer layout attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_buffer_layout *layout); +/** + * dpni_set_tx_conf_buffer_layout() - Set Tx confirmation buffer layout + * configuration. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @layout: Buffer layout configuration + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_tx_conf_buffer_layout(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dpni_buffer_layout *layout); +/** + * dpni_get_spid() - Get the AIOP storage profile ID associated with the DPNI + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @spid: Returned aiop storage-profile ID + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Only relevant for DPNI that belongs to AIOP container. + */ +int dpni_get_qdid(struct fsl_mc_io *mc_io, uint16_t token, uint16_t *qdid); + +/** + * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @data_offset: Tx data offset (from start of buffer) + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, + uint16_t token, + uint16_t *data_offset); + +/** + * enum dpni_counter - DPNI counter types + * @DPNI_CNT_ING_FRAME: Counts ingress frames + * @DPNI_CNT_ING_BYTE: Counts ingress bytes + * @DPNI_CNT_ING_FRAME_DROP: Counts ingress frames dropped due to explicit + * 'drop' setting + * @DPNI_CNT_ING_FRAME_DISCARD: Counts ingress frames discarded due to errors + * @DPNI_CNT_ING_MCAST_FRAME: Counts ingress multicast frames + * @DPNI_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes + * @DPNI_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames + * @DPNI_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes + * @DPNI_CNT_EGR_FRAME: Counts egress frames + * @DPNI_CNT_EGR_BYTE: Counts egress bytes + * @DPNI_CNT_EGR_FRAME_DISCARD: Counts egress frames discarded due to errors + */ +enum dpni_counter { + DPNI_CNT_ING_FRAME = 0x0, + DPNI_CNT_ING_BYTE = 0x1, + DPNI_CNT_ING_FRAME_DROP = 0x2, + DPNI_CNT_ING_FRAME_DISCARD = 0x3, + DPNI_CNT_ING_MCAST_FRAME = 0x4, + DPNI_CNT_ING_MCAST_BYTE = 0x5, + DPNI_CNT_ING_BCAST_FRAME = 0x6, + DPNI_CNT_ING_BCAST_BYTES = 0x7, + DPNI_CNT_EGR_FRAME = 0x8, + DPNI_CNT_EGR_BYTE = 0x9, + DPNI_CNT_EGR_FRAME_DISCARD = 0xa +}; + +/** + * dpni_get_counter() - Read a specific DPNI counter + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @counter: The requested counter + * @value: Returned counter's current value + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_counter(struct fsl_mc_io *mc_io, + uint16_t token, + enum dpni_counter counter, + uint64_t *value); + +/** + * dpni_set_counter() - Set (or clear) a specific DPNI counter + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @counter: The requested counter + * @value: New counter value; typically pass '0' for resetting + * the counter. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_counter(struct fsl_mc_io *mc_io, + uint16_t token, + enum dpni_counter counter, + uint64_t value); +/** + * struct - Structure representing DPNI link configuration + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + */ +struct dpni_link_cfg { + uint64_t rate; + uint64_t options; +}; + +/** + * dpni_set_link_cfg() - set the link configuration. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @cfg: Link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_link_cfg *cfg); + +/** + * struct dpni_link_state - Structure representing DPNI link state + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + * @up: Link state; '0' for down, '1' for up + */ +struct dpni_link_state { + uint64_t rate; + uint64_t options; + int up; +}; + +/** + * dpni_get_link_state() - Return the link state (either up or down) + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @state: Returned link state; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_link_state(struct fsl_mc_io *mc_io, + uint16_t token, + struct dpni_link_state *state); + +/** + * dpni_set_primary_mac_addr() - Set the primary MAC address + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @mac_addr: MAC address to set as primary address + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, + uint16_t token, + const uint8_t mac_addr[6]); +/** + * dpni_get_primary_mac_addr() - Get the primary MAC address + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @mac_addr: Returned MAC address + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, + uint16_t token, + uint8_t mac_addr[6]); +/** + * dpni_add_mac_addr() - Add MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @mac_addr: MAC address to add + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, + uint16_t token, + const uint8_t mac_addr[6]); + +/** + * dpni_remove_mac_addr() - Remove MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @mac_addr: MAC address to remove + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, + uint16_t token, + const uint8_t mac_addr[6]); + +/** + * enum dpni_dest - DPNI destination types + * DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and + * does not generate FQDAN notifications; user is expected to + * dequeue from the queue based on polling or other user-defined + * method + * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN + * notifications to the specified DPIO; user is expected to dequeue + * from the queue only after notification is received + * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate + * FQDAN notifications, but is connected to the specified DPCON + * object; user is expected to dequeue from the DPCON channel + */ +enum dpni_dest { + DPNI_DEST_NONE = 0, + DPNI_DEST_DPIO = 1, + DPNI_DEST_DPCON = 2 +}; + +/** + * struct dpni_dest_cfg - Structure representing DPNI destination parameters + * @dest_type: Destination type + * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type + * @priority: Priority selection within the DPIO or DPCON channel; valid values + * are 0-1 or 0-7, depending on the number of priorities in that + * channel; not relevant for 'DPNI_DEST_NONE' option + */ +struct dpni_dest_cfg { + enum dpni_dest dest_type; + int dest_id; + uint8_t priority; +}; + +/* DPNI queue modification options */ + +/* Select to modify the user's context associated with the queue */ +#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 +/* Select to modify the queue's destination */ +#define DPNI_QUEUE_OPT_DEST 0x00000002 + +/** + * struct dpni_queue_cfg - Structure representing queue configuration + * @options: Flags representing the suggested modifications to the queue; + * Use any combination of 'DPNI_QUEUE_OPT_<X>' flags + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' + * is contained in 'options' + * @dest_cfg: Queue destination parameters; + * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' + */ +struct dpni_queue_cfg { + uint32_t options; + uint64_t user_ctx; + struct dpni_dest_cfg dest_cfg; +}; + +/** + * struct dpni_queue_attr - Structure representing queue attributes + * @user_ctx: User context value provided in the frame descriptor of each + * dequeued frame + * @dest_cfg: Queue destination configuration + * @fqid: Virtual fqid value to be used for dequeue operations + */ +struct dpni_queue_attr { + uint64_t user_ctx; + struct dpni_dest_cfg dest_cfg; + uint32_t fqid; +}; + +/* DPNI Tx flow modification options */ + +/* Select to modify the settings for dedicate Tx confirmation/error */ +#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 +/*!< Select to modify the Tx confirmation and/or error setting */ +#define DPNI_TX_FLOW_OPT_ONLY_TX_ERROR 0x00000002 +/*!< Select to modify the queue configuration */ +#define DPNI_TX_FLOW_OPT_QUEUE 0x00000004 +/*!< Select to modify the L3 checksum generation setting */ +#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 +/*!< Select to modify the L4 checksum generation setting */ +#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 + +/** + * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration + * @options: Flags representing the suggested modifications to the Tx flow; + * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags + * @conf_err_cfg: Tx confirmation and error configuration; these settings are + * ignored if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' was set at + * DPNI creation + * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; + * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in + * 'options' + * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; + * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in + * 'options' + */ +struct dpni_tx_flow_cfg { + uint32_t options; + /** + * struct cnf_err_cfg - Tx confirmation and error configuration + * @use_default_queue: Set to '1' to use the common (default) Tx + * confirmation and error queue; Set to '0' to use the + * private Tx confirmation and error queue; valid only if + * 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in + * 'options' + * @errors_only: Set to '1' to report back only error frames; + * Set to '0' to confirm transmission/error for all + * transmitted frames; + * valid only if 'DPNI_TX_FLOW_OPT_ONLY_TX_ERROR' is + * contained in 'options' and 'use_default_queue = 0'; + * @queue_cfg: Queue configuration; valid only if + * 'DPNI_TX_FLOW_OPT_QUEUE' is contained in 'options' + */ + struct { + int use_default_queue; + int errors_only; + struct dpni_queue_cfg queue_cfg; + } conf_err_cfg; + int l3_chksum_gen; + int l4_chksum_gen; +}; + +/** + * dpni_set_tx_flow() - Set Tx flow configuration + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @flow_id: Provides (or returns) the sender's flow ID; + * for each new sender set (*flow_id) to + * 'DPNI_NEW_FLOW_ID' to generate a new flow_id; + * this ID should be used as the QDBIN argument + * in enqueue operations + * @cfg: Tx flow configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_flow(struct fsl_mc_io *mc_io, + uint16_t token, + uint16_t *flow_id, + const struct dpni_tx_flow_cfg *cfg); + +/** + * struct dpni_tx_flow_attr - Structure representing Tx flow attributes + * @conf_err_attr: Tx confirmation and error attributes + * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled + * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled + */ +struct dpni_tx_flow_attr { + /** + * struct conf_err_attr - Tx confirmation and error attributes + * @use_default_queue: '1' if using common (default) Tx confirmation and + * error queue; + * '0' if using private Tx confirmation and error + * queue + * @errors_only: '1' if only error frames are reported back; '0' if all + * transmitted frames are confirmed + * @queue_attr: Queue attributes + */ + struct { + int use_default_queue; + int errors_only; + struct dpni_queue_attr queue_attr; + } conf_err_attr; + int l3_chksum_gen; + int l4_chksum_gen; +}; + +/** + * dpni_get_tx_flow() - Get Tx flow attributes + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function + * @attr: Returned Tx flow attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_flow(struct fsl_mc_io *mc_io, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_flow_attr *attr); + +/** + * dpni_set_rx_flow() - Set Rx flow configuration + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @tc_id: Traffic class selection (0-7); + * use 'DPNI_ALL_TCS' to set all TCs and all flows + * @flow_id Rx flow id within the traffic class; use + * 'DPNI_ALL_TC_FLOWS' to set all flows within + * this tc_id; ignored if tc_id is set to + * 'DPNI_ALL_TCS'; + * @cfg: Rx flow configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_rx_flow(struct fsl_mc_io *mc_io, + uint16_t token, + uint8_t tc_id, + uint16_t flow_id, + const struct dpni_queue_cfg *cfg); + +/** + * dpni_get_rx_flow() - Get Rx flow attributes + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPNI object + * @tc_id: Traffic class selection (0-7) + * @flow_id: Rx flow id within the traffic class + * @attr: Returned Rx flow attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_rx_flow(struct fsl_mc_io *mc_io, + uint16_t token, + uint8_t tc_id, + uint16_t flow_id, + struct dpni_queue_attr *attr); + +#endif /* _FSL_DPNI_H */ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h new file mode 100644 index 0000000000..f837e8926c --- /dev/null +++ b/include/fsl-mc/fsl_dprc.h @@ -0,0 +1,659 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Author: German Rivera <German.Rivera@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_DPRC_H +#define _FSL_DPRC_H + +/* DPRC Version */ +#define DPRC_VER_MAJOR 2 +#define DPRC_VER_MINOR 0 + +/* Command IDs */ +#define DPRC_CMDID_CLOSE 0x800 +#define DPRC_CMDID_OPEN 0x805 + +#define DPRC_CMDID_GET_ATTR 0x004 +#define DPRC_CMDID_RESET_CONT 0x005 + +#define DPRC_CMDID_GET_CONT_ID 0x830 +#define DPRC_CMDID_GET_OBJ_COUNT 0x159 +#define DPRC_CMDID_GET_OBJ 0x15A +#define DPRC_CMDID_GET_RES_COUNT 0x15B +#define DPRC_CMDID_GET_RES_IDS 0x15C +#define DPRC_CMDID_GET_OBJ_REG 0x15E + +#define DPRC_CMDID_CONNECT 0x167 +#define DPRC_CMDID_DISCONNECT 0x168 +#define DPRC_CMDID_GET_CONNECTION 0x16C + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ + MC_RSP_OP(cmd, 0, 0, 32, int, container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_OPEN(cmd, container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \ + MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ + MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->version.minor);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_count) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ(cmd, obj_index) \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_index) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_RES_COUNT(cmd, type) \ +do { \ + MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \ + MC_RSP_OP(cmd, 0, 0, 32, int, res_count) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \ +do { \ + MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ + range_desc->iter_status); \ + MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ + MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ + MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ + range_desc->iter_status);\ + MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ + MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\ + MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ +} while (0) + +/* param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \ +do { \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, region_desc->base_paddr);\ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->interface_id); \ + MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ + MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->interface_id); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \ + MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \ + MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \ + MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \ + MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \ + MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \ + MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \ + MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \ + MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \ + MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \ + MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \ + MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \ + MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \ + MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \ + MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \ + MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \ + MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \ + MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \ + MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \ + MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \ + MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \ + MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \ + MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \ + MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \ + MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_DISCONNECT(cmd, endpoint) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint->interface_id); \ + MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \ + MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \ + MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \ + MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \ + MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \ + MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \ + MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \ + MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->interface_id); \ + MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ + MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ + MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ + MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \ + MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \ + MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \ + MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \ + MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \ + MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \ + MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \ + MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \ + MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \ + MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \ + MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \ + MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \ + MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \ +} while (0) + + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \ +do { \ + MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \ + MC_RSP_OP(cmd, 3, 32, 32, int, endpoint2->interface_id); \ + MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \ + MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \ + MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \ + MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \ + MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \ + MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \ + MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \ + MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \ + MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \ + MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \ + MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \ + MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \ + MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \ + MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \ + MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \ + MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \ + MC_RSP_OP(cmd, 6, 0, 32, int, state); \ +} while (0) + +/* Data Path Resource Container API + * Contains DPRC API for managing and querying DPAA resources + */ +struct fsl_mc_io; + +/** + * Set this value as the icid value in dprc_cfg structure when creating a + * container, in case the ICID is not selected by the user and should be + * allocated by the DPRC from the pool of ICIDs. + */ +#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0)) + +/** + * Set this value as the portal_id value in dprc_cfg structure when creating a + * container, in case the portal ID is not specifically selected by the + * user and should be allocated by the DPRC from the pool of portal ids. + */ +#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0)) + +/** + * dprc_get_container_id() - Get container ID associated with a given portal. + * @mc_io: Pointer to MC portal's I/O object + * @container_id: Requested container ID + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_container_id(struct fsl_mc_io *mc_io, int *container_id); + +/** + * dprc_open() - Open DPRC object for use + * @mc_io: Pointer to MC portal's I/O object + * @container_id: Container ID to open + * @token: Returned token of DPRC object + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Required before any operation on the object. + */ +int dprc_open(struct fsl_mc_io *mc_io, int container_id, uint16_t *token); + +/** + * dprc_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_close(struct fsl_mc_io *mc_io, uint16_t token); + +/** + * Container general options + * + * These options may be selected at container creation by the container creator + * and can be retrieved using dprc_get_attributes() + */ + +/* Spawn Policy Option allowed - Indicates that the new container is allowed + * to spawn and have its own child containers. + */ +#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001 + +/* General Container allocation policy - Indicates that the new container is + * allowed to allocate requested resources from its parent container; if not + * set, the container is only allowed to use resources in its own pools; Note + * that this is a container's global policy, but the parent container may + * override it and set specific quota per resource type. + */ +#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002 + +/* Object initialization allowed - software context associated with this + * container is allowed to invoke object initialization operations. + */ +#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004 + +/* Topology change allowed - software context associated with this + * container is allowed to invoke topology operations, such as attach/detach + * of network objects. + */ +#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 + +/* IOMMU bypass - indicates whether objects of this container are permitted + * to bypass the IOMMU. + */ +#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010 + +/* AIOP - Indicates that container belongs to AIOP. */ +#define DPRC_CFG_OPT_AIOP 0x00000020 + +/** + * struct dprc_cfg - Container configuration options + * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free + * ICID value is allocated by the DPRC + * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free + * portal ID is allocated by the DPRC + * @options: Combination of 'DPRC_CFG_OPT_<X>' options + */ +struct dprc_cfg { + uint16_t icid; + int portal_id; + uint64_t options; +}; + +/** + * dprc_reset_container - Reset child container. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @child_container_id: ID of the container to reset + * + * In case a software context crashes or becomes non-responsive, the parent + * may wish to reset its resources container before the software context is + * restarted. + * + * This routine informs all objects assigned to the child container that the + * container is being reset, so they may perform any cleanup operations that are + * needed. All objects handles that were owned by the child container shall be + * closed. + * + * Note that such request may be submitted even if the child software context + * has not crashed, but the resulting object cleanup operations will not be + * aware of that. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_reset_container(struct fsl_mc_io *mc_io, + uint16_t token, + int child_container_id); + +/** + * struct dprc_attributes - Container attributes + * @container_id: Container's ID + * @icid: Container's ICID + * @portal_id: Container's portal ID + * @options: Container's options as set at container's creation + * @version: DPRC version + */ +struct dprc_attributes { + int container_id; + uint16_t icid; + int portal_id; + uint64_t options; + /** + * struct version - DPRC version + * @major: DPRC major version + * @minor: DPRC minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; +}; + +/** + * dprc_get_attributes() - Obtains container attributes + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @attributes Returned container attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_attributes(struct fsl_mc_io *mc_io, + uint16_t token, + struct dprc_attributes *attributes); + +/** + * dprc_get_obj_count() - Obtains the number of objects in the DPRC + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @obj_count: Number of objects assigned to the DPRC + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_count(struct fsl_mc_io *mc_io, uint16_t token, int *obj_count); + +/* Objects Attributes Flags */ + +/* Opened state - Indicates that an object is open by at least one owner */ +#define DPRC_OBJ_STATE_OPEN 0x00000001 +/* Plugged state - Indicates that the object is plugged */ +#define DPRC_OBJ_STATE_PLUGGED 0x00000002 + +/** + * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() + * @type: Type of object: NULL terminated string + * @id: ID of logical object resource + * @vendor: Object vendor identifier + * @ver_major: Major version number + * @ver_minor: Minor version number + * @irq_count: Number of interrupts supported by the object + * @region_count: Number of mappable regions supported by the object + * @state: Object state: combination of DPRC_OBJ_STATE_ states + */ +struct dprc_obj_desc { + char type[16]; + int id; + uint16_t vendor; + uint16_t ver_major; + uint16_t ver_minor; + uint8_t irq_count; + uint8_t region_count; + uint32_t state; +}; + +/** + * dprc_get_obj() - Get general information on an object + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @obj_index: Index of the object to be queried (< obj_count) + * @obj_desc: Returns the requested object descriptor + * + * The object descriptors are retrieved one by one by incrementing + * obj_index up to (not including) the value of obj_count returned + * from dprc_get_obj_count(). dprc_get_obj_count() must + * be called prior to dprc_get_obj(). + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj(struct fsl_mc_io *mc_io, + uint16_t token, + int obj_index, + struct dprc_obj_desc *obj_desc); + +/** + * dprc_get_res_count() - Obtains the number of free resources that are assigned + * to this container, by pool type + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @type: pool type + * @res_count: Returned number of free resources of the given + * resource type that are assigned to this DPRC + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_res_count(struct fsl_mc_io *mc_io, + uint16_t token, + char *type, + int *res_count); + +/** + * enum dprc_iter_status - Iteration status + * @DPRC_ITER_STATUS_FIRST: Perform first iteration + * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed + * @DPRC_ITER_STATUS_LAST: Indicates last iteration + */ +enum dprc_iter_status { + DPRC_ITER_STATUS_FIRST = 0, + DPRC_ITER_STATUS_MORE = 1, + DPRC_ITER_STATUS_LAST = 2 +}; + +/** + * struct dprc_res_ids_range_desc - Resource ID range descriptor + * @base_id: Base resource ID of this range + * @last_id: Last resource ID of this range + * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at + * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE, + * additional iterations are needed, until the returned marker is + * DPRC_ITER_STATUS_LAST + */ +struct dprc_res_ids_range_desc { + int base_id; + int last_id; + enum dprc_iter_status iter_status; +}; + +/** + * dprc_get_res_ids() - Obtains IDs of free resources in the container + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @type: pool type + * @range_desc: range descriptor + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_res_ids(struct fsl_mc_io *mc_io, + uint16_t token, + char *type, + struct dprc_res_ids_range_desc *range_desc); + +/** + * struct dprc_region_desc - Mappable region descriptor + * @base_paddr: Region base physical address + * @size: Region size (in bytes) + */ +struct dprc_region_desc { + uint64_t base_paddr; + uint32_t size; +}; + +/** + * dprc_get_obj_region() - Get region information for a specified object. + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @obj_type; Object type as returned in dprc_get_obj() + * @obj_id: Unique object instance as returned in dprc_get_obj() + * @region_index: The specific region to query + * @region_desc: Returns the requested region descriptor + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_obj_region(struct fsl_mc_io *mc_io, + uint16_t token, + char *obj_type, + int obj_id, + uint8_t region_index, + struct dprc_region_desc *region_desc); +/** + * struct dprc_endpoint - Endpoint description for link connect/disconnect + * operations + * @type: Endpoint object type: NULL terminated string + * @id: Endpoint object ID + * @interface_id: Interface ID; should be set for endpoints with multiple + * interfaces ("dpsw", "dpdmux"); for others, always set to 0 + */ +struct dprc_endpoint { + char type[16]; + int id; + int interface_id; +}; + +/** + * dprc_connect() - Connect two endpoints to create a network link between them + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Endpoint 2 configuration parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_connect(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2); + +/** + * dprc_disconnect() - Disconnect one endpoint to remove its network connection + * @mc_io: Pointer to MC portal's I/O object + * @token: Token of DPRC object + * @endpoint: Endpoint configuration parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_disconnect(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dprc_endpoint *endpoint); + +/** +* dprc_get_connection() - Get connected endpoint and link status if connection +* exists. +* @mc_io Pointer to MC portal's I/O object +* @token Token of DPRC object +* @endpoint1 Endpoint 1 configuration parameters +* @endpoint2 Returned endpoint 2 configuration parameters +* @state: Returned link state: 1 - link is up, 0 - link is down +* +* Return: '0' on Success; -ENAVAIL if connection does not exist. +*/ +int dprc_get_connection(struct fsl_mc_io *mc_io, + uint16_t token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, + int *state); + +#endif /* _FSL_DPRC_H */ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index b9f089e5f3..ec244150e8 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -53,7 +53,8 @@ struct mc_ccsr_registers { u32 reg_error[]; }; -int mc_init(bd_t *bis); - int get_mc_boot_status(void); +unsigned long mc_get_dram_block_size(void); +int fsl_mc_ldpaa_init(bd_t *bis); +void fsl_mc_ldpaa_exit(bd_t *bis); #endif diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index e7fcb5b142..cb39c39722 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -1,4 +1,4 @@ -/* Copyright 2014 Freescale Semiconductor Inc. +/* Copyright 2013-2015 Freescale Semiconductor Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -41,9 +41,9 @@ enum mc_cmd_status { #define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */ #define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */ -#define MC_CMD_HDR_AUTHID_O 38 /* Authentication ID field offset */ -#define MC_CMD_HDR_AUTHID_S 10 /* Authentication ID field size */ #define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ +#define MC_CMD_HDR_TOKEN_O 38 /* Token field offset */ +#define MC_CMD_HDR_TOKEN_S 10 /* Token field size */ #define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ #define MC_CMD_HDR_PRI_O 15 /* Priority field offset */ #define MC_CMD_HDR_PRI_S 1 /* Priority field size */ @@ -52,12 +52,15 @@ enum mc_cmd_status { ((enum mc_cmd_status)u64_dec((_hdr), \ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) -#define MC_CMD_HDR_READ_AUTHID(_hdr) \ - ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S)) +#define MC_CMD_HDR_READ_TOKEN(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) #define MC_CMD_PRI_LOW 0 /*!< Low Priority command indication */ #define MC_CMD_PRI_HIGH 1 /*!< High Priority command indication */ +#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ + ((_ext)[_param] |= u64_enc((_offset), (_width), _arg)) + #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ ((_cmd).params[_param] |= u64_enc((_offset), (_width), _arg)) @@ -66,12 +69,12 @@ enum mc_cmd_status { static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, uint8_t priority, - uint16_t auth_id) + uint16_t token) { uint64_t hdr; hdr = u64_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); - hdr |= u64_enc(MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S, auth_id); + hdr |= u64_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token); hdr |= u64_enc(MC_CMD_HDR_PRI_O, MC_CMD_HDR_PRI_S, priority); hdr |= u64_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S, MC_CMD_STATUS_READY); diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h new file mode 100644 index 0000000000..9f0697851b --- /dev/null +++ b/include/fsl-mc/fsl_mc_private.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_MC_PRIVATE_H_ +#define _FSL_MC_PRIVATE_H_ + +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <linux/compat.h> +#include <linux/types.h> +#include <linux/stringify.h> + +#include <fsl-mc/fsl_mc_sys.h> +#include <fsl-mc/fsl_mc_cmd.h> +#include <fsl-mc/fsl_dprc.h> +#include <fsl-mc/fsl_dpbp.h> + +extern struct fsl_mc_io *dflt_mc_io; + +/** + * struct dpbp_node - DPBP strucuture + * @uint16_t handle: DPBP object handle + * @int dpbp_id: DPBP id + */ +struct fsl_dpbp_obj { + uint16_t dpbp_handle; + struct dpbp_attr dpbp_attr; +}; + +extern struct fsl_dpbp_obj *dflt_dpbp; + +/** + * struct fsl_dpio_obj - DPIO strucuture + * @int dpio_id: DPIO id + * @struct qbman_swp *sw_portal: SW portal object + */ +struct fsl_dpio_obj { + int dpio_id; + struct qbman_swp *sw_portal; /** SW portal object */ +}; + +extern struct fsl_dpio_obj *dflt_dpio; + +int mc_init(void); +int ldpaa_eth_init(struct dprc_obj_desc obj_desc); +#endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/include/fsl-mc/fsl_qbman_base.h b/include/fsl-mc/fsl_qbman_base.h new file mode 100644 index 0000000000..c92cbe1323 --- /dev/null +++ b/include/fsl-mc/fsl_qbman_base.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_QBMAN_BASE_H +#define _FSL_QBMAN_BASE_H + +/* Descriptor for a QBMan instance on the SoC. On partitions/targets that do not + * control this QBMan instance, these values may simply be place-holders. The + * idea is simply that we be able to distinguish between them, eg. so that SWP + * descriptors can identify which QBMan instance they belong to. */ +struct qbman_block_desc { + void *ccsr_reg_bar; /* CCSR register map */ + int irq_rerr; /* Recoverable error interrupt line */ + int irq_nrerr; /* Non-recoverable error interrupt line */ +}; + +/* Descriptor for a QBMan software portal, expressed in terms that make sense to + * the user context. Ie. on MC, this information is likely to be true-physical, + * and instantiated statically at compile-time. On GPP, this information is + * likely to be obtained via "discovery" over a partition's "layerscape bus" + * (ie. in response to a MC portal command), and would take into account any + * virtualisation of the GPP user's address space and/or interrupt numbering. */ +struct qbman_swp_desc { + const struct qbman_block_desc *block; /* The QBMan instance */ + void *cena_bar; /* Cache-enabled portal register map */ + void *cinh_bar; /* Cache-inhibited portal register map */ +}; + +/* Driver object for managing a QBMan portal */ +struct qbman_swp; + +/* Place-holder for FDs, we represent it via the simplest form that we need for + * now. Different overlays may be needed to support different options, etc. (It + * is impractical to define One True Struct, because the resulting encoding + * routines (lots of read-modify-writes) would be worst-case performance whether + * or not circumstances required them.) + * + * Note, as with all data-structures exchanged between software and hardware (be + * they located in the portal register map or DMA'd to and from main-memory), + * the driver ensures that the caller of the driver API sees the data-structures + * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words + * contained within this structure are represented in host-endianness, even if + * hardware always treats them as little-endian. As such, if any of these fields + * are interpreted in a binary (rather than numerical) fashion by hardware + * blocks (eg. accelerators), then the user should be careful. We illustrate + * with an example; + * + * Suppose the desired behaviour of an accelerator is controlled by the "frc" + * field of the FDs that are sent to it. Suppose also that the behaviour desired + * by the user corresponds to an "frc" value which is expressed as the literal + * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit + * value in which 0xfe is the first byte and 0xba is the last byte, and as + * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If + * the software is little-endian also, this can simply be achieved by setting + * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set + * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is + * to treat the 32-bit words as numerical values, in which the offset of a field + * from the beginning of the first byte (as required or generated by hardware) + * is numerically encoded by a left-shift (ie. by raising the field to a + * corresponding power of 2). Ie. in the current example, software could set + * "frc" in the following way, and it would work correctly on both little-endian + * and big-endian operation; + * fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24); + */ +struct qbman_fd { + union { + uint32_t words[8]; + struct qbman_fd_simple { + uint32_t addr_lo; + uint32_t addr_hi; + uint32_t len; + /* offset in the MS 16 bits, BPID in the LS 16 bits */ + uint32_t bpid_offset; + uint32_t frc; /* frame context */ + /* "err", "va", "cbmt", "asal", [...] */ + uint32_t ctrl; + /* flow context */ + uint32_t flc_lo; + uint32_t flc_hi; + } simple; + }; +}; + +#endif /* !_FSL_QBMAN_BASE_H */ diff --git a/include/fsl-mc/fsl_qbman_portal.h b/include/fsl-mc/fsl_qbman_portal.h new file mode 100644 index 0000000000..2aadad888b --- /dev/null +++ b/include/fsl-mc/fsl_qbman_portal.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_QBMAN_PORTAL_H +#define _FSL_QBMAN_PORTAL_H + +#include <fsl-mc/fsl_qbman_base.h> + +/* Create and destroy a functional object representing the given QBMan portal + * descriptor. */ +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *); + + /************/ + /* Dequeues */ + /************/ + +/* See the QBMan driver API documentation for details on the enqueue + * mechanisms. NB: the use of a 'ldpaa_' prefix for this type is because it is + * primarily used by the "DPIO" layer that sits above (and hides) the QBMan + * driver. The structure is defined in the DPIO interface, but to avoid circular + * dependencies we just pre/re-declare it here opaquely. */ +struct ldpaa_dq; + + +/* ------------------- */ +/* Pull-mode dequeuing */ +/* ------------------- */ + +struct qbman_pull_desc { + uint32_t dont_manipulate_directly[6]; +}; + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_pull_desc_clear(struct qbman_pull_desc *); +/* If not called, or if called with 'storage' as NULL, the result pull dequeues + * will produce results to DQRR. If 'storage' is non-NULL, then results are + * produced to the given memory location (using the physical/DMA address which + * the caller provides in 'storage_phys'), and 'stash' controls whether or not + * those writes to main-memory express a cache-warming attribute. */ +void qbman_pull_desc_set_storage(struct qbman_pull_desc *, + struct ldpaa_dq *storage, + dma_addr_t storage_phys, + int stash); +/* numframes must be between 1 and 16, inclusive */ +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *, uint8_t numframes); +/* token is the value that shows up in the dequeue results that can be used to + * detect when the results have been published, and is not really used when + * dequeue results go to DQRR. The easiest technique is to zero result "storage" + * before issuing a pull dequeue, and use any non-zero 'token' value. */ +void qbman_pull_desc_set_token(struct qbman_pull_desc *, uint8_t token); +/* Exactly one of the following descriptor "actions" should be set. (Calling any + * one of these will replace the effect of any prior call to one of these.) + * - pull dequeue from the given frame queue (FQ) + * - pull dequeue from any FQ in the given work queue (WQ) + * - pull dequeue from any FQ in any WQ in the given channel + */ +void qbman_pull_desc_set_fq(struct qbman_pull_desc *, uint32_t fqid); + +/* Issue the pull dequeue command */ +int qbman_swp_pull(struct qbman_swp *, struct qbman_pull_desc *); + +/* -------------------------------- */ +/* Polling DQRR for dequeue results */ +/* -------------------------------- */ + +/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry + * only once, so repeated calls can return a sequence of DQRR entries, without + * requiring they be consumed immediately or in any particular order. */ +const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *); +/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ +void qbman_swp_dqrr_consume(struct qbman_swp *, const struct ldpaa_dq *); + +/* ------------------------------------------------- */ +/* Polling user-provided storage for dequeue results */ +/* ------------------------------------------------- */ + +/* Only used for user-provided storage of dequeue results, not DQRR. Prior to + * being used, the storage must set "oldtoken", so that the driver notices when + * hardware has filled it in with results using a "newtoken". NB, for efficiency + * purposes, the driver will perform any required endianness conversion to + * ensure that the user's dequeue result storage is in host-endian format + * (whether or not that is the same as the little-endian format that hardware + * DMA'd to the user's storage). As such, once the user has called + * qbman_dq_entry_has_newtoken() and been returned a valid dequeue result, they + * should not call it again on the same memory location (except of course if + * another dequeue command has been executed to produce a new result to that + * location). + */ +void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *, + unsigned int num_entries, + uint8_t oldtoken); +int qbman_dq_entry_has_newtoken(struct qbman_swp *, + const struct ldpaa_dq *, + uint8_t newtoken); + +/* -------------------------------------------------------- */ +/* Parsing dequeue entries (DQRR and user-provided storage) */ +/* -------------------------------------------------------- */ + +/* DQRR entries may contain non-dequeue results, ie. notifications */ +int qbman_dq_entry_is_DQ(const struct ldpaa_dq *); + + /************/ + /* Enqueues */ + /************/ + +struct qbman_eq_desc { + uint32_t dont_manipulate_directly[8]; +}; + + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_eq_desc_clear(struct qbman_eq_desc *); +/* Exactly one of the following descriptor "actions" should be set. (Calling + * any one of these will replace the effect of any prior call to one of these.) + * - enqueue without order-restoration + * - enqueue with order-restoration + * - fill a hole in the order-restoration sequence, without any enqueue + * - advance NESN (Next Expected Sequence Number), without any enqueue + * 'respond_success' indicates whether an enqueue response should be DMA'd + * after success (otherwise a response is DMA'd only after failure). + * 'incomplete' indicates that other fragments of the same 'seqnum' are yet to + * be enqueued. + */ +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *, int respond_success); +void qbman_eq_desc_set_response(struct qbman_eq_desc *, + dma_addr_t storage_phys, + int stash); +/* token is the value that shows up in an enqueue response that can be used to + * detect when the results have been published. The easiest technique is to zero + * result "storage" before issuing an enqueue, and use any non-zero 'token' + * value. */ +void qbman_eq_desc_set_token(struct qbman_eq_desc *, uint8_t token); +/* Exactly one of the following descriptor "targets" should be set. (Calling any + * one of these will replace the effect of any prior call to one of these.) + * - enqueue to a frame queue + * - enqueue to a queuing destination + * Note, that none of these will have any affect if the "action" type has been + * set to "orp_hole" or "orp_nesn". + */ +void qbman_eq_desc_set_fq(struct qbman_eq_desc *, uint32_t fqid); +void qbman_eq_desc_set_qd(struct qbman_eq_desc *, uint32_t qdid, + uint32_t qd_bin, uint32_t qd_prio); + +/* Issue an enqueue command. ('fd' should only be NULL if the "action" of the + * descriptor is "orp_hole" or "orp_nesn".) */ +int qbman_swp_enqueue(struct qbman_swp *, const struct qbman_eq_desc *, + const struct qbman_fd *fd); + + /*******************/ + /* Buffer releases */ + /*******************/ + +struct qbman_release_desc { + uint32_t dont_manipulate_directly[1]; +}; + +/* Clear the contents of a descriptor to default/starting state. */ +void qbman_release_desc_clear(struct qbman_release_desc *); +/* Set the ID of the buffer pool to release to */ +void qbman_release_desc_set_bpid(struct qbman_release_desc *, uint32_t bpid); +/* Issue a release command. 'num_buffers' must be less than 8. */ +int qbman_swp_release(struct qbman_swp *, const struct qbman_release_desc *, + const uint64_t *buffers, unsigned int num_buffers); + + /*******************/ + /* Buffer acquires */ + /*******************/ + +int qbman_swp_acquire(struct qbman_swp *, uint32_t bpid, uint64_t *buffers, + unsigned int num_buffers); +#endif /* !_FSL_QBMAN_PORTAL_H */ diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h new file mode 100644 index 0000000000..ca8e440bd9 --- /dev/null +++ b/include/fsl-mc/ldpaa_wriop.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LDPAA_WRIOP_H +#define __LDPAA_WRIOP_H + + #include <phy.h> + +enum wriop_port { + WRIOP1_DPMAC1 = 1, + WRIOP1_DPMAC2, + WRIOP1_DPMAC3, + WRIOP1_DPMAC4, + WRIOP1_DPMAC5, + WRIOP1_DPMAC6, + WRIOP1_DPMAC7, + WRIOP1_DPMAC8, + WRIOP1_DPMAC9, + WRIOP1_DPMAC10, + WRIOP1_DPMAC11, + WRIOP1_DPMAC12, + WRIOP1_DPMAC13, + WRIOP1_DPMAC14, + WRIOP1_DPMAC15, + WRIOP1_DPMAC16, + WRIOP1_DPMAC17, + WRIOP1_DPMAC18, + WRIOP1_DPMAC19, + WRIOP1_DPMAC20, + WRIOP1_DPMAC21, + WRIOP1_DPMAC22, + WRIOP1_DPMAC23, + WRIOP1_DPMAC24, + NUM_WRIOP_PORTS, +}; + +struct wriop_dpmac_info { + u8 enabled; + u8 id; + u8 phy_addr; + u8 board_mux; + void *phy_regs; + phy_interface_t enet_if; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; + +#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0" +#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1" + +void wriop_init_dpmac(int, int, int); +void wriop_disable_dpmac(int); +void wriop_enable_dpmac(int); +void wriop_set_mdio(int, struct mii_dev *); +struct mii_dev *wriop_get_mdio(int); +void wriop_set_phy_address(int, int); +int wriop_get_phy_address(int); +void wriop_set_phy_dev(int, struct phy_device *); +struct phy_device *wriop_get_phy_dev(int); +phy_interface_t wriop_get_enet_if(int); + +void wriop_dpmac_disable(int); +void wriop_dpmac_enable(int); +phy_interface_t wriop_dpmac_enet_if(int, int); +#endif /* __LDPAA_WRIOP_H */ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index feccef9c9c..4099a74a4a 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -34,9 +34,7 @@ #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR - -u32 fsl_ddr_get_version(void); +u32 fsl_ddr_get_version(unsigned int ctrl_num); #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 095b33e29e..e5b6e03c8f 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -155,6 +155,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 #define MD_CNTL_WRCW 0x00080000 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) +#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) +#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 @@ -165,6 +167,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define DDR_CDR2_VREF_RANGE_2 0x00000040 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) diff --git a/include/fsl_debug_server.h b/include/fsl_debug_server.h new file mode 100644 index 0000000000..28d8adbe11 --- /dev/null +++ b/include/fsl_debug_server.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DBG_SERVER_H__ +#define __FSL_DBG_SERVER_H__ + +#include <asm/io.h> +#include <common.h> + +/* + * Define Debug Server firmware version information + */ + +/* Major version number: incremented on API compatibility changes */ +#define DEBUG_SERVER_VER_MAJOR 0 + +/* Minor version number: incremented on API additions (backward + * compatible); reset when major version is incremented. + */ +#define DEBUG_SERVER_VER_MINOR 1 + +#define DEBUG_SERVER_INIT_STATUS (1 << 0) +#define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001) + +int debug_server_init(void); +unsigned long debug_server_get_dram_block_size(void); + +#endif /* __FSL_DBG_SERVER_H__ */ + diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h new file mode 100644 index 0000000000..b569b4d2b6 --- /dev/null +++ b/include/fsl_dspi.h @@ -0,0 +1,150 @@ +/* + * Freescale DSPI Module Defines + * + * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * Chao Fu (B44548@freesacle.com) + * Haikun Wang (B53464@freescale.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_DSPI_H_ +#define _FSL_DSPI_H_ + +/* DMA Serial Peripheral Interface (DSPI) */ +struct dspi { + u32 mcr; /* 0x00 */ + u32 resv0; /* 0x04 */ + u32 tcr; /* 0x08 */ + u32 ctar[8]; /* 0x0C - 0x28 */ + u32 sr; /* 0x2C */ + u32 irsr; /* 0x30 */ + u32 tfr; /* 0x34 - PUSHR */ + u32 rfr; /* 0x38 - POPR */ +#ifdef CONFIG_MCF547x_8x + u32 tfdr[4]; /* 0x3C */ + u8 resv2[0x30]; /* 0x40 */ + u32 rfdr[4]; /* 0x7C */ +#else + u32 tfdr[16]; /* 0x3C */ + u32 rfdr[16]; /* 0x7C */ +#endif +}; + +/* Module configuration */ +#define DSPI_MCR_MSTR 0x80000000 +#define DSPI_MCR_CSCK 0x40000000 +#define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) +#define DSPI_MCR_FRZ 0x08000000 +#define DSPI_MCR_MTFE 0x04000000 +#define DSPI_MCR_PCSSE 0x02000000 +#define DSPI_MCR_ROOE 0x01000000 +#define DSPI_MCR_PCSIS(x) (1 << (16 + (x))) +#define DSPI_MCR_PCSIS_MASK (0xff << 16) +#define DSPI_MCR_CSIS7 0x00800000 +#define DSPI_MCR_CSIS6 0x00400000 +#define DSPI_MCR_CSIS5 0x00200000 +#define DSPI_MCR_CSIS4 0x00100000 +#define DSPI_MCR_CSIS3 0x00080000 +#define DSPI_MCR_CSIS2 0x00040000 +#define DSPI_MCR_CSIS1 0x00020000 +#define DSPI_MCR_CSIS0 0x00010000 +#define DSPI_MCR_DOZE 0x00008000 +#define DSPI_MCR_MDIS 0x00004000 +#define DSPI_MCR_DTXF 0x00002000 +#define DSPI_MCR_DRXF 0x00001000 +#define DSPI_MCR_CTXF 0x00000800 +#define DSPI_MCR_CRXF 0x00000400 +#define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8) +#define DSPI_MCR_FCPCS 0x00000001 +#define DSPI_MCR_PES 0x00000001 +#define DSPI_MCR_HALT 0x00000001 + +/* Transfer count */ +#define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16) + +/* Clock and transfer attributes */ +#define DSPI_CTAR(x) (0x0c + (x * 4)) +#define DSPI_CTAR_DBR 0x80000000 +#define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27) +#define DSPI_CTAR_CPOL 0x04000000 +#define DSPI_CTAR_CPHA 0x02000000 +#define DSPI_CTAR_LSBFE 0x01000000 +#define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22) +#define DSPI_CTAR_PCSSCK_7CLK 0x00A00000 +#define DSPI_CTAR_PCSSCK_5CLK 0x00800000 +#define DSPI_CTAR_PCSSCK_3CLK 0x00400000 +#define DSPI_CTAR_PCSSCK_1CLK 0x00000000 +#define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20) +#define DSPI_CTAR_PASC_7CLK 0x00300000 +#define DSPI_CTAR_PASC_5CLK 0x00200000 +#define DSPI_CTAR_PASC_3CLK 0x00100000 +#define DSPI_CTAR_PASC_1CLK 0x00000000 +#define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18) +#define DSPI_CTAR_PDT_7CLK 0x000A0000 +#define DSPI_CTAR_PDT_5CLK 0x00080000 +#define DSPI_CTAR_PDT_3CLK 0x00040000 +#define DSPI_CTAR_PDT_1CLK 0x00000000 +#define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16) +#define DSPI_CTAR_PBR_7CLK 0x00030000 +#define DSPI_CTAR_PBR_5CLK 0x00020000 +#define DSPI_CTAR_PBR_3CLK 0x00010000 +#define DSPI_CTAR_PBR_1CLK 0x00000000 +#define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12) +#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8) +#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4) +#define DSPI_CTAR_BR(x) ((x) & 0x0F) + +/* Status */ +#define DSPI_SR_TCF 0x80000000 +#define DSPI_SR_TXRXS 0x40000000 +#define DSPI_SR_EOQF 0x10000000 +#define DSPI_SR_TFUF 0x08000000 +#define DSPI_SR_TFFF 0x02000000 +#define DSPI_SR_RFOF 0x00080000 +#define DSPI_SR_RFDF 0x00020000 +#define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12) +#define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8) +#define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4) +#define DSPI_SR_RXPTR(x) ((x) & 0x0000000F) + +/* DMA/interrupt request selct and enable */ +#define DSPI_IRSR_TCFE 0x80000000 +#define DSPI_IRSR_EOQFE 0x10000000 +#define DSPI_IRSR_TFUFE 0x08000000 +#define DSPI_IRSR_TFFFE 0x02000000 +#define DSPI_IRSR_TFFFS 0x01000000 +#define DSPI_IRSR_RFOFE 0x00080000 +#define DSPI_IRSR_RFDFE 0x00020000 +#define DSPI_IRSR_RFDFS 0x00010000 + +/* Transfer control - 32-bit access */ +#define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16) +#define DSPI_TFR_CONT 0x80000000 +#define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28) +#define DSPI_TFR_EOQ 0x08000000 +#define DSPI_TFR_CTCNT 0x04000000 +#define DSPI_TFR_CS7 0x00800000 +#define DSPI_TFR_CS6 0x00400000 +#define DSPI_TFR_CS5 0x00200000 +#define DSPI_TFR_CS4 0x00100000 +#define DSPI_TFR_CS3 0x00080000 +#define DSPI_TFR_CS2 0x00040000 +#define DSPI_TFR_CS1 0x00020000 +#define DSPI_TFR_CS0 0x00010000 + +/* Transfer Fifo */ +#define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF) + +/* Bit definitions and macros for DRFR */ +#define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF) + +/* Bit definitions and macros for DTFDR group */ +#define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF) +#define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16) + +/* Bit definitions and macros for DRFDR group */ +#define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF) + +#endif /* _FSL_DSPI_H_ */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 57295b4bc0..41bf05be4c 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -158,7 +158,11 @@ #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ struct fsl_esdhc_cfg { +#ifdef CONFIG_LS2085A + u64 esdhc_base; +#else u32 esdhc_base; +#endif u32 sdhc_clk; u8 max_bus_width; struct mmc_config cfg; diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 11474b757c..a7ddd5fc88 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -790,24 +790,36 @@ extern void print_ifc_regs(void); extern void init_early_memctl_regs(void); void init_final_memctl_regs(void); -#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) - -#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) \ - (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) \ - (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) -#define set_ifc_ftim(i, j, v) \ - (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) +#define IFC_RREGS_4KOFFSET (4*1024) +#define IFC_RREGS_64KOFFSET (64*1024) + +#define IFC_FCM_BASE_ADDR \ + ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr_ext(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) \ + (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, @@ -869,20 +881,26 @@ struct fsl_ifc_nand { u32 nand_evter_en; u32 res17[0x2]; u32 nand_evter_intr_en; - u32 res18[0x2]; + u32 nand_vol_addr_stat; + u32 res18; u32 nand_erattr0; u32 nand_erattr1; u32 res19[0x10]; u32 nand_fsr; - u32 res20; - u32 nand_eccstat[4]; - u32 res21[0x20]; + u32 res20[0x3]; + u32 nand_eccstat[6]; + u32 res21[0x1c]; u32 nanndcr; u32 res22[0x2]; u32 nand_autoboot_trgr; u32 res23; u32 nand_mdr; - u32 res24[0x5C]; + u32 res24[0x1c]; + u32 nand_dll_lowcfg0; + u32 nand_dll_lowcfg1; + u32 res25; + u32 nand_dll_lowstat; + u32 res26[0x3C]; }; /* @@ -917,7 +935,6 @@ struct fsl_ifc_gpcm { u32 gpcm_erattr1; u32 gpcm_erattr2; u32 gpcm_stat; - u32 res4[0x1F3]; }; #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT @@ -965,9 +982,11 @@ struct fsl_ifc_ftim { }; /* - * IFC Controller Registers + * IFC Controller Global Registers + * FCM - Flash control machine */ -struct fsl_ifc { + +struct fsl_ifc_fcm { u32 ifc_rev; u32 res1[0x2]; struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; @@ -979,7 +998,8 @@ struct fsl_ifc { struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; u32 rb_stat; - u32 res6[0x2]; + u32 rb_map; + u32 wp_map; u32 ifc_gcr; u32 res7[0x2]; u32 cm_evter_stat; @@ -993,12 +1013,20 @@ struct fsl_ifc { u32 res11[0x2]; u32 ifc_ccr; u32 ifc_csr; - u32 res12[0x2EB]; + u32 ddr_ccr_low; +}; + +struct fsl_ifc_runtime { struct fsl_ifc_nand ifc_nand; struct fsl_ifc_nor ifc_nor; struct fsl_ifc_gpcm ifc_gpcm; }; +struct fsl_ifc { + struct fsl_ifc_fcm *gregs; + struct fsl_ifc_runtime *rregs; +}; + #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #undef CSPR_MSEL_NOR #define CSPR_MSEL_NOR CSPR_MSEL_GPCM diff --git a/include/fsl_memac.h b/include/fsl_memac.h new file mode 100644 index 0000000000..bed2a40bb2 --- /dev/null +++ b/include/fsl_memac.h @@ -0,0 +1,264 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang <tie-fei.zang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MEMAC_H__ +#define __MEMAC_H__ + +#include <phy.h> + +struct memac { + /* memac general control and status registers */ + u32 res_0[2]; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 res_18[5]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res_30[4]; + u32 ievent; /* Interrupt event register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 res_48; + u32 imask; /* interrupt mask register */ + u32 res_50; + u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */ + u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */ + u32 rx_pause_status; /* Receive pause status register */ + u32 res_78[2]; + u32 mac_addr[14]; /* MAC address */ + u32 lpwake_timer; /* EEE low power wakeup timer register */ + u32 sleep_timer; /* Transmit EEE Low Power Timer register */ + u32 res_c0[8]; + u32 statn_config; /* Statistics configuration register */ + u32 res_e4[7]; + + /* memac statistics counter registers */ + u32 rx_eoct_l; /* Rx ethernet octests lower */ + u32 rx_eoct_u; /* Rx ethernet octests upper */ + u32 rx_oct_l; /* Rx octests lower */ + u32 rx_oct_u; /* Rx octests upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_undsz_l; /* Rx undersized packet lower */ + u32 rx_undsz_u; /* Rx undersized packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_oversz_l; /* Rx oversized packet lower */ + u32 rx_oversz_u; /* Rx oversized packet upper */ + u32 rx_jabber_l; /* Rx Jabber packet lower */ + u32 rx_jabber_u; /* Rx Jabber packet upper */ + u32 rx_frag_l; /* Rx Fragment packet lower */ + u32 rx_frag_u; /* Rx Fragment packet upper */ + u32 rx_cnp_l; /* Rx control packet lower */ + u32 rx_cnp_u; /* Rx control packet upper */ + u32 rx_drntp_l; /* Rx dripped not truncated packet lower */ + u32 rx_drntp_u; /* Rx dripped not truncated packet upper */ + u32 res_1d0[0xc]; + + u32 tx_eoct_l; /* Tx ethernet octests lower */ + u32 tx_eoct_u; /* Tx ethernet octests upper */ + u32 tx_oct_l; /* Tx octests lower */ + u32 tx_oct_u; /* Tx octests upper */ + u32 res_210[0x2]; + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */ + u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 res_258[0x2]; + u32 tx_pkt_l; /* Tx packets lower */ + u32 tx_pkt_u; /* Tx packets upper */ + u32 tx_undsz_l; /* Tx undersized packet lower */ + u32 tx_undsz_u; /* Tx undersized packet upper */ + u32 tx_64_l; /* Tx 64 oct packet lower */ + u32 tx_64_u; /* Tx 64 oct packet upper */ + u32 tx_127_l; /* Tx 65 to 127 oct packet lower */ + u32 tx_127_u; /* Tx 65 to 127 oct packet upper */ + u32 tx_255_l; /* Tx 128 to 255 oct packet lower */ + u32 tx_255_u; /* Tx 128 to 255 oct packet upper */ + u32 tx_511_l; /* Tx 256 to 511 oct packet lower */ + u32 tx_511_u; /* Tx 256 to 511 oct packet upper */ + u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */ + u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */ + u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */ + u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */ + u32 tx_1519_l; /* Tx 1519 to max oct packet lower */ + u32 tx_1519_u; /* Tx 1519 to max oct packet upper */ + u32 res_2a8[0x6]; + u32 tx_cnp_l; /* Tx control packet lower */ + u32 tx_cnp_u; /* Tx control packet upper */ + u32 res_2c8[0xe]; + + /* Line interface control register */ + u32 if_mode; /* interface mode control */ + u32 if_status; /* interface status */ + u32 res_308[0xe]; + + /* HiGig/2 Register */ + u32 hg_config; /* HiGig2 control and configuration */ + u32 res_344[0x3]; + u32 hg_pause_quanta; /* HiGig2 pause quanta */ + u32 res_354[0x3]; + u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */ + u32 res_364[0x3]; + u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */ + u32 hg_fifos_status; /* HiGig2 fifos status */ + u32 rhm; /* Rx HiGig2 message counter register */ + u32 thm;/* Tx HiGig2 message counter register */ + u32 res_380[0x320]; +}; + +/* COMMAND_CONFIG - command and configuration register */ +#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IF_MODE - Interface Mode Register */ +#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ +#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */ +#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */ +#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */ +#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */ +#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ +#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ +#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ +#define IF_MODE_RG 0x00000004 /* 1- RGMII */ +#define IF_MODE_RM 0x00000008 /* 1- RGMII */ + +#define IF_DEFAULT (IF_GMII) + +/* Internal PHY Registers - SGMII */ +#define PHY_SGMII_CR_PHY_RESET 0x8000 +#define PHY_SGMII_CR_RESET_AN 0x0200 +#define PHY_SGMII_CR_DEF_VAL 0x1140 +#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 +#define PHY_SGMII_IF_MODE_AN 0x0002 +#define PHY_SGMII_IF_MODE_SGMII 0x0001 + +struct memac_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_STAT_PRE (1 << 5) +#define MDIO_STAT_ENC (1 << 6) +#define MDIO_STAT_HOLD_15_CLK (7 << 2) +#define MDIO_STAT_NEG (1 << 23) + +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/include/fsl_usb.h b/include/fsl_usb.h index d251f5d4ce..33d9f03096 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -87,6 +87,33 @@ struct ccsr_usb_phy { /* USB Erratum Checking code */ #ifdef CONFIG_PPC +static inline bool has_dual_phy(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T1023: + case SVR_T1024: + case SVR_T1013: + case SVR_T1014: + return IS_SVR_REV(svr, 1, 0); + case SVR_T1040: + case SVR_T1042: + case SVR_T1020: + case SVR_T1022: + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_T4240: + case SVR_T4160: + case SVR_T4080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + } + + return false; +} + static inline bool has_erratum_a006261(void) { u32 svr = get_svr(); @@ -155,8 +182,13 @@ static inline bool has_erratum_a007792(void) case SVR_T4240: case SVR_T4160: return IS_SVR_REV(svr, 2, 0); - case SVR_T1040: + case SVR_T1024: + case SVR_T1023: return IS_SVR_REV(svr, 1, 0); + case SVR_T1040: + case SVR_T1042: + case SVR_T1020: + case SVR_T1022: case SVR_T2080: case SVR_T2081: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); @@ -164,7 +196,25 @@ static inline bool has_erratum_a007792(void) return false; } +static inline bool has_erratum_a005697(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_9131: + case SVR_9132: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + return false; +} + #else +static inline bool has_dual_phy(void) +{ + return false; +} + static inline bool has_erratum_a006261(void) { return false; @@ -184,5 +234,10 @@ static inline bool has_erratum_a007792(void) { return false; } + +static inline bool has_erratum_a005697(void) +{ + return false; +} #endif #endif /*_ASM_FSL_USB_H_ */ diff --git a/include/i2c.h b/include/i2c.h index 31b038991e..6fd73fae4c 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -64,8 +64,8 @@ struct dm_i2c_chip { * bus can operate at different speeds (measured in Hz, typically 100KHz * or 400KHz). * - * To obtain this structure, use bus->uclass_priv where bus is the I2C - * bus udevice. + * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the + * I2C bus udevice. * * @speed_hz: Bus speed in hertz (typically 100000) */ @@ -340,7 +340,7 @@ struct dm_i2c_ops { * The bus speed value will be updated by the uclass if this function * does not return an error. This method is optional - if it is not * provided then the driver can read the speed from - * bus->uclass_priv->speed_hz + * dev_get_uclass_priv(bus)->speed_hz * * @bus: Bus to adjust * @speed: Requested speed in Hz @@ -354,7 +354,7 @@ struct dm_i2c_ops { * Normally this can be provided by the uclass, but if you want your * driver to check the bus speed by looking at the hardware, you can * implement that here. This method is optional. This method would - * normally be expected to return bus->uclass_priv->speed_hz. + * normally be expected to return dev_get_uclass_priv(bus)->speed_hz. * * @bus: Bus to check * @return speed of selected I2C bus in Hz, -ve on error diff --git a/include/lcd.h b/include/lcd.h index f049fd3489..59202b7e59 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -51,6 +51,7 @@ void lcd_set_flush_dcache(int flush); typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 160) */ ushort vl_row; /* Number of rows (i.e. 100) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ u_char vl_bpix; /* Bits per pixel, 0 = 1 */ ushort *cmap; /* Pointer to the colormap */ void *priv; /* Pointer to driver-specific data */ @@ -196,6 +197,14 @@ void lcd_sync(void); #define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ #endif /* color definitions */ +#if LCD_BPP == LCD_COLOR16 +#define fbptr_t ushort +#elif LCD_BPP == LCD_COLOR32 +#define fbptr_t u32 +#else +#define fbptr_t uchar +#endif + #ifndef PAGE_SIZE #define PAGE_SIZE 4096 #endif diff --git a/include/lcd_console.h b/include/lcd_console.h index 429214df80..2e0f56f990 100644 --- a/include/lcd_console.h +++ b/include/lcd_console.h @@ -9,6 +9,26 @@ #define CONFIG_CONSOLE_SCROLL_LINES 1 #endif +struct console_t { + short curr_col, curr_row; + short cols, rows; + void *fbbase; + u32 lcdsizex, lcdsizey, lcdrot; + void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c); + void (*fp_console_moverow)(struct console_t *pcons, + u32 rowdst, u32 rowsrc); + void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr); +}; + +/** + * console_calc_rowcol() - calculate available rows / columns wihtin a given + * screen-size based on used VIDEO_FONT. + * + * @pcons: Pointer to struct console_t + * @sizex: size X of the screen in pixel + * @sizey: size Y of the screen in pixel + */ +void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey); /** * lcd_init_console() - Initialize lcd console parameters * @@ -16,11 +36,11 @@ * console has. * * @address: Console base address - * @rows: Number of rows in the console - * @cols: Number of columns in the console + * @vl_rows: Number of rows in the console + * @vl_cols: Number of columns in the console + * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise */ -void lcd_init_console(void *address, int rows, int cols); - +void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot); /** * lcd_set_col() - Set the number of the current lcd console column * diff --git a/include/linker_lists.h b/include/linker_lists.h index 940c871281..b22d169d97 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -103,6 +103,16 @@ */ /** + * ll_sym() - Access a linker-generated array entry + * @_type: Data type of the entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + */ +#define llsym(_type, _name, _list) \ + ((_type *)&_u_boot_list_2_##_list##_2_##_name) + +/** * ll_entry_declare() - Declare linker-generated array entry * @_type: Data type of the entry * @_name: Name of the entry diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index b317dcb5fe..6d1f88ec2e 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -24,6 +24,18 @@ #endif #endif +#ifdef CONFIG_LS102XA +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#endif + +#ifdef CONFIG_PPC +#define QE_IMMR_OFFSET 0x00140000 +#else +#define QE_IMMR_OFFSET 0x01400000 +#endif + /* QE I-RAM */ typedef struct qe_iram { u32 iadd; /* I-RAM Address Register */ diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index bd48704c87..822fca0357 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h @@ -379,6 +379,11 @@ struct usb_endpoint_descriptor { #define USB_DT_ENDPOINT_SIZE 7 #define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ +/* Used to access common fields */ +struct usb_generic_descriptor { + __u8 bLength; + __u8 bDescriptorType; +}; /* * Endpoints @@ -1002,4 +1007,17 @@ struct usb_set_sel_req { */ #define USB_SELF_POWER_VBUS_MAX_DRAW 100 +/** + * struct usb_string - wraps a C string and its USB id + * @id:the (nonzero) ID for this string + * @s:the string, in UTF-8 encoding + * + * If you're using usb_gadget_get_string(), use this to wrap a string + * together with its ID. + */ +struct usb_string { + u8 id; + const char *s; +}; + #endif /* __LINUX_USB_CH9_H */ diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 230f47d67e..4adf35e3ae 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -859,19 +859,6 @@ void usb_del_gadget_udc(struct usb_gadget *gadget); /* utility to simplify dealing with string descriptors */ /** - * struct usb_string - wraps a C string and its USB id - * @id:the (nonzero) ID for this string - * @s:the string, in UTF-8 encoding - * - * If you're using usb_gadget_get_string(), use this to wrap a string - * together with its ID. - */ -struct usb_string { - u8 id; - const char *s; -}; - -/** * struct usb_gadget_strings - a set of USB strings in a given language * @language:identifies the strings' language (0x0409 for en-us) * @strings:array of strings with their ids diff --git a/include/malloc.h b/include/malloc.h index 5df634873f..f4da9e6ddd 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -906,6 +906,9 @@ void *realloc_simple(void *ptr, size_t size); #endif +/* Set up pre-relocation malloc() ready for use */ +int initf_malloc(void); + /* Public routines */ /* Simple versions which can be used when space is tight */ diff --git a/include/mapmem.h b/include/mapmem.h new file mode 100644 index 0000000000..42ef3e8c2a --- /dev/null +++ b/include/mapmem.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger <joe.hershberger@ni.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __MAPMEM_H +#define __MAPMEM_H + +/* Define a null map_sysmem() if the architecture doesn't use it */ +# ifdef CONFIG_ARCH_MAP_SYSMEM +#include <asm/io.h> +# else +static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) +{ + return (void *)(uintptr_t)paddr; +} + +static inline void unmap_sysmem(const void *vaddr) +{ +} + +static inline phys_addr_t map_to_sysmem(const void *ptr) +{ + return (phys_addr_t)(uintptr_t)ptr; +} +# endif + +#endif /* __MAPMEM_H */ diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h index 7e210e3296..cc72cde13f 100644 --- a/include/mpc823_lcd.h +++ b/include/mpc823_lcd.h @@ -16,6 +16,7 @@ typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ ushort vl_width; /* Width of display area in millimeters */ ushort vl_height; /* Height of display area in millimeters */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 11d898527b..3753e47edf 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,10 +6,6 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -/* define for common ppc_asm.tmpl */ -#define EXC_OFF_SYS_RESET 0x100 /* System reset */ -#define _START_OFFSET 0 - #if defined(CONFIG_E500) #include <e500.h> #endif diff --git a/include/mvmfp.h b/include/mvmfp.h index 961d79995c..e61e92d4d5 100644 --- a/include/mvmfp.h +++ b/include/mvmfp.h @@ -21,61 +21,77 @@ /* * MFP configuration is represented by a 32-bit unsigned integer */ -#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \ +#ifdef CONFIG_MVMFP_V2 +#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ + /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ + /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ + /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ + /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ + /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ + /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ + /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ + /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) +#else +#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ /* bit 12 - Unused */ \ /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ - /* bit 09 - Pull State flag */ (((_pF) & 0x1) << 9) | \ - /* bit 08 - Drv-strength flag */ (((_dF) & 0x1) << 8) | \ - /* bit 07 - Edge-det flag */ (((_eF) & 0x1) << 7) | \ + /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03..00 - Alt-fun flag */ (((_aF) & 0x1) << 3) | \ - /* bits Alternate-fun select */ ((_afn) & 0x7)) + /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ + /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) +#endif /* * to facilitate the definition, the following macros are provided * * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ -#define MFP_OFFSET_MASK MFP(0xffff, 0,0, 0,0, 0,0, 0,0) -#define MFP_REG(x) MFP(x, 0,0, 0,0, 0,0, 0,0) +#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) +#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) #define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) -#define MFP_AF_FLAG MFP(0x0000, 0,0, 0,0, 0,0, 0,1) -#define MFP_DRIVE_FLAG MFP(0x0000, 0,0, 0,1, 0,0, 0,0) -#define MFP_EDGE_FLAG MFP(0x0000, 0,0, 0,0, 0,1, 0,0) -#define MFP_PULL_FLAG MFP(0x0000, 0,1, 0,0, 0,0, 0,0) +#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) +#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) +#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) +#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) +#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) +#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) +#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) +#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) + +#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) +#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) +#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) +#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) +#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) -#define MFP_AF0 MFP(0x0000, 0,0, 0,0, 0,0, 0,1) -#define MFP_AF1 MFP(0x0000, 0,0, 0,0, 0,0, 1,1) -#define MFP_AF2 MFP(0x0000, 0,0, 0,0, 0,0, 2,1) -#define MFP_AF3 MFP(0x0000, 0,0, 0,0, 0,0, 3,1) -#define MFP_AF4 MFP(0x0000, 0,0, 0,0, 0,0, 4,1) -#define MFP_AF5 MFP(0x0000, 0,0, 0,0, 0,0, 5,1) -#define MFP_AF6 MFP(0x0000, 0,0, 0,0, 0,0, 6,1) -#define MFP_AF7 MFP(0x0000, 0,0, 0,0, 0,0, 7,1) -#define MFP_AF_MASK MFP(0x0000, 0,0, 0,0, 0,0, 7,0) +#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) +#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) +#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) +#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) +#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) -#define MFP_LPM_EDGE_NONE MFP(0x0000, 0,0, 0,0, 0,1, 0,0) -#define MFP_LPM_EDGE_RISE MFP(0x0000, 0,0, 0,0, 1,1, 0,0) -#define MFP_LPM_EDGE_FALL MFP(0x0000, 0,0, 0,0, 2,1, 0,0) -#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0,0, 0,0, 3,1, 0,0) -#define MFP_LPM_EDGE_MASK MFP(0x0000, 0,0, 0,0, 3,0, 0,0) +#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) -#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0,0, 0,1, 0,0, 0,0) -#define MFP_DRIVE_SLOW MFP(0x0000, 0,0, 1,1, 0,0, 0,0) -#define MFP_DRIVE_MEDIUM MFP(0x0000, 0,0, 2,1, 0,0, 0,0) -#define MFP_DRIVE_FAST MFP(0x0000, 0,0, 3,1, 0,0, 0,0) -#define MFP_DRIVE_MASK MFP(0x0000, 0,0, 3,0, 0,0, 0,0) +#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) +#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) +#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) +#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) -#define MFP_PULL_NONE MFP(0x0000, 0,1, 0,0, 0,0, 0,0) -#define MFP_PULL_LOW MFP(0x0000, 1,1, 0,0, 0,0, 0,0) -#define MFP_PULL_HIGH MFP(0x0000, 2,1, 0,0, 0,0, 0,0) -#define MFP_PULL_BOTH MFP(0x0000, 3,1, 0,0, 0,0, 0,0) -#define MFP_PULL_FLOAT MFP(0x0000, 4,1, 0,0, 0,0, 0,0) -#define MFP_PULL_MASK MFP(0x0000, 7,0, 0,0, 0,0, 0,0) +#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) +#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) +#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) +#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) +#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) +#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ + | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ + | MFP_AF_MASK) #define MFP_EOC 0xffffffff /* indicates end-of-conf */ /* Functions */ diff --git a/include/net.h b/include/net.h index 237c932be3..d17173d818 100644 --- a/include/net.h +++ b/include/net.h @@ -39,8 +39,9 @@ #define PKTALIGN ARCH_DMA_MINALIGN /* IPv4 addresses are always 32 bits in size */ -typedef __be32 IPaddr_t; - +struct in_addr { + __be32 s_addr; +}; /** * An incoming packet handler. @@ -51,7 +52,7 @@ typedef __be32 IPaddr_t; * @param len packet length */ typedef void rxhand_f(uchar *pkt, unsigned dport, - IPaddr_t sip, unsigned sport, + struct in_addr sip, unsigned sport, unsigned len); /** @@ -65,7 +66,7 @@ typedef void rxhand_f(uchar *pkt, unsigned dport, * @param len packet length */ typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport, - IPaddr_t sip, unsigned sport, uchar *pkt, unsigned len); + struct in_addr sip, unsigned sport, uchar *pkt, unsigned len); /* * A timeout handler. Called after time interval has expired. @@ -78,32 +79,94 @@ enum eth_state_t { ETH_STATE_ACTIVE }; +#ifdef CONFIG_DM_ETH +/** + * struct eth_pdata - Platform data for Ethernet MAC controllers + * + * @iobase: The base address of the hardware registers + * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env + * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_... + */ +struct eth_pdata { + phys_addr_t iobase; + unsigned char enetaddr[6]; + int phy_interface; +}; + +/** + * struct eth_ops - functions of Ethernet MAC controllers + * + * start: Prepare the hardware to send and receive packets + * send: Send the bytes passed in "packet" as a packet on the wire + * recv: Check if the hardware received a packet. If so, set the pointer to the + * packet buffer in the packetp parameter. If not, return an error or 0 to + * indicate that the hardware receive FIFO is empty. If 0 is returned, the + * network stack will not process the empty packet, but free_pkt() will be + * called if supplied + * free_pkt: Give the driver an opportunity to manage its packet buffer memory + * when the network stack is finished processing it. This will only be + * called when no error was returned from recv - optional + * stop: Stop the hardware from looking for packets - may be called even if + * state == PASSIVE + * mcast: Join or leave a multicast group (for TFTP) - optional + * write_hwaddr: Write a MAC address to the hardware (used to pass it to Linux + * on some platforms like ARM). This function expects the + * eth_pdata::enetaddr field to be populated - optional + * read_rom_hwaddr: Some devices have a backup of the MAC address stored in a + * ROM on the board. This is how the driver should expose it + * to the network stack. This function should fill in the + * eth_pdata::enetaddr field - optional + */ +struct eth_ops { + int (*start)(struct udevice *dev); + int (*send)(struct udevice *dev, void *packet, int length); + int (*recv)(struct udevice *dev, uchar **packetp); + int (*free_pkt)(struct udevice *dev, uchar *packet, int length); + void (*stop)(struct udevice *dev); +#ifdef CONFIG_MCAST_TFTP + int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join); +#endif + int (*write_hwaddr)(struct udevice *dev); + int (*read_rom_hwaddr)(struct udevice *dev); +}; + +#define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) + +struct udevice *eth_get_dev(void); /* get the current device */ +/* + * The devname can be either an exact name given by the driver or device tree + * or it can be an alias of the form "eth%d" + */ +struct udevice *eth_get_dev_by_name(const char *devname); +unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ +/* Used only when NetConsole is enabled */ +int eth_init_state_only(void); /* Set active state */ +void eth_halt_state_only(void); /* Set passive state */ +#endif + +#ifndef CONFIG_DM_ETH struct eth_device { char name[16]; unsigned char enetaddr[6]; phys_addr_t iobase; int state; - int (*init) (struct eth_device *, bd_t *); - int (*send) (struct eth_device *, void *packet, int length); - int (*recv) (struct eth_device *); - void (*halt) (struct eth_device *); + int (*init)(struct eth_device *, bd_t *); + int (*send)(struct eth_device *, void *packet, int length); + int (*recv)(struct eth_device *); + void (*halt)(struct eth_device *); #ifdef CONFIG_MCAST_TFTP - int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set); + int (*mcast)(struct eth_device *, const u8 *enetaddr, u8 set); #endif - int (*write_hwaddr) (struct eth_device *); + int (*write_hwaddr)(struct eth_device *); struct eth_device *next; int index; void *priv; }; -extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ -extern int eth_register(struct eth_device* dev);/* Register network device */ -extern int eth_unregister(struct eth_device *dev);/* Remove network device */ -extern void eth_try_another(int first_restart); /* Change the device */ -extern void eth_set_current(void); /* set nterface to ethcur var */ +int eth_register(struct eth_device *dev);/* Register network device */ +int eth_unregister(struct eth_device *dev);/* Remove network device */ -/* get the current device MAC */ extern struct eth_device *eth_current; static inline __attribute__((always_inline)) @@ -111,39 +174,19 @@ struct eth_device *eth_get_dev(void) { return eth_current; } -extern struct eth_device *eth_get_dev_by_name(const char *devname); -extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ -extern int eth_get_dev_index(void); /* get the device index */ -extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr); -extern int eth_getenv_enetaddr(char *name, uchar *enetaddr); -extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); +struct eth_device *eth_get_dev_by_name(const char *devname); +struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ -/* - * Get the hardware address for an ethernet interface . - * Args: - * base_name - base name for device (normally "eth") - * index - device index number (0 for first) - * enetaddr - returns 6 byte hardware address - * Returns: - * Return true if the address is valid. - */ -extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, - uchar *enetaddr); - -extern int usb_eth_initialize(bd_t *bi); -extern int eth_init(bd_t *bis); /* Initialize the device */ -extern int eth_send(void *packet, int length); /* Send a packet */ - -#ifdef CONFIG_API -extern int eth_receive(void *packet, int length); /* Receive a packet*/ -extern void (*push_packet)(void *packet, int length); -#endif -extern int eth_rx(void); /* Check for received packets */ -extern void eth_halt(void); /* stop SCC */ -extern char *eth_get_name(void); /* get name of current device */ +/* get the current device MAC */ +static inline unsigned char *eth_get_ethaddr(void) +{ + if (eth_current) + return eth_current->enetaddr; + return NULL; +} /* Set active state */ -static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis) +static inline __attribute__((always_inline)) int eth_init_state_only(void) { eth_get_dev()->state = ETH_STATE_ACTIVE; @@ -167,8 +210,43 @@ static inline __attribute__((always_inline)) void eth_halt_state_only(void) int eth_write_hwaddr(struct eth_device *dev, const char *base_name, int eth_number); +int usb_eth_initialize(bd_t *bi); +#endif + +int eth_initialize(void); /* Initialize network subsystem */ +void eth_try_another(int first_restart); /* Change the device */ +void eth_set_current(void); /* set nterface to ethcur var */ + +int eth_get_dev_index(void); /* get the device index */ +void eth_parse_enetaddr(const char *addr, uchar *enetaddr); +int eth_getenv_enetaddr(char *name, uchar *enetaddr); +int eth_setenv_enetaddr(char *name, const uchar *enetaddr); + +/* + * Get the hardware address for an ethernet interface . + * Args: + * base_name - base name for device (normally "eth") + * index - device index number (0 for first) + * enetaddr - returns 6 byte hardware address + * Returns: + * Return true if the address is valid. + */ +int eth_getenv_enetaddr_by_index(const char *base_name, int index, + uchar *enetaddr); + +int eth_init(void); /* Initialize the device */ +int eth_send(void *packet, int length); /* Send a packet */ + +#ifdef CONFIG_API +int eth_receive(void *packet, int length); /* Receive a packet*/ +extern void (*push_packet)(void *packet, int length); +#endif +int eth_rx(void); /* Check for received packets */ +void eth_halt(void); /* stop SCC */ +const char *eth_get_name(void); /* get name of current device */ + #ifdef CONFIG_MCAST_TFTP -int eth_mcast_join(IPaddr_t mcast_addr, u8 join); +int eth_mcast_join(struct in_addr mcast_addr, int join); u32 ether_crc(size_t len, unsigned char const *p); #endif @@ -183,9 +261,9 @@ u32 ether_crc(size_t len, unsigned char const *p); */ struct ethernet_hdr { - uchar et_dest[6]; /* Destination node */ - uchar et_src[6]; /* Source node */ - ushort et_protlen; /* Protocol or length */ + u8 et_dest[6]; /* Destination node */ + u8 et_src[6]; /* Source node */ + u16 et_protlen; /* Protocol or length */ }; /* Ethernet header size */ @@ -194,16 +272,16 @@ struct ethernet_hdr { #define ETH_FCS_LEN 4 /* Octets in the FCS */ struct e802_hdr { - uchar et_dest[6]; /* Destination node */ - uchar et_src[6]; /* Source node */ - ushort et_protlen; /* Protocol or length */ - uchar et_dsap; /* 802 DSAP */ - uchar et_ssap; /* 802 SSAP */ - uchar et_ctl; /* 802 control */ - uchar et_snap1; /* SNAP */ - uchar et_snap2; - uchar et_snap3; - ushort et_prot; /* 802 protocol */ + u8 et_dest[6]; /* Destination node */ + u8 et_src[6]; /* Source node */ + u16 et_protlen; /* Protocol or length */ + u8 et_dsap; /* 802 DSAP */ + u8 et_ssap; /* 802 SSAP */ + u8 et_ctl; /* 802 control */ + u8 et_snap1; /* SNAP */ + u8 et_snap2; + u8 et_snap3; + u16 et_prot; /* 802 protocol */ }; /* 802 + SNAP + ethernet header size */ @@ -213,11 +291,11 @@ struct e802_hdr { * Virtual LAN Ethernet header */ struct vlan_ethernet_hdr { - uchar vet_dest[6]; /* Destination node */ - uchar vet_src[6]; /* Source node */ - ushort vet_vlan_type; /* PROT_VLAN */ - ushort vet_tag; /* TAG of VLAN */ - ushort vet_type; /* protocol type */ + u8 vet_dest[6]; /* Destination node */ + u8 vet_src[6]; /* Source node */ + u16 vet_vlan_type; /* PROT_VLAN */ + u16 vet_tag; /* TAG of VLAN */ + u16 vet_type; /* protocol type */ }; /* VLAN Ethernet header size */ @@ -235,16 +313,16 @@ struct vlan_ethernet_hdr { * Internet Protocol (IP) header. */ struct ip_hdr { - uchar ip_hl_v; /* header length and version */ - uchar ip_tos; /* type of service */ - ushort ip_len; /* total length */ - ushort ip_id; /* identification */ - ushort ip_off; /* fragment offset field */ - uchar ip_ttl; /* time to live */ - uchar ip_p; /* protocol */ - ushort ip_sum; /* checksum */ - IPaddr_t ip_src; /* Source IP address */ - IPaddr_t ip_dst; /* Destination IP address */ + u8 ip_hl_v; /* header length and version */ + u8 ip_tos; /* type of service */ + u16 ip_len; /* total length */ + u16 ip_id; /* identification */ + u16 ip_off; /* fragment offset field */ + u8 ip_ttl; /* time to live */ + u8 ip_p; /* protocol */ + u16 ip_sum; /* checksum */ + struct in_addr ip_src; /* Source IP address */ + struct in_addr ip_dst; /* Destination IP address */ }; #define IP_OFFS 0x1fff /* ip offset *= 8 */ @@ -259,20 +337,20 @@ struct ip_hdr { * Internet Protocol (IP) + UDP header. */ struct ip_udp_hdr { - uchar ip_hl_v; /* header length and version */ - uchar ip_tos; /* type of service */ - ushort ip_len; /* total length */ - ushort ip_id; /* identification */ - ushort ip_off; /* fragment offset field */ - uchar ip_ttl; /* time to live */ - uchar ip_p; /* protocol */ - ushort ip_sum; /* checksum */ - IPaddr_t ip_src; /* Source IP address */ - IPaddr_t ip_dst; /* Destination IP address */ - ushort udp_src; /* UDP source port */ - ushort udp_dst; /* UDP destination port */ - ushort udp_len; /* Length of UDP packet */ - ushort udp_xsum; /* Checksum */ + u8 ip_hl_v; /* header length and version */ + u8 ip_tos; /* type of service */ + u16 ip_len; /* total length */ + u16 ip_id; /* identification */ + u16 ip_off; /* fragment offset field */ + u8 ip_ttl; /* time to live */ + u8 ip_p; /* protocol */ + u16 ip_sum; /* checksum */ + struct in_addr ip_src; /* Source IP address */ + struct in_addr ip_dst; /* Destination IP address */ + u16 udp_src; /* UDP source port */ + u16 udp_dst; /* UDP destination port */ + u16 udp_len; /* Length of UDP packet */ + u16 udp_xsum; /* Checksum */ }; #define IP_UDP_HDR_SIZE (sizeof(struct ip_udp_hdr)) @@ -282,14 +360,14 @@ struct ip_udp_hdr { * Address Resolution Protocol (ARP) header. */ struct arp_hdr { - ushort ar_hrd; /* Format of hardware address */ + u16 ar_hrd; /* Format of hardware address */ # define ARP_ETHER 1 /* Ethernet hardware address */ - ushort ar_pro; /* Format of protocol address */ - uchar ar_hln; /* Length of hardware address */ + u16 ar_pro; /* Format of protocol address */ + u8 ar_hln; /* Length of hardware address */ # define ARP_HLEN 6 - uchar ar_pln; /* Length of protocol address */ + u8 ar_pln; /* Length of protocol address */ # define ARP_PLEN 4 - ushort ar_op; /* Operation */ + u16 ar_op; /* Operation */ # define ARPOP_REQUEST 1 /* Request to resolve address */ # define ARPOP_REPLY 2 /* Response to previous request */ @@ -301,16 +379,16 @@ struct arp_hdr { * the sizes above, and are defined as appropriate for * specific hardware/protocol combinations. */ - uchar ar_data[0]; + u8 ar_data[0]; #define ar_sha ar_data[0] #define ar_spa ar_data[ARP_HLEN] #define ar_tha ar_data[ARP_HLEN + ARP_PLEN] #define ar_tpa ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN] #if 0 - uchar ar_sha[]; /* Sender hardware address */ - uchar ar_spa[]; /* Sender protocol address */ - uchar ar_tha[]; /* Target hardware address */ - uchar ar_tpa[]; /* Target protocol address */ + u8 ar_sha[]; /* Sender hardware address */ + u8 ar_spa[]; /* Sender protocol address */ + u8 ar_tha[]; /* Target hardware address */ + u8 ar_tpa[]; /* Target protocol address */ #endif /* 0 */ }; @@ -332,20 +410,20 @@ struct arp_hdr { #define ICMP_NOT_REACH_PORT 3 /* Port unreachable */ struct icmp_hdr { - uchar type; - uchar code; - ushort checksum; + u8 type; + u8 code; + u16 checksum; union { struct { - ushort id; - ushort sequence; + u16 id; + u16 sequence; } echo; - ulong gateway; + u32 gateway; struct { - ushort unused; - ushort mtu; + u16 unused; + u16 mtu; } frag; - uchar data[0]; + u8 data[0]; } un; }; @@ -383,105 +461,104 @@ struct icmp_hdr { * * Note: * - * All variables of type IPaddr_t are stored in NETWORK byte order + * All variables of type struct in_addr are stored in NETWORK byte order * (big endian). */ /* net.c */ /** BOOTP EXTENTIONS **/ -extern IPaddr_t NetOurGatewayIP; /* Our gateway IP address */ -extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown) */ -extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown) */ +extern struct in_addr net_gateway; /* Our gateway IP address */ +extern struct in_addr net_netmask; /* Our subnet mask (0 = unknown) */ +/* Our Domain Name Server (0 = unknown) */ +extern struct in_addr net_dns_server; #if defined(CONFIG_BOOTP_DNS2) -extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown) */ +/* Our 2nd Domain Name Server (0 = unknown) */ +extern struct in_addr net_dns_server2; #endif -extern char NetOurNISDomain[32]; /* Our NIS domain */ -extern char NetOurHostName[32]; /* Our hostname */ -extern char NetOurRootPath[64]; /* Our root path */ -extern ushort NetBootFileSize; /* Our boot file size in blocks */ +extern char net_nis_domain[32]; /* Our IS domain */ +extern char net_hostname[32]; /* Our hostname */ +extern char net_root_path[64]; /* Our root path */ /** END OF BOOTP EXTENTIONS **/ -extern ulong NetBootFileXferSize; /* size of bootfile in bytes */ -extern uchar NetOurEther[6]; /* Our ethernet address */ -extern uchar NetServerEther[6]; /* Boot server enet address */ -extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */ -extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */ -extern uchar *NetTxPacket; /* THE transmit packet */ -extern uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */ -extern uchar *NetRxPacket; /* Current receive packet */ -extern int NetRxPacketLen; /* Current rx packet length */ -extern unsigned NetIPID; /* IP ID (counting) */ -extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */ -extern uchar NetEtherNullAddr[6]; +extern u8 net_ethaddr[6]; /* Our ethernet address */ +extern u8 net_server_ethaddr[6]; /* Boot server enet address */ +extern struct in_addr net_ip; /* Our IP addr (0 = unknown) */ +extern struct in_addr net_server_ip; /* Server IP addr (0 = unknown) */ +extern uchar *net_tx_packet; /* THE transmit packet */ +extern uchar *net_rx_packets[PKTBUFSRX]; /* Receive packets */ +extern uchar *net_rx_packet; /* Current receive packet */ +extern int net_rx_packet_len; /* Current rx packet length */ +extern const u8 net_bcast_ethaddr[6]; /* Ethernet broadcast address */ +extern const u8 net_null_ethaddr[6]; #define VLAN_NONE 4095 /* untagged */ #define VLAN_IDMASK 0x0fff /* mask of valid vlan id */ -extern ushort NetOurVLAN; /* Our VLAN */ -extern ushort NetOurNativeVLAN; /* Our Native VLAN */ +extern ushort net_our_vlan; /* Our VLAN */ +extern ushort net_native_vlan; /* Our Native VLAN */ -extern int NetRestartWrap; /* Tried all network devices */ +extern int net_restart_wrap; /* Tried all network devices */ enum proto_t { BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL }; -/* from net/net.c */ -extern char BootFile[128]; /* Boot File name */ +extern char net_boot_file_name[128];/* Boot File name */ +/* The actual transferred size of the bootfile (in bytes) */ +extern u32 net_boot_file_size; +/* Boot file size in blocks as reported by the DHCP server */ +extern u32 net_boot_file_expected_size_in_blocks; #if defined(CONFIG_CMD_DNS) -extern char *NetDNSResolve; /* The host to resolve */ -extern char *NetDNSenvvar; /* the env var to put the ip into */ +extern char *net_dns_resolve; /* The host to resolve */ +extern char *net_dns_env_var; /* the env var to put the ip into */ #endif #if defined(CONFIG_CMD_PING) -extern IPaddr_t NetPingIP; /* the ip address to ping */ +extern struct in_addr net_ping_ip; /* the ip address to ping */ #endif #if defined(CONFIG_CMD_CDP) /* when CDP completes these hold the return values */ -extern ushort CDPNativeVLAN; /* CDP returned native VLAN */ -extern ushort CDPApplianceVLAN; /* CDP returned appliance VLAN */ +extern ushort cdp_native_vlan; /* CDP returned native VLAN */ +extern ushort cdp_appliance_vlan; /* CDP returned appliance VLAN */ /* * Check for a CDP packet by examining the received MAC address field */ -static inline int is_cdp_packet(const uchar *et_addr) +static inline int is_cdp_packet(const uchar *ethaddr) { - extern const uchar NetCDPAddr[6]; + extern const u8 net_cdp_ethaddr[6]; - return memcmp(et_addr, NetCDPAddr, 6) == 0; + return memcmp(ethaddr, net_cdp_ethaddr, 6) == 0; } #endif #if defined(CONFIG_CMD_SNTP) -extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */ -extern int NetTimeOffset; /* offset time from UTC */ +extern struct in_addr net_ntp_server; /* the ip address to NTP */ +extern int net_ntp_time_offset; /* offset time from UTC */ #endif #if defined(CONFIG_MCAST_TFTP) -extern IPaddr_t Mcast_addr; +extern struct in_addr net_mcast_addr; #endif /* Initialize the network adapter */ -extern void net_init(void); -extern int NetLoop(enum proto_t); - -/* Shutdown adapters and cleanup */ -extern void NetStop(void); +void net_init(void); +int net_loop(enum proto_t); /* Load failed. Start again. */ -extern void NetStartAgain(void); +int net_start_again(void); /* Get size of the ethernet header when we send */ -extern int NetEthHdrSize(void); +int net_eth_hdr_size(void); /* Set ethernet header; returns the size of the header */ -extern int NetSetEther(uchar *, uchar *, uint); -extern int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot); +int net_set_ether(uchar *xet, const uchar *dest_ethaddr, uint prot); +int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot); /* Set IP header */ -extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source); -extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, +void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source); +void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport, int sport, int len); /** @@ -515,12 +592,12 @@ unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum); int ip_checksum_ok(const void *addr, unsigned nbytes); /* Callbacks */ -extern rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */ -extern void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */ -extern rxhand_f *net_get_arp_handler(void); /* Get ARP RX packet handler */ -extern void net_set_arp_handler(rxhand_f *); /* Set ARP RX packet handler */ -extern void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */ -extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */ +rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */ +void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */ +rxhand_f *net_get_arp_handler(void); /* Get ARP RX packet handler */ +void net_set_arp_handler(rxhand_f *); /* Set ARP RX packet handler */ +void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */ +void net_set_timeout_handler(ulong, thand_f *);/* Set timeout handler */ /* Network loop state */ enum net_loop_state { @@ -538,13 +615,14 @@ static inline void net_set_state(enum net_loop_state state) } /* Transmit a packet */ -static inline void NetSendPacket(uchar *pkt, int len) +static inline void net_send_packet(uchar *pkt, int len) { + /* Currently no way to return errors from eth_send() */ (void) eth_send(pkt, len); } /* - * Transmit "NetTxPacket" as UDP packet, performing ARP request if needed + * Transmit "net_tx_packet" as UDP packet, performing ARP request if needed * (ether will be populated) * * @param ether Raw packet buffer @@ -553,15 +631,15 @@ static inline void NetSendPacket(uchar *pkt, int len) * @param sport Source UDP port * @param payload_len Length of data after the UDP header */ -extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, +int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, int payload_len); /* Processes a received packet */ -extern void NetReceive(uchar *, int); +void net_process_received_packet(uchar *in_packet, int len); #ifdef CONFIG_NETCONSOLE -void NcStart(void); -int nc_input_packet(uchar *pkt, IPaddr_t src_ip, unsigned dest_port, +void nc_start(void); +int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, unsigned src_port, unsigned len); #endif @@ -599,78 +677,78 @@ void net_auto_load(void); * footprint in our tests. */ /* return IP *in network byteorder* */ -static inline IPaddr_t NetReadIP(void *from) +static inline struct in_addr net_read_ip(void *from) { - IPaddr_t ip; + struct in_addr ip; memcpy((void *)&ip, (void *)from, sizeof(ip)); return ip; } /* return ulong *in network byteorder* */ -static inline ulong NetReadLong(ulong *from) +static inline u32 net_read_u32(u32 *from) { - ulong l; + u32 l; memcpy((void *)&l, (void *)from, sizeof(l)); return l; } /* write IP *in network byteorder* */ -static inline void NetWriteIP(void *to, IPaddr_t ip) +static inline void net_write_ip(void *to, struct in_addr ip) { memcpy(to, (void *)&ip, sizeof(ip)); } /* copy IP */ -static inline void NetCopyIP(void *to, void *from) +static inline void net_copy_ip(void *to, void *from) { - memcpy((void *)to, from, sizeof(IPaddr_t)); + memcpy((void *)to, from, sizeof(struct in_addr)); } /* copy ulong */ -static inline void NetCopyLong(ulong *to, ulong *from) +static inline void net_copy_u32(u32 *to, u32 *from) { - memcpy((void *)to, (void *)from, sizeof(ulong)); + memcpy((void *)to, (void *)from, sizeof(u32)); } /** - * is_zero_ether_addr - Determine if give Ethernet address is all zeros. + * is_zero_ethaddr - Determine if give Ethernet address is all zeros. * @addr: Pointer to a six-byte array containing the Ethernet address * * Return true if the address is all zeroes. */ -static inline int is_zero_ether_addr(const u8 *addr) +static inline int is_zero_ethaddr(const u8 *addr) { return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]); } /** - * is_multicast_ether_addr - Determine if the Ethernet address is a multicast. + * is_multicast_ethaddr - Determine if the Ethernet address is a multicast. * @addr: Pointer to a six-byte array containing the Ethernet address * * Return true if the address is a multicast address. * By definition the broadcast address is also a multicast address. */ -static inline int is_multicast_ether_addr(const u8 *addr) +static inline int is_multicast_ethaddr(const u8 *addr) { return 0x01 & addr[0]; } /* - * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast + * is_broadcast_ethaddr - Determine if the Ethernet address is broadcast * @addr: Pointer to a six-byte array containing the Ethernet address * * Return true if the address is the broadcast address. */ -static inline int is_broadcast_ether_addr(const u8 *addr) +static inline int is_broadcast_ethaddr(const u8 *addr) { return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff; } /* - * is_valid_ether_addr - Determine if the given Ethernet address is valid + * is_valid_ethaddr - Determine if the given Ethernet address is valid * @addr: Pointer to a six-byte array containing the Ethernet address * * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not @@ -678,21 +756,21 @@ static inline int is_broadcast_ether_addr(const u8 *addr) * * Return true if the address is valid. */ -static inline int is_valid_ether_addr(const u8 *addr) +static inline int is_valid_ethaddr(const u8 *addr) { /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to * explicitly check for it here. */ - return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); + return !is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr); } /** - * eth_random_addr - Generate software assigned random Ethernet address + * net_random_ethaddr - Generate software assigned random Ethernet address * @addr: Pointer to a six-byte array containing the Ethernet address * * Generate a random Ethernet address (MAC) that is not multicast * and has the local assigned bit set. */ -static inline void eth_random_addr(uchar *addr) +static inline void net_random_ethaddr(uchar *addr) { int i; unsigned int seed = get_timer(0); @@ -705,28 +783,28 @@ static inline void eth_random_addr(uchar *addr) } /* Convert an IP address to a string */ -extern void ip_to_string(IPaddr_t x, char *s); +void ip_to_string(struct in_addr x, char *s); /* Convert a string to ip address */ -extern IPaddr_t string_to_ip(const char *s); +struct in_addr string_to_ip(const char *s); /* Convert a VLAN id to a string */ -extern void VLAN_to_string(ushort x, char *s); +void vlan_to_string(ushort x, char *s); /* Convert a string to a vlan id */ -extern ushort string_to_VLAN(const char *s); +ushort string_to_vlan(const char *s); /* read a VLAN id from an environment variable */ -extern ushort getenv_VLAN(char *); +ushort getenv_vlan(char *); /* copy a filename (allow for "..." notation, limit length) */ -extern void copy_filename(char *dst, const char *src, int size); +void copy_filename(char *dst, const char *src, int size); /* get a random source port */ -extern unsigned int random_port(void); +unsigned int random_port(void); /* Update U-Boot over TFTP */ -extern int update_tftp(ulong addr); +int update_tftp(ulong addr); /**********************************************************************/ diff --git a/include/os.h b/include/os.h index e3645e0116..a758f099aa 100644 --- a/include/os.h +++ b/include/os.h @@ -64,7 +64,7 @@ off_t os_lseek(int fd, off_t offset, int whence); * Access to the OS open() system call * * \param pathname Pathname of file to open - * \param flags Flags, like O_RDONLY, O_RDWR + * \param flags Flags, like OS_O_RDONLY, OS_O_RDWR * \return file descriptor, or -1 on error */ int os_open(const char *pathname, int flags); diff --git a/include/pci.h b/include/pci.h index 004a048d2f..07b1e9a4f5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -457,12 +457,15 @@ static inline void pci_set_region(struct pci_region *reg, typedef int pci_dev_t; -#define PCI_BUS(d) (((d) >> 16) & 0xff) -#define PCI_DEV(d) (((d) >> 11) & 0x1f) -#define PCI_FUNC(d) (((d) >> 8) & 0x7) -#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) - -#define PCI_ANY_ID (~0) +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) +#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) +#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) +#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) +#define PCI_VENDEV(v, d) (((v) << 16) | (d)) +#define PCI_ANY_ID (~0) struct pci_device_id { unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ @@ -495,7 +498,12 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev * Structure of a PCI controller (host bridge) */ struct pci_controller { +#ifdef CONFIG_DM_PCI + struct udevice *bus; + struct udevice *ctlr; +#else struct pci_controller *next; +#endif int first_busno; int last_busno; @@ -511,7 +519,7 @@ struct pci_controller { struct pci_config_table *config_table; void (*fixup_irq)(struct pci_controller *, pci_dev_t); - +#ifndef CONFIG_DM_PCI /* Low-level architecture-dependent routines */ int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); @@ -519,17 +527,21 @@ struct pci_controller { int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); +#endif /* Used by auto config */ struct pci_region *pci_mem, *pci_io, *pci_prefetch; /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; +#ifndef CONFIG_DM_PCI int current_busno; void *priv_data; +#endif }; +#ifndef CONFIG_DM_PCI static inline void pci_set_ops(struct pci_controller *hose, int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *), @@ -550,6 +562,7 @@ static inline void pci_set_ops(struct pci_controller *hose, hose->write_word = write_word; hose->write_dword = write_dword; } +#endif #ifdef CONFIG_PCI_INDIRECT_BRIDGE extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); @@ -602,12 +615,14 @@ extern int pci_hose_write_config_word(struct pci_controller *hose, extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); +#ifndef CONFIG_DM_PCI extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); +#endif extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); @@ -705,5 +720,387 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); */ int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev); +/** + * pci_hose_find_devices() - Find devices by vendor/device ID + * + * @hose: PCI hose to search + * @busnum: Bus number to search + * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record + * @indexp: Pointer to device index to find. To find the first matching + * device, pass 0; to find the second, pass 1, etc. This + * parameter is decremented for each non-matching device so + * can be called repeatedly. + */ +pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, + struct pci_device_id *ids, int *indexp); + +/* Access sizes for PCI reads and writes */ +enum pci_size_t { + PCI_SIZE_8, + PCI_SIZE_16, + PCI_SIZE_32, +}; + +struct udevice; + +#ifdef CONFIG_DM_PCI +/** + * struct pci_child_platdata - information stored about each PCI device + * + * Every device on a PCI bus has this per-child data. + * + * It can be accessed using dev_get_parentdata(dev) if dev->parent is a + * PCI bus (i.e. UCLASS_PCI) + * + * @devfn: Encoded device and function index - see PCI_DEVFN() + * @vendor: PCI vendor ID (see pci_ids.h) + * @device: PCI device ID (see pci_ids.h) + * @class: PCI class, 3 bytes: (base, sub, prog-if) + */ +struct pci_child_platdata { + int devfn; + unsigned short vendor; + unsigned short device; + unsigned int class; +}; + +/* PCI bus operations */ +struct dm_pci_ops { + /** + * read_config() - Read a PCI configuration value + * + * PCI buses must support reading and writing configuration values + * so that the bus can be scanned and its devices configured. + * + * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. + * If bridges exist it is possible to use the top-level bus to + * access a sub-bus. In that case @bus will be the top-level bus + * and PCI_BUS(bdf) will be a different (higher) value + * + * @bus: Bus to read from + * @bdf: Bus, device and function to read + * @offset: Byte offset within the device's configuration space + * @valuep: Place to put the returned value + * @size: Access size + * @return 0 if OK, -ve on error + */ + int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong *valuep, enum pci_size_t size); + /** + * write_config() - Write a PCI configuration value + * + * @bus: Bus to write to + * @bdf: Bus, device and function to write + * @offset: Byte offset within the device's configuration space + * @value: Value to write + * @size: Access size + * @return 0 if OK, -ve on error + */ + int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong value, enum pci_size_t size); +}; + +/* Get access to a PCI bus' operations */ +#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) + +/** + * pci_bind_bus_devices() - scan a PCI bus and bind devices + * + * Scan a PCI bus looking for devices. Bind each one that is found. If + * devices are already bound that match the scanned devices, just update the + * child data so that the device can be used correctly (this happens when + * the device tree describes devices we expect to see on the bus). + * + * Devices that are bound in this way will use a generic PCI driver which + * does nothing. The device can still be accessed but will not provide any + * driver interface. + * + * @bus: Bus containing devices to bind + * @return 0 if OK, -ve on error + */ +int pci_bind_bus_devices(struct udevice *bus); + +/** + * pci_auto_config_devices() - configure bus devices ready for use + * + * This works through all devices on a bus by scanning the driver model + * data structures (normally these have been set up by pci_bind_bus_devices() + * earlier). + * + * Space is allocated for each PCI base address register (BAR) so that the + * devices are mapped into memory and I/O space ready for use. + * + * @bus: Bus containing devices to bind + * @return 0 if OK, -ve on error + */ +int pci_auto_config_devices(struct udevice *bus); + +/** + * pci_bus_find_bdf() - Find a device given its PCI bus address + * + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @devp: Returns the device for this address, if found + * @return 0 if OK, -ENODEV if not found + */ +int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); + +/** + * pci_bus_find_devfn() - Find a device on a bus + * + * @find_devfn: PCI device address (device and function only) + * @devp: Returns the device for this address, if found + * @return 0 if OK, -ENODEV if not found + */ +int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, + struct udevice **devp); + +/** + * pci_get_ff() - Returns a mask for the given access size + * + * @size: Access size + * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for + * PCI_SIZE_32 + */ +int pci_get_ff(enum pci_size_t size); + +/** + * pci_bus_find_devices () - Find devices on a bus + * + * @bus: Bus to search + * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record + * @indexp: Pointer to device index to find. To find the first matching + * device, pass 0; to find the second, pass 1, etc. This + * parameter is decremented for each non-matching device so + * can be called repeatedly. + * @devp: Returns matching device if found + * @return 0 if found, -ENODEV if not + */ +int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, + int *indexp, struct udevice **devp); + +/** + * pci_find_device_id() - Find a device on any bus + * + * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record + * @index: Index number of device to find, 0 for the first match, 1 for + * the second, etc. + * @devp: Returns matching device if found + * @return 0 if found, -ENODEV if not + */ +int pci_find_device_id(struct pci_device_id *ids, int index, + struct udevice **devp); + +/** + * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices + * + * This probes the given bus which causes it to be scanned for devices. The + * devices will be bound but not probed. + * + * @hose specifies the PCI hose that will be used for the scan. This is + * always a top-level bus with uclass UCLASS_PCI. The bus to scan is + * in @bdf, and is a subordinate bus reachable from @hose. + * + * @hose: PCI hose to scan + * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) + * @return 0 if OK, -ve on error + */ +int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf); + +/** + * pci_bus_read_config() - Read a configuration value from a device + * + * TODO(sjg@chromium.org): We should be able to pass just a device and have + * it do the right thing. It would be good to have that function also. + * + * @bus: Bus to read from + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @valuep: Place to put the returned value + * @size: Access size + * @return 0 if OK, -ve on error + */ +int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, + unsigned long *valuep, enum pci_size_t size); + +/** + * pci_bus_write_config() - Write a configuration value to a device + * + * @bus: Bus to write from + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @value: Value to write + * @size: Access size + * @return 0 if OK, -ve on error + */ +int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, + unsigned long value, enum pci_size_t size); + +/* + * The following functions provide access to the above without needing the + * size parameter. We are trying to encourage the use of the 8/16/32-style + * functions, rather than byte/word/dword. But both are supported. + */ +int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); + +/* Compatibility with old naming */ +static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, + u32 value) +{ + return pci_write_config32(pcidev, offset, value); +} + +int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); + +/* Compatibility with old naming */ +static inline int pci_write_config_word(pci_dev_t pcidev, int offset, + u16 value) +{ + return pci_write_config16(pcidev, offset, value); +} + +int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); + +/* Compatibility with old naming */ +static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, + u8 value) +{ + return pci_write_config8(pcidev, offset, value); +} + +int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); + +/* Compatibility with old naming */ +static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, + u32 *valuep) +{ + return pci_read_config32(pcidev, offset, valuep); +} + +int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); + +/* Compatibility with old naming */ +static inline int pci_read_config_word(pci_dev_t pcidev, int offset, + u16 *valuep) +{ + return pci_read_config16(pcidev, offset, valuep); +} + +int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); + +/* Compatibility with old naming */ +static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, + u8 *valuep) +{ + return pci_read_config8(pcidev, offset, valuep); +} + +/** + * struct dm_pci_emul_ops - PCI device emulator operations + */ +struct dm_pci_emul_ops { + /** + * get_devfn(): Check which device and function this emulators + * + * @dev: device to check + * @return the device and function this emulates, or -ve on error + */ + int (*get_devfn)(struct udevice *dev); + /** + * read_config() - Read a PCI configuration value + * + * @dev: Emulated device to read from + * @offset: Byte offset within the device's configuration space + * @valuep: Place to put the returned value + * @size: Access size + * @return 0 if OK, -ve on error + */ + int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, + enum pci_size_t size); + /** + * write_config() - Write a PCI configuration value + * + * @dev: Emulated device to write to + * @offset: Byte offset within the device's configuration space + * @value: Value to write + * @size: Access size + * @return 0 if OK, -ve on error + */ + int (*write_config)(struct udevice *dev, uint offset, ulong value, + enum pci_size_t size); + /** + * read_io() - Read a PCI I/O value + * + * @dev: Emulated device to read from + * @addr: I/O address to read + * @valuep: Place to put the returned value + * @size: Access size + * @return 0 if OK, -ENOENT if @addr is not mapped by this device, + * other -ve value on error + */ + int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, + enum pci_size_t size); + /** + * write_io() - Write a PCI I/O value + * + * @dev: Emulated device to write from + * @addr: I/O address to write + * @value: Value to write + * @size: Access size + * @return 0 if OK, -ENOENT if @addr is not mapped by this device, + * other -ve value on error + */ + int (*write_io)(struct udevice *dev, unsigned int addr, + ulong value, enum pci_size_t size); + /** + * map_physmem() - Map a device into sandbox memory + * + * @dev: Emulated device to map + * @addr: Memory address, normally corresponding to a PCI BAR. + * The device should have been configured to have a BAR + * at this address. + * @lenp: On entry, the size of the area to map, On exit it is + * updated to the size actually mapped, which may be less + * if the device has less space + * @ptrp: Returns a pointer to the mapped address. The device's + * space can be accessed as @lenp bytes starting here + * @return 0 if OK, -ENOENT if @addr is not mapped by this device, + * other -ve value on error + */ + int (*map_physmem)(struct udevice *dev, phys_addr_t addr, + unsigned long *lenp, void **ptrp); + /** + * unmap_physmem() - undo a memory mapping + * + * This must be called after map_physmem() to undo the mapping. + * Some devices can use this to check what has been written into + * their mapped memory and perform an operations they require on it. + * In this way, map/unmap can be used as a sort of handshake between + * the emulated device and its users. + * + * @dev: Emuated device to unmap + * @vaddr: Mapped memory address, as passed to map_physmem() + * @len: Size of area mapped, as returned by map_physmem() + * @return 0 if OK, -ve on error + */ + int (*unmap_physmem)(struct udevice *dev, const void *vaddr, + unsigned long len); +}; + +/* Get access to a PCI device emulator's operations */ +#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) + +/** + * sandbox_pci_get_emul() - Get the emulation device for a PCI device + * + * Searches for a suitable emulator for the given PCI bus device + * + * @bus: PCI bus to search + * @find_devfn: PCI device and function address (PCI_DEVFN()) + * @emulp: Returns emulated device if found + * @return 0 if found, -ENODEV if not found + */ +int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, + struct udevice **emulp); + +#endif + #endif /* __ASSEMBLY__ */ #endif /* _PCI_H */ diff --git a/include/pci_ids.h b/include/pci_ids.h index dc2ca218a6..2e6685112b 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -3016,6 +3016,8 @@ #define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 #define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 #define PCI_VENDOR_ID_SCALEMP 0x8686 diff --git a/include/phy.h b/include/phy.h index d117fc1634..3f826b66f7 100644 --- a/include/phy.h +++ b/include/phy.h @@ -51,7 +51,9 @@ typedef enum { PHY_INTERFACE_MODE_RGMII_TXID, PHY_INTERFACE_MODE_RTBI, PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_NONE /* Must be last */ + PHY_INTERFACE_MODE_NONE, /* Must be last */ + + PHY_INTERFACE_MODE_COUNT, } phy_interface_t; static const char *phy_interface_strings[] = { @@ -142,7 +144,11 @@ struct phy_device { struct phy_driver *drv; void *priv; +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else struct eth_device *dev; +#endif /* forced speed & duplex (no autoneg) * partner speed & duplex & pause (autoneg) @@ -205,10 +211,17 @@ int phy_init(void); int phy_reset(struct phy_device *phydev); struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, phy_interface_t interface); +#ifdef CONFIG_DM_ETH +void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct udevice *dev, + phy_interface_t interface); +#else void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, phy_interface_t interface); +#endif int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); @@ -241,6 +254,15 @@ int phy_teranetics_init(void); int phy_vitesse_init(void); int board_phy_config(struct phy_device *phydev); +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); + +/** + * phy_get_interface_by_name() - Look up a PHY interface name + * + * @str: PHY interface name, e.g. "mii" + * @return PHY_INTERFACE_MODE_... value, or -1 if not found + */ +int phy_get_interface_by_name(const char *str); /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 07199b4f89..8e7a22d020 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -180,7 +180,7 @@ enum { #define LDOB_3_30V 15 #define LDO_VOL_MASK 0xf -#define LDO_EN 4 +#define LDO_EN (1 << 4) /* * Boost Regulator diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 36d5975584..ba166ebdd4 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -12,6 +12,8 @@ #ifndef __PPC_ASM_TMPL__ #define __PPC_ASM_TMPL__ +#include <config.h> + /*************************************************************************** * * These definitions simplify the ugly declarations necessary for GOT @@ -243,6 +245,45 @@ */ #define COPY_EE(d, s) rlwimi d,s,0,16,16 #define NOCOPY(d, s) + +#ifdef CONFIG_E500 +#define EXC_XFER_TEMPLATE(n, label, hdlr, msr, copyee) \ + stw r22,_NIP(r21); \ + stw r23,_MSR(r21); \ + li r23,n; \ + stw r23,TRAP(r21); \ + li r20,msr; \ + copyee(r20,r23); \ + rlwimi r20,r23,0,25,25; \ + mtmsr r20; \ + bl 1f; \ +1: mflr r23; \ + addis r23,r23,(hdlr - 1b)@ha; \ + addi r23,r23,(hdlr - 1b)@l; \ + b transfer_to_handler + +#define STD_EXCEPTION(n, label, hdlr) \ +label: \ + EXCEPTION_PROLOG(SRR0, SRR1); \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY) \ + +#define CRIT_EXCEPTION(n, label, hdlr) \ +label: \ + EXCEPTION_PROLOG(CSRR0, CSRR1); \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(n, label, hdlr, \ + MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ + +#define MCK_EXCEPTION(n, label, hdlr) \ +label: \ + EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(n, label, hdlr, \ + MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ + +#else /* !E500 */ + #define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \ bl 1f; \ 1: mflr r20; \ @@ -280,4 +321,5 @@ label: \ EXC_XFER_TEMPLATE(label, hdlr, \ MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ +#endif /* !E500 */ #endif /* __PPC_ASM_TMPL__ */ diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h index 723f6ab766..1ea3717bf7 100644 --- a/include/pxa_lcd.h +++ b/include/pxa_lcd.h @@ -48,6 +48,7 @@ struct pxafb_info { typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ ushort vl_width; /* Width of display area in millimeters */ ushort vl_height; /* Height of display area in millimeters */ diff --git a/include/spi.h b/include/spi.h index c58e453559..9495ca53c9 100644 --- a/include/spi.h +++ b/include/spi.h @@ -38,11 +38,12 @@ /* SPI RX operation modes */ #define SPI_OPM_RX_AS (1 << 0) -#define SPI_OPM_RX_DOUT (1 << 1) -#define SPI_OPM_RX_DIO (1 << 2) -#define SPI_OPM_RX_QOF (1 << 3) -#define SPI_OPM_RX_QIOF (1 << 4) -#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ +#define SPI_OPM_RX_AF (1 << 1) +#define SPI_OPM_RX_DOUT (1 << 2) +#define SPI_OPM_RX_DIO (1 << 3) +#define SPI_OPM_RX_QOF (1 << 4) +#define SPI_OPM_RX_QIOF (1 << 5) +#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ SPI_OPM_RX_QIOF) @@ -385,12 +386,12 @@ struct dm_spi_ops { * allowed to claim the same bus for several slaves without releasing * the bus in between. * - * @bus: The SPI slave + * @dev: The SPI slave * * Returns: 0 if the bus was claimed successfully, or a negative value * if it wasn't. */ - int (*claim_bus)(struct udevice *bus); + int (*claim_bus)(struct udevice *dev); /** * Release the SPI bus @@ -399,9 +400,9 @@ struct dm_spi_ops { * all transfers have finished. It may disable any SPI hardware as * appropriate. * - * @bus: The SPI slave + * @dev: The SPI slave */ - int (*release_bus)(struct udevice *bus); + int (*release_bus)(struct udevice *dev); /** * Set the word length for SPI transactions @@ -413,7 +414,7 @@ struct dm_spi_ops { * * Returns: 0 on success, -ve on failure. */ - int (*set_wordlen)(struct udevice *bus, unsigned int wordlen); + int (*set_wordlen)(struct udevice *dev, unsigned int wordlen); /** * SPI transfer diff --git a/include/spi_flash.h b/include/spi_flash.h index 5913b39e26..f2814ef41a 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -62,11 +62,10 @@ struct spi_slave; * return 0 - Success, 1 - Failure */ struct spi_flash { -#ifdef CONFIG_DM_SPI_FLASH struct spi_slave *spi; +#ifdef CONFIG_DM_SPI_FLASH struct udevice *dev; -#else - struct spi_slave *spi; + u16 flags; #endif const char *name; u8 dual_flash; @@ -91,13 +90,13 @@ struct spi_flash { #ifndef CONFIG_DM_SPI_FLASH /* * These are not strictly needed for driver model, but keep them here - * whilt the transition is in progress. + * while the transition is in progress. * * Normally each driver would provide its own operations, but for * SPI flash most chips use the same algorithms. One approach is * to create a 'common' SPI flash device which knows how to talk * to most devices, and then allow other drivers to be used instead - * if requird, perhaps with a way of scanning through the list to + * if required, perhaps with a way of scanning through the list to * find the driver that matches the device. */ int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); @@ -118,6 +117,41 @@ struct dm_spi_flash_ops { #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) #ifdef CONFIG_DM_SPI_FLASH +/** + * spi_flash_read_dm() - Read data from SPI flash + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to read from + * @len: Number of bytes to read + * @buf: Buffer to put the data that is read + * @return 0 if OK, -ve on error + */ +int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf); + +/** + * spi_flash_write_dm() - Write data to SPI flash + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to write to + * @len: Number of bytes to write + * @buf: Buffer containing bytes to write + * @return 0 if OK, -ve on error + */ +int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len, + const void *buf); + +/** + * spi_flash_erase_dm() - Erase blocks of the SPI flash + * + * Note that @len must be a muiltiple of the flash sector size. + * + * @dev: SPI flash device + * @offset: Offset into device in bytes to start erasing + * @len: Number of bytes to erase + * @return 0 if OK, -ve on error + */ +int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len); + int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode, struct udevice **devp); @@ -132,21 +166,21 @@ void spi_flash_free(struct spi_flash *flash); int spi_flash_remove(struct udevice *flash); static inline int spi_flash_read(struct spi_flash *flash, u32 offset, - size_t len, void *buf) + size_t len, void *buf) { - return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf); + return spi_flash_read_dm(flash->dev, offset, len, buf); } static inline int spi_flash_write(struct spi_flash *flash, u32 offset, - size_t len, const void *buf) + size_t len, const void *buf) { - return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf); + return spi_flash_write_dm(flash->dev, offset, len, buf); } static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, - size_t len) + size_t len) { - return sf_get_ops(flash->dev)->erase(flash->dev, offset, len); + return spi_flash_erase_dm(flash->dev, offset, len); } struct sandbox_state; diff --git a/include/status_led.h b/include/status_led.h index 27f4bdfa87..a5e35df80a 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -105,6 +105,7 @@ typedef unsigned long led_id_t; extern void __led_toggle (led_id_t mask); extern void __led_init (led_id_t mask, int state); extern void __led_set (led_id_t mask, int state); +void __led_blink(led_id_t mask, int freq); #else # error Status LED configuration missing #endif diff --git a/include/usb.h b/include/usb.h index 2c3d506345..1984e8f590 100644 --- a/include/usb.h +++ b/include/usb.h @@ -2,6 +2,9 @@ * (C) Copyright 2001 * Denis Peter, MPL AG Switzerland * + * Adapted for U-Boot driver model + * (C) Copyright 2015 Google, Inc + * * SPDX-License-Identifier: GPL-2.0+ * Note: Part of this code has been derived from linux * @@ -9,6 +12,7 @@ #ifndef _USB_H_ #define _USB_H_ +#include <fdtdec.h> #include <usb_defs.h> #include <linux/usb/ch9.h> #include <asm/cache.h> @@ -85,6 +89,19 @@ enum { PACKET_SIZE_64 = 3, }; +/** + * struct usb_device - information about a USB device + * + * With driver model both UCLASS_USB (the USB controllers) and UCLASS_USB_HUB + * (the hubs) have this as parent data. Hubs are children of controllers or + * other hubs and there is always a single root hub for each controller. + * Therefore struct usb_device can always be accessed with + * dev_get_parentdata(dev), where dev is a USB device. + * + * Pointers exist for obtaining both the device (could be any uclass) and + * controller (UCLASS_USB) from this structure. The controller does not have + * a struct usb_device since it is not a device. + */ struct usb_device { int devnum; /* Device number on USB bus */ int speed; /* full/low/high */ @@ -123,13 +140,19 @@ struct usb_device { unsigned long int_pending; /* 1 bit per ep, used by int_queue */ int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ - int portnr; + int portnr; /* Port number, 1=first */ +#ifndef CONFIG_DM_USB + /* parent hub, or NULL if this is the root hub */ struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; - void *controller; /* hardware controller private data */ +#endif /* slot_id - for xHCI enabled devices */ unsigned int slot_id; +#ifdef CONFIG_DM_USB + struct udevice *dev; /* Pointer to associated device */ + struct udevice *controller_dev; /* Pointer to associated controller */ +#endif }; struct int_queue; @@ -156,12 +179,14 @@ enum usb_init_type { defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \ defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \ defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \ - defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2) + defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2) || \ + defined(CONFIG_USB_EMUL) int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); int usb_lowlevel_stop(int index); -#ifdef CONFIG_MUSB_HOST -void usb_reset_root_port(void); + +#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_DM_USB) +int usb_reset_root_port(void); #else #define usb_reset_root_port() #endif @@ -245,7 +270,6 @@ int usb_stop(void); /* stop the USB Controller */ int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol); int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id); -struct usb_device *usb_get_dev_index(int index); int usb_control_msg(struct usb_device *dev, unsigned int pipe, unsigned char request, unsigned char requesttype, unsigned short value, unsigned short index, @@ -389,6 +413,113 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); ((usb_pipeendpoint(pipe) * 2) - \ (usb_pipein(pipe) ? 0 : 1)) +/** + * struct usb_device_id - identifies USB devices for probing and hotplugging + * @match_flags: Bit mask controlling which of the other fields are used to + * match against new devices. Any field except for driver_info may be + * used, although some only make sense in conjunction with other fields. + * This is usually set by a USB_DEVICE_*() macro, which sets all + * other fields in this structure except for driver_info. + * @idVendor: USB vendor ID for a device; numbers are assigned + * by the USB forum to its members. + * @idProduct: Vendor-assigned product ID. + * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers. + * This is also used to identify individual product versions, for + * a range consisting of a single device. + * @bcdDevice_hi: High end of version number range. The range of product + * versions is inclusive. + * @bDeviceClass: Class of device; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Device classes specify behavior of all + * the interfaces on a device. + * @bDeviceSubClass: Subclass of device; associated with bDeviceClass. + * @bDeviceProtocol: Protocol of device; associated with bDeviceClass. + * @bInterfaceClass: Class of interface; numbers are assigned + * by the USB forum. Products may choose to implement classes, + * or be vendor-specific. Interface classes specify behavior only + * of a given interface; other interfaces may support other classes. + * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass. + * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass. + * @bInterfaceNumber: Number of interface; composite devices may use + * fixed interface numbers to differentiate between vendor-specific + * interfaces. + * @driver_info: Holds information used by the driver. Usually it holds + * a pointer to a descriptor understood by the driver, or perhaps + * device flags. + * + * In most cases, drivers will create a table of device IDs by using + * USB_DEVICE(), or similar macros designed for that purpose. + * They will then export it to userspace using MODULE_DEVICE_TABLE(), + * and provide it to the USB core through their usb_driver structure. + * + * See the usb_match_id() function for information about how matches are + * performed. Briefly, you will normally use one of several macros to help + * construct these entries. Each entry you provide will either identify + * one or more specific products, or will identify a class of products + * which have agreed to behave the same. You should put the more specific + * matches towards the beginning of your table, so that driver_info can + * record quirks of specific products. + */ +struct usb_device_id { + /* which fields to match against? */ + u16 match_flags; + + /* Used for product specific matches; range is inclusive */ + u16 idVendor; + u16 idProduct; + u16 bcdDevice_lo; + u16 bcdDevice_hi; + + /* Used for device class matches */ + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + + /* Used for interface class matches */ + u8 bInterfaceClass; + u8 bInterfaceSubClass; + u8 bInterfaceProtocol; + + /* Used for vendor-specific interface matches */ + u8 bInterfaceNumber; + + /* not matched against */ + ulong driver_info; +}; + +/* Some useful macros to use to create struct usb_device_id */ +#define USB_DEVICE_ID_MATCH_VENDOR 0x0001 +#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 +#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004 +#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 +#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010 +#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020 +#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040 +#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 +#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 +#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 +#define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400 + +/* Match anything, indicates this is a valid entry even if everything is 0 */ +#define USB_DEVICE_ID_MATCH_NONE 0x0800 +#define USB_DEVICE_ID_MATCH_ALL 0x07ff + +/** + * struct usb_driver_entry - Matches a driver to its usb_device_ids + * @compatible: Compatible string + * @data: Data for this compatible string + */ +struct usb_driver_entry { + struct driver *driver; + const struct usb_device_id *match; +}; + +#define USB_DEVICE(__name, __match) \ + ll_entry_declare(struct usb_driver_entry, __name, usb_driver_entry) = {\ + .driver = llsym(struct driver, __name, driver), \ + .match = __match, \ + } + /************************************************************************* * Hub Stuff */ @@ -423,15 +554,360 @@ struct usb_hub_device { struct usb_hub_descriptor desc; }; +#ifdef CONFIG_DM_USB +/** + * struct usb_platdata - Platform data about a USB controller + * + * Given a USB controller (UCLASS_USB) dev this is dev_get_platdata(dev) + */ +struct usb_platdata { + enum usb_init_type init_type; +}; + +/** + * struct usb_dev_platdata - Platform data about a USB device + * + * Given a USB device dev this structure is dev_get_parent_platdata(dev). + * This is used by sandbox to provide emulation data also. + * + * @id: ID used to match this device + * @speed: Stores the speed associated with a USB device + * @devnum: Device address on the USB bus + * @slot_id: USB3 slot ID, which is separate from the device address + * @portnr: Port number of this device on its parent hub, numbered from 1 + * (0 mean this device is the root hub) + * @strings: List of descriptor strings (for sandbox emulation purposes) + * @desc_list: List of descriptors (for sandbox emulation purposes) + */ +struct usb_dev_platdata { + struct usb_device_id id; + enum usb_device_speed speed; + int devnum; + int slot_id; + int portnr; /* Hub port number, 1..n */ +#ifdef CONFIG_SANDBOX + struct usb_string *strings; + /* NULL-terminated list of descriptor pointers */ + struct usb_generic_descriptor **desc_list; +#endif + int configno; +}; + +/** + * struct usb_bus_priv - information about the USB controller + * + * Given a USB controller (UCLASS_USB) 'dev', this is + * dev_get_uclass_priv(dev). + * + * @next_addr: Next device address to allocate minus 1. Incremented by 1 + * each time a new device address is set, so this holds the + * number of devices on the bus + * @desc_before_addr: true if we can read a device descriptor before it + * has been assigned an address. For XHCI this is not possible + * so this will be false. + */ +struct usb_bus_priv { + int next_addr; + bool desc_before_addr; +}; + +/** + * struct dm_usb_ops - USB controller operations + * + * This defines the operations supoorted on a USB controller. Common + * arguments are: + * + * @bus: USB bus (i.e. controller), which is in UCLASS_USB. + * @udev: USB device parent data. Controllers are not expected to need + * this, since the device address on the bus is encoded in @pipe. + * It is used for sandbox, and can be handy for debugging and + * logging. + * @pipe: An assortment of bitfields which provide address and packet + * type information. See create_pipe() above for encoding + * details + * @buffer: A buffer to use for sending/receiving. This should be + * DMA-aligned. + * @length: Buffer length in bytes + */ +struct dm_usb_ops { + /** + * control() - Send a control message + * + * Most parameters are as above. + * + * @setup: Additional setup information required by the message + */ + int (*control)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + struct devrequest *setup); + /** + * bulk() - Send a bulk message + * + * Parameters are as above. + */ + int (*bulk)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length); + /** + * interrupt() - Send an interrupt message + * + * Most parameters are as above. + * + * @interval: Interrupt interval + */ + int (*interrupt)(struct udevice *bus, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + int interval); + /** + * alloc_device() - Allocate a new device context (XHCI) + * + * Before sending packets to a new device on an XHCI bus, a device + * context must be created. If this method is not NULL it will be + * called before the device is enumerated (even before its descriptor + * is read). This should be NULL for EHCI, which does not need this. + */ + int (*alloc_device)(struct udevice *bus, struct usb_device *udev); +}; + +#define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) +#define usb_get_emul_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) + +#ifdef CONFIG_MUSB_HOST +int usb_reset_root_port(void); +#endif + +/** + * usb_get_dev_index() - look up a device index number + * + * Look up devices using their index number (starting at 0). This works since + * in U-Boot device addresses are allocated starting at 1 with no gaps. + * + * TODO(sjg@chromium.org): Remove this function when usb_ether.c is modified + * to work better with driver model. + * + * @bus: USB bus to check + * @index: Index number of device to find (0=first). This is just the + * device address less 1. + */ +struct usb_device *usb_get_dev_index(struct udevice *bus, int index); + +/** + * usb_legacy_port_reset() - Legacy function to reset a hub port + * + * @hub: Hub device + * @portnr: Port number (1=first) + */ +int usb_legacy_port_reset(struct usb_device *hub, int portnr); + +/** + * usb_setup_device() - set up a device ready for use + * + * @dev: USB device pointer. This need not be a real device - it is + * common for it to just be a local variable with its ->dev + * member (i.e. @dev->dev) set to the parent device + * @do_read: true to read the device descriptor before an address is set + * (should be false for XHCI buses, true otherwise) + * @parent: Parent device (either UCLASS_USB or UCLASS_USB_HUB) + * @portnr: Port number on hub (1=first) or 0 for none + * @return 0 if OK, -ve on error */ +int usb_setup_device(struct usb_device *dev, bool do_read, + struct usb_device *parent, int portnr); + +/** + * usb_hub_scan() - Scan a hub and find its devices + * + * @hub: Hub device to scan + */ +int usb_hub_scan(struct udevice *hub); + +/** + * usb_scan_device() - Scan a device on a bus + * + * Scan a device on a bus. It has already been detected and is ready to + * be enumerated. This may be either the root hub (@parent is a bus) or a + * normal device (@parent is a hub) + * + * @parent: Parent device + * @port: Hub port number (numbered from 1) + * @speed: USB speed to use for this device + * @devp: Returns pointer to device if all is well + * @return 0 if OK, -ve on error + */ +int usb_scan_device(struct udevice *parent, int port, + enum usb_device_speed speed, struct udevice **devp); + +/** + * usb_get_bus() - Find the bus for a device + * + * Search up through parents to find the bus this device is connected to. This + * will be a device with uclass UCLASS_USB. + * + * @dev: Device to check + * @busp: Returns bus, or NULL if not found + * @return 0 if OK, -EXDEV is somehow this bus does not have a controller (this + * indicates a critical error in the USB stack + */ +int usb_get_bus(struct udevice *dev, struct udevice **busp); + +/** + * usb_select_config() - Set up a device ready for use + * + * This function assumes that the device already has an address and a driver + * bound, and is ready to be set up. + * + * This re-reads the device and configuration descriptors and sets the + * configuration + * + * @dev: Device to set up + */ +int usb_select_config(struct usb_device *dev); + +/** + * usb_child_pre_probe() - Pre-probe function for USB devices + * + * This is called on all children of hubs and USB controllers (i.e. UCLASS_USB + * and UCLASS_USB_HUB) when a new device is about to be probed. It sets up the + * device from the saved platform data and calls usb_select_config() to + * finish set up. + * + * Once this is done, the device's normal driver can take over, knowing the + * device is accessible on the USB bus. + * + * This function is for use only by the internal USB stack. + * + * @dev: Device to set up + */ +int usb_child_pre_probe(struct udevice *dev); + +struct ehci_ctrl; + +/** + * usb_setup_ehci_gadget() - Set up a USB device as a gadget + * + * TODO(sjg@chromium.org): Tidy this up when USB gadgets can use driver model + * + * This provides a way to tell a controller to start up as a USB device + * instead of as a host. It is untested. + */ +int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp); + +/** + * usb_stor_reset() - Prepare to scan USB storage devices + * + * Empty the list of USB storage devices in preparation for scanning them. + * This must be called before a USB scan. + */ +void usb_stor_reset(void); + +#else /* !CONFIG_DM_USB */ + +struct usb_device *usb_get_dev_index(int index); + +#endif + +bool usb_device_has_child_on_port(struct usb_device *parent, int port); + int usb_hub_probe(struct usb_device *dev, int ifnum); void usb_hub_reset(void); -int hub_port_reset(struct usb_device *dev, int port, + +/** + * legacy_hub_port_reset() - reset a port given its usb_device pointer + * + * Reset a hub port and see if a device is present on that port, providing + * sufficient time for it to show itself. The port status is returned. + * + * With driver model this moves to hub_port_reset() and is passed a struct + * udevice. + * + * @dev: USB device to reset + * @port: Port number to reset (note ports are numbered from 0 here) + * @portstat: Returns port status + */ +int legacy_hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat); -struct usb_device *usb_alloc_new_device(void *controller); +int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat); + +/** + * usb_alloc_new_device() - Allocate a new device + * + * @devp: returns a pointer of a new device structure. With driver model this + * is a device pointer, but with legacy USB this pointer is + * driver-specific. + * @return 0 if OK, -ENOSPC if we have found out of room for new devices + */ +int usb_alloc_new_device(struct udevice *controller, struct usb_device **devp); + +/** + * usb_free_device() - Free a partially-inited device + * + * This is an internal function. It is used to reverse the action of + * usb_alloc_new_device() when we hit a problem during init. + */ +void usb_free_device(struct udevice *controller); int usb_new_device(struct usb_device *dev); -void usb_free_device(void); + int usb_alloc_device(struct usb_device *dev); +/** + * usb_emul_setup_device() - Set up a new USB device emulation + * + * This is normally called when a new emulation device is bound. It tells + * the USB emulation uclass about the features of the emulator. + * + * @dev: Emulation device + * @maxpacketsize: Maximum packet size (e.g. PACKET_SIZE_64) + * @strings: List of USB string descriptors, terminated by a NULL + * entry + * @desc_list: List of points or USB descriptors, terminated by NULL. + * The first entry must be struct usb_device_descriptor, + * and others follow on after that. + * @return 0 if OK, -ve on error + */ +int usb_emul_setup_device(struct udevice *dev, int maxpacketsize, + struct usb_string *strings, void **desc_list); + +/** + * usb_emul_control() - Send a control packet to an emulator + * + * @emul: Emulator device + * @udev: USB device (which the emulator is causing to appear) + * See struct dm_usb_ops for details on other parameters + * @return 0 if OK, -ve on error + */ +int usb_emul_control(struct udevice *emul, struct usb_device *udev, + unsigned long pipe, void *buffer, int length, + struct devrequest *setup); + +/** + * usb_emul_bulk() - Send a bulk packet to an emulator + * + * @emul: Emulator device + * @udev: USB device (which the emulator is causing to appear) + * See struct dm_usb_ops for details on other parameters + * @return 0 if OK, -ve on error + */ +int usb_emul_bulk(struct udevice *emul, struct usb_device *udev, + unsigned long pipe, void *buffer, int length); + +/** + * usb_emul_find() - Find an emulator for a particular device + * + * Check @pipe to find a device number on bus @bus and return it. + * + * @bus: USB bus (controller) + * @pipe: Describes pipe being used, and includes the device number + * @emulp: Returns pointer to emulator, or NULL if not found + * @return 0 if found, -ve on error + */ +int usb_emul_find(struct udevice *bus, ulong pipe, struct udevice **emulp); + +/** + * usb_emul_reset() - Reset all emulators ready for use + * + * Clear out any address information in the emulators and make then ready for + * a new USB scan + */ +void usb_emul_reset(struct udevice *dev); + #endif /*_USB_H_ */ diff --git a/include/usb_defs.h b/include/usb_defs.h index 236a5ecdf6..8214ba9bf5 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -165,12 +165,14 @@ #define USB_TEST_MODE_FORCE_ENABLE 0x05 -/* "pipe" definitions */ - -#define PIPE_ISOCHRONOUS 0 -#define PIPE_INTERRUPT 1 -#define PIPE_CONTROL 2 -#define PIPE_BULK 3 +/* + * "pipe" definitions, use unsigned so we can compare reliably, since this + * value is shifted up to bits 30/31. + */ +#define PIPE_ISOCHRONOUS 0U +#define PIPE_INTERRUPT 1U +#define PIPE_CONTROL 2U +#define PIPE_BULK 3U #define PIPE_DEVEP_MASK 0x0007ff00 #define USB_ISOCHRONOUS 0 @@ -178,6 +180,15 @@ #define USB_CONTROL 2 #define USB_BULK 3 +#define USB_PIPE_TYPE_SHIFT 30 +#define USB_PIPE_TYPE_MASK (3 << USB_PIPE_TYPE_SHIFT) + +#define USB_PIPE_DEV_SHIFT 8 +#define USB_PIPE_DEV_MASK (0x7f << USB_PIPE_DEV_SHIFT) + +#define USB_PIPE_EP_SHIFT 15 +#define USB_PIPE_EP_MASK (0xf << USB_PIPE_EP_SHIFT) + /* USB-status codes: */ #define USB_ST_ACTIVE 0x1 /* TD is active */ #define USB_ST_STALLED 0x2 /* TD is stalled */ @@ -286,4 +297,49 @@ #define HUB_CHANGE_LOCAL_POWER 0x0001 #define HUB_CHANGE_OVERCURRENT 0x0002 +/* Mask for wIndex in get/set port feature */ +#define USB_HUB_PORT_MASK 0xf + +/* + * CBI style + */ + +#define US_CBI_ADSC 0 + +/* Command Block Wrapper */ +struct umass_bbb_cbw { + __u32 dCBWSignature; +# define CBWSIGNATURE 0x43425355 + __u32 dCBWTag; + __u32 dCBWDataTransferLength; + __u8 bCBWFlags; +# define CBWFLAGS_OUT 0x00 +# define CBWFLAGS_IN 0x80 +# define CBWFLAGS_SBZ 0x7f + __u8 bCBWLUN; + __u8 bCDBLength; +# define CBWCDBLENGTH 16 + __u8 CBWCDB[CBWCDBLENGTH]; +}; +#define UMASS_BBB_CBW_SIZE 31 + +/* Command Status Wrapper */ +struct umass_bbb_csw { + __u32 dCSWSignature; +# define CSWSIGNATURE 0x53425355 + __u32 dCSWTag; + __u32 dCSWDataResidue; + __u8 bCSWStatus; +# define CSWSTATUS_GOOD 0x0 +# define CSWSTATUS_FAILED 0x1 +# define CSWSTATUS_PHASE 0x2 +}; +#define UMASS_BBB_CSW_SIZE 13 + +/* + * BULK only + */ +#define US_BBB_RESET 0xff +#define US_BBB_GET_MAX_LUN 0xfe + #endif /*_USB_DEFS_H_ */ diff --git a/include/video.h b/include/video.h index 673aa2ec56..65e4ec1e1a 100644 --- a/include/video.h +++ b/include/video.h @@ -69,4 +69,8 @@ void video_clear(void); int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode); #endif +#if defined(CONFIG_LG4573) +int lg4573_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif #endif diff --git a/include/vsprintf.h b/include/vsprintf.h index 5624482d57..09c8abd951 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -39,10 +39,33 @@ int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); long simple_strtol(const char *cp, char **endp, unsigned int base); + +/** + * panic() - Print a message and reset/hang + * + * Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is + * defined, then it will hang instead of reseting. + * + * @param fmt: printf() format string for message, which should not include + * \n, followed by arguments + */ void panic(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2), noreturn)); /** + * panic_str() - Print a message and reset/hang + * + * Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is + * defined, then it will hang instead of reseting. + * + * This function can be used instead of panic() when your board does not + * already use printf(), * to keep code size small. + * + * @param fmt: string to display, which should not include \n + */ +void panic_str(const char *str) __attribute__ ((noreturn)); + +/** * Format a string and place it in a buffer * * @param buf The buffer to place the result into |