diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/cache.h | 31 | ||||
-rw-r--r-- | include/configs/MPC8548CDS.h | 24 | ||||
-rw-r--r-- | include/configs/P2041RDB.h | 55 | ||||
-rw-r--r-- | include/configs/T102xRDB.h | 78 | ||||
-rw-r--r-- | include/configs/T104xRDB.h | 38 | ||||
-rw-r--r-- | include/configs/T208xRDB.h | 36 | ||||
-rw-r--r-- | include/configs/T4240RDB.h | 35 | ||||
-rw-r--r-- | include/configs/corenet_ds.h | 63 | ||||
-rw-r--r-- | include/configs/exynos5-common.h | 2 | ||||
-rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 36 | ||||
-rw-r--r-- | include/configs/sifive-fu540.h | 1 | ||||
-rw-r--r-- | include/configs/stm32mp1.h | 12 | ||||
-rw-r--r-- | include/configs/vexpress_aemv8a.h | 17 | ||||
-rw-r--r-- | include/dm/platform_data/serial_stm32.h | 15 | ||||
-rw-r--r-- | include/efi_api.h | 4 | ||||
-rw-r--r-- | include/efi_loader.h | 4 | ||||
-rw-r--r-- | include/env_callback.h | 2 | ||||
-rw-r--r-- | include/env_flags.h | 2 | ||||
-rw-r--r-- | include/image.h | 1 | ||||
-rw-r--r-- | include/net.h | 2 | ||||
-rw-r--r-- | include/net/pcap.h | 55 | ||||
-rw-r--r-- | include/netdev.h | 3 | ||||
-rw-r--r-- | include/power/stpmic1.h | 12 |
23 files changed, 257 insertions, 271 deletions
diff --git a/include/cache.h b/include/cache.h index c6334ca27f..32f59fd8f7 100644 --- a/include/cache.h +++ b/include/cache.h @@ -22,6 +22,22 @@ struct cache_ops { * @return 0 if OK, -ve on error */ int (*get_info)(struct udevice *dev, struct cache_info *info); + + /** + * enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev); + + /** + * disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ + int (*disable)(struct udevice *dev); }; #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) @@ -35,4 +51,19 @@ struct cache_ops { */ int cache_get_info(struct udevice *dev, struct cache_info *info); +/** + * cache_enable() - Enable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_enable(struct udevice *dev); + +/** + * cache_disable() - Flush and disable cache + * + * @dev: Device to check (UCLASS_CACHE) + * @return 0 if OK, -ve on error + */ +int cache_disable(struct udevice *dev); #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b37601c794..3a8c074dc5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -289,7 +287,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif /* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e196f3ce33..f8cfef7b2d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -483,7 +443,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5ab51e3233..8c1434fb10 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,96 +494,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif -/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 56ddef07f5..53ee1484d0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ab92ca3b68..3d95c4afa2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -433,49 +433,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 0accdc6119..57d8d171a7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -61,7 +61,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -176,44 +175,48 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e5c3a0c3f2..60e09c1939 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -499,7 +455,26 @@ #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 397bbf6d9d..e0a4d76d53 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -128,9 +128,9 @@ #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(MMC, mmc, 2) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e07d2a178f..1481d683e5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -207,8 +207,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -572,44 +570,56 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 858b7a7da1..736ceb1f48 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -26,6 +26,7 @@ #define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 24f7b9d463..92660fe2a0 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -10,11 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/stm32.h> -/* - * Number of clock ticks in 1 sec - */ -#define CONFIG_SYS_HZ 1000 - #ifndef CONFIG_STM32MP1_TRUSTED /* PSCI support */ #define CONFIG_ARMV7_PSCI_1_0 @@ -52,7 +47,6 @@ /* SPL support */ #ifdef CONFIG_SPL -/* BOOTROM load address */ /* SPL use DDR */ #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 @@ -85,7 +79,9 @@ #endif /* Dynamic MTD partition support */ +#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) #define CONFIG_SYS_MTDPARTS_RUNTIME +#endif /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS @@ -146,6 +142,7 @@ * and the ramdisk at the end. */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdelay=1\0" \ "kernel_addr_r=0xc2000000\0" \ "fdt_addr_r=0xc4000000\0" \ "scriptaddr=0xc4100000\0" \ @@ -154,7 +151,8 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "env_default=1\0" \ + "altbootcmd=run bootcmd\0" \ + "env_default=1\0" \ "env_check=if test $env_default -eq 1;"\ " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 9746470552..b2c14f9e10 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -16,8 +16,7 @@ #define CONFIG_REMAKE_ELF /* Link Definitions */ -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -83,8 +82,7 @@ #define GICR_BASE (0x2f100000) #else -#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ - defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #elif CONFIG_TARGET_VEXPRESS64_JUNO @@ -191,17 +189,6 @@ "booti $kernel_addr - $fdt_addr" -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=0x80080000\0" \ - "initrd_addr=0x84000000\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" - -#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" - - #endif /* Monitor Command Prompt */ diff --git a/include/dm/platform_data/serial_stm32.h b/include/dm/platform_data/serial_stm32.h deleted file mode 100644 index 85153df527..0000000000 --- a/include/dm/platform_data/serial_stm32.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - */ - -#ifndef __SERIAL_STM32_H -#define __SERIAL_STM32_H - -/* Information about a serial port */ -struct stm32_serial_platdata { - struct stm32_usart *base; /* address of registers in physical memory */ -}; - -#endif /* __SERIAL_STM32_H */ diff --git a/include/efi_api.h b/include/efi_api.h index 43778197af..cb895f31e5 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -483,7 +483,7 @@ struct efi_device_path_cdrom_path { struct efi_device_path dp; u32 boot_entry; u64 partition_start; - u64 partition_end; + u64 partition_size; } __packed; struct efi_device_path_file_path { @@ -1281,6 +1281,8 @@ struct efi_simple_network { struct efi_mac_address *dest_addr, u16 *protocol); struct efi_event *wait_for_packet; struct efi_simple_network_mode *mode; + /* private fields */ + u32 int_status; }; #define EFI_PXE_BASE_CODE_PROTOCOL_GUID \ diff --git a/include/efi_loader.h b/include/efi_loader.h index 5298ea7997..00eba8afa4 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -478,6 +478,10 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, /* Adds a range into the EFI memory map */ efi_status_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type, bool overlap_only_ram); +/* Adds a conventional range into the EFI memory map */ +efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end, + u64 ram_top); + /* Called by board init to initialize the EFI drivers */ efi_status_t efi_driver_init(void); /* Called by board init to initialize the EFI memory map */ diff --git a/include/env_callback.h b/include/env_callback.h index 982c07854d..74da20eec3 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -42,7 +42,7 @@ #define DNS_CALLBACK #endif -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET #define NET_CALLBACKS \ "bootfile:bootfile," \ "ipaddr:ipaddr," \ diff --git a/include/env_flags.h b/include/env_flags.h index e5380f2948..725841a891 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -36,7 +36,7 @@ enum env_flags_varaccess { #define CONFIG_ENV_FLAGS_LIST_STATIC "" #endif -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET #ifdef CONFIG_REGEX #define ETHADDR_WILDCARD "\\d*" #else diff --git a/include/image.h b/include/image.h index 404b7338e6..c1065c06f9 100644 --- a/include/image.h +++ b/include/image.h @@ -284,6 +284,7 @@ enum { IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */ IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ + IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/net.h b/include/net.h index a54d5eeac5..75a16e4c8f 100644 --- a/include/net.h +++ b/include/net.h @@ -816,7 +816,7 @@ static inline int is_valid_ethaddr(const u8 *addr) static inline void net_random_ethaddr(uchar *addr) { int i; - unsigned int seed = get_timer(0); + unsigned int seed = get_ticks(); for (i = 0; i < 6; i++) addr[i] = rand_r(&seed); diff --git a/include/net/pcap.h b/include/net/pcap.h new file mode 100644 index 0000000000..512ba982f1 --- /dev/null +++ b/include/net/pcap.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 + * Ramon Fried <rfried.dev@gmail.com> + */ + +/** + * pcap_init() - Initialize PCAP memory buffer + * + * @paddr physicaly memory address to store buffer + * @size maximum size of capture file in memory + * + * @return 0 on success, -ERROR on error + */ +int pcap_init(phys_addr_t paddr, unsigned long size); + +/** + * pcap_start_stop() - start / stop pcap capture + * + * @start if true, start capture if false stop capture + * + * @return 0 on success, -ERROR on error + */ +int pcap_start_stop(bool start); + +/** + * pcap_clear() - clear pcap capture buffer and statistics + * + * @return 0 on success, -ERROR on error + */ +int pcap_clear(void); + +/** + * pcap_print_status() - print status of pcap capture + * + * @return 0 on success, -ERROR on error + */ +int pcap_print_status(void); + +/** + * pcap_active() - check if pcap is enabled + * + * @return TRUE if active, FALSE if not. + */ +bool pcap_active(void); + +/** + * pcap_post() - Post a packet to PCAP file + * + * @packet: packet to post + * @len: packet length in bytes + * @outgoing packet direction (outgoing/incoming) + * @return 0 on success, -ERROR on error + */ +int pcap_post(const void *packet, size_t len, bool outgoing); diff --git a/include/netdev.h b/include/netdev.h index a40c4adaad..68a3fceab6 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -10,6 +10,7 @@ #ifndef _NETDEV_H_ #define _NETDEV_H_ +#include <phy_interface.h> /* * Board and CPU-specific initialization functions @@ -21,6 +22,8 @@ */ int board_eth_init(bd_t *bis); +int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h index 0e6721d852..dc8b5a7459 100644 --- a/include/power/stpmic1.h +++ b/include/power/stpmic1.h @@ -22,11 +22,12 @@ /* BUCKS_MRST_CR */ #define STPMIC1_MRST_BUCK(buck) BIT(buck) -#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0) +#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) /* LDOS_MRST_CR */ #define STPMIC1_MRST_LDO(ldo) BIT(ldo) -#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0) +#define STPMIC1_MRST_LDO_DEBUG 0 /* BUCKx_MAIN_CR (x=1...4) */ #define STPMIC1_BUCK_ENA BIT(0) @@ -107,11 +108,4 @@ enum { STPMIC1_PWR_SW2, STPMIC1_MAX_PWR_SW, }; - -int stpmic1_shadow_read_byte(u8 addr, u8 *buf); -int stpmic1_shadow_write_byte(u8 addr, u8 *buf); -int stpmic1_nvm_read_byte(u8 addr, u8 *buf); -int stpmic1_nvm_write_byte(u8 addr, u8 *buf); -int stpmic1_nvm_read_all(u8 *buf, int buf_len); -int stpmic1_nvm_write_all(u8 *buf, int buf_len); #endif |