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-rw-r--r--include/configs/am43xx_evm.h13
-rw-r--r--include/configs/dlvision-10g.h18
-rw-r--r--include/configs/hrcon.h89
-rw-r--r--include/configs/kwb.h8
-rw-r--r--include/configs/omap3_logic.h9
-rw-r--r--include/configs/pengwyn.h67
-rw-r--r--include/configs/strider.h651
-rw-r--r--include/configs/ti_armv7_common.h7
-rw-r--r--include/fastboot.h22
-rw-r--r--include/fb_mmc.h5
-rw-r--r--include/fb_nand.h11
-rw-r--r--include/gdsys_fpga.h101
-rw-r--r--include/image-sparse.h (renamed from include/aboot.h)17
-rw-r--r--include/linux/mtd/concat.h5
-rw-r--r--include/linux/mtd/doc2000.h11
-rw-r--r--include/linux/mtd/mtd.h2
-rw-r--r--include/linux/mtd/nand_ecc.h8
-rw-r--r--include/part.h3
-rw-r--r--include/part_efi.h3
-rw-r--r--include/uuid.h4
20 files changed, 973 insertions, 81 deletions
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index d93e3e7619..b02abd389e 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -177,11 +177,22 @@
"fdt ram 0x80f80000 0x80000;" \
"ramdisk ram 0x81000000 0x4000000\0"
+#define CONFIG_DFU_SF
+#define DFU_ALT_INFO_QSPI \
+ "dfu_alt_info_qspi=" \
+ "u-boot.bin raw 0x0 0x080000;" \
+ "u-boot.backup raw 0x080000 0x080000;" \
+ "u-boot-spl-os raw 0x100000 0x010000;" \
+ "u-boot-env raw 0x110000 0x010000;" \
+ "u-boot-env.backup raw 0x120000 0x010000;" \
+ "kernel raw 0x130000 0x800000\0"
+
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_RAM
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_QSPI
#else
#define DFUARGS
#endif
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 0b804ebdd7..b614f190bf 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -67,7 +67,7 @@
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
/*
@@ -105,17 +105,22 @@
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_DUAL
#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
-#define CONFIG_SYS_SPD_BUS_NUM 2
+#define CONFIG_SYS_SPD_BUS_NUM 4
/* Temp sensor/hwmon/dtt */
-#define CONFIG_SYS_DTT_BUS_NUM 2
+#define CONFIG_SYS_DTT_BUS_NUM 4
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
@@ -123,8 +128,9 @@
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
-#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
-#define CONFIG_SYS_SIL1178_I2C {0, 1}
+#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
+#define CONFIG_SYS_SIL1178_I2C {0, 2}
+#define CONFIG_SYS_DP501_I2C {0, 2}
/* EBC peripherals */
@@ -327,5 +333,7 @@
*/
#define CONFIG_SYS_MPC92469AC
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
#endif /* __CONFIG_H */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 3cb279a912..84d0928a67 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -20,7 +20,11 @@
#define CONFIG_SYS_TEXT_BASE 0xFE000000
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_IDENT_STRING " hrcon dh 0.01"
+#else
#define CONFIG_IDENT_STRING " hrcon 0.01"
+#endif
#define CONFIG_BOARD_EARLY_INIT_F
@@ -343,6 +347,22 @@
#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
+#endif
+
/*
* Software (bit-bang) I2C driver configuration
*/
@@ -358,34 +378,85 @@
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
+#define I2C_SOFT_DECLARATIONS5
+#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
+#define I2C_SOFT_DECLARATIONS6
+#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
+#define I2C_SOFT_DECLARATIONS7
+#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
+#define I2C_SOFT_DECLARATIONS8
+#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
+
+#ifdef CONFIG_HRCON_DH
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
+#endif
-#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
-#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
+ {12, 0x4c} }
+#else
+#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
+ {8, 0x4c} }
+#endif
#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
#endif
+#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
+
+#ifdef CONFIG_HRCON_DH
+#define I2C_ACTIVE \
+ do { \
+ if (I2C_ADAP_HWNR > 7) \
+ fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+ else \
+ fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+ } while (0)
+#else
#define I2C_ACTIVE { }
+#endif
#define I2C_TRISTATE { }
#define I2C_READ \
- (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+ (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
#define I2C_SDA(bit) \
do { \
if (bit) \
- fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+ fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
else \
- fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+ fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
} while (0)
#define I2C_SCL(bit) \
do { \
if (bit) \
- fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+ fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
else \
- fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+ fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
} while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
@@ -402,6 +473,10 @@ int fpga_gpio_get(unsigned int bus, int pin);
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_OSD_DH
+#endif
+
/*
* General PCI
* Addresses are mapped 1-1.
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 96f2e9d39b..45253b8118 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -57,6 +57,8 @@
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
BUR_COMMON_ENV \
+"bootaddr=0x80001100\0" \
+"bootdev=cpsw(0,0)\0" \
"vx_romfsbase=0x800E0000\0" \
"vx_romfssize=0x20000\0" \
"vx_memtop=0x8FBEF000\0" \
@@ -66,7 +68,7 @@ BUR_COMMON_ENV \
"logoaddr=0x82000000\0" \
"defaultARlen=0x8000\0" \
"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
-"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \
"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
"bmp display ${logoaddr} 0 0\0" \
"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
@@ -74,11 +76,11 @@ BUR_COMMON_ENV \
"mmcboot=echo booting AR from eMMC-flash ...; "\
"run logo0 || run logo1; " \
"run loadromfs; " \
- "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \
+ "fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \
"run defaultAR;\0" \
"netboot=echo booting AR from network ...; " \
"run loadromfs; " \
- "tftp ${loadaddr} arimg && go ${loadaddr}; " \
+ "tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \
"puts 'networkboot failed!';\0" \
"netscript=echo running script from network (tftp) ...; " \
"tftp 0x80000000 netscript.img && source; " \
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index ecd5615859..7b60f29bd2 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -272,13 +272,4 @@
#endif /* (CONFIG_CMD_NET) */
-/*
- * BOOTP fields
- */
-
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-
#endif /* __CONFIG_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index ccb5dd3c03..d68cdede86 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -127,35 +127,58 @@
#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
+
+/* NAND Configuration. */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE 4096
+#define CONFIG_SYS_NAND_OOBSIZE 224
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
+ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
+ 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
+ 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
+ 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
+ 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
+ 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
+ 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
+ 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
+ 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
+
#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_ECCBYTES 26
+#define CONFIG_SYS_NAND_ECCSTEPS 8
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
+/* END NAND Configuration. */
+
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_CMD_ASKENV /* monitor functions : ask for env variable */
+#define CONFIG_VERSION_VARIABLE /* monitor functions : u-boot version */
+#define CONFIG_CMD_DIAG /* monitor functions : Diagnostics */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
- "128k(SPL.backup1)," \
- "128k(SPL.backup2)," \
- "128k(SPL.backup3),1792k(u-boot)," \
- "128k(u-boot-spl-os)," \
- "128k(u-boot-env),5m(kernel),-(rootfs)"
+/* Size must be a multiple of Nand erase size (524288 b) */
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL)," \
+ "512k(SPL.backup1)," \
+ "512k(SPL.backup2)," \
+ "512k(SPL.backup3),1536k(u-boot)," \
+ "512k(u-boot-spl-os)," \
+ "512k(u-boot-env),5m(kernel),-(rootfs)"
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
@@ -198,11 +221,15 @@
#undef CONFIG_SPL_ETH_SUPPORT
#endif
+/* CPSW ethernet */
+#define CONFIG_NET_MULTI
+
/* Network */
#define CONFIG_CMD_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
+#define CONFIG_PHY_REALTEK
/* CPSW support */
#define CONFIG_SPL_ETH_SUPPORT
diff --git a/include/configs/strider.h b/include/configs/strider.h
new file mode 100644
index 0000000000..fb7b7f9551
--- /dev/null
+++ b/include/configs/strider.h
@@ -0,0 +1,651 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC830x 1 /* MPC830x family */
+#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
+#define CONFIG_STRIDER 1 /* STRIDER board specific */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
+#ifdef CONFIG_STRIDER_CPU
+#define CONFIG_IDENT_STRING " strider cpu 0.01"
+#else
+#define CONFIG_IDENT_STRING " strider con 0.01"
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_CMD_FPGAD
+#define CONFIG_CMD_IOLOOP
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_SVCOD_DIV_2 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_MII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH (\
+ SICRH_ESDHC_A_SD |\
+ SICRH_ESDHC_B_SD |\
+ SICRH_ESDHC_C_SD |\
+ SICRH_GPIO_A_GPIO |\
+ SICRH_GPIO_B_GPIO |\
+ SICRH_IEEE1588_A_GPIO |\
+ SICRH_USB |\
+ SICRH_GTM_GPIO |\
+ SICRH_IEEE1588_B_GPIO |\
+ SICRH_ETSEC2_GPIO |\
+ SICRH_GPIOSEL_1 |\
+ SICRH_TMROBI_V3P3 |\
+ SICRH_TSOBI1_V2P5 |\
+ SICRH_TSOBI2_V2P5) /* 0x0037f103 */
+#define CONFIG_SYS_SICRL (\
+ SICRL_SPI_PF0 |\
+ SICRL_UART_PF0 |\
+ SICRL_IRQ_PF0 |\
+ SICRL_I2C2_PF0 |\
+ SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_LOZ \
+ | DDRCDR_NZ_LOZ \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of one chip NT5TU64M16HG from NANYA
+ */
+
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_BANK_BIT_3 \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3 0
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00260802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (7 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (9 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x26279222 */
+#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (4 << TIMING_CFG2_CPO_SHIFT) \
+ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x021848c5 */
+#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x08240100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_16)
+ /* 0x43100000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0242 << SDRAM_MODE_SD_SHIFT))
+ /* ODT 150ohm CL=4, AL=0 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2 0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR 0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#if 1
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/*
+ * FPGA
+ */
+#define CONFIG_SYS_FPGA0_BASE 0xE0600000
+#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
+
+/* Window base at FPGA base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
+
+#define CONFIG_SYS_FPGA_COUNT 1
+
+#define CONFIG_SYS_MCLINK_MAX 3
+
+#define CONFIG_SYS_FPGA_PTR \
+ { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
+#define CONFIG_SYS_FPGA_NO_RFL_HI
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+
+#define CONFIG_PCA953X /* NXP PCA9554 */
+#define CONFIG_PCA9698 /* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
+#ifdef CONFIG_STRIDER_CON
+#define I2C_SOFT_DECLARATIONS5
+#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
+#define I2C_SOFT_DECLARATIONS6
+#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
+#define I2C_SOFT_DECLARATIONS7
+#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
+#define I2C_SOFT_DECLARATIONS8
+#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
+ {12, 0x4c} }
+#else
+#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
+ {4, 0x18} }
+#endif
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
+#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
+#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
+ (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
+#else
+#define I2C_SDA_GPIO 0x0040
+#define I2C_SCL_GPIO 0x0020
+#define I2C_FPGA_IDX I2C_ADAP_HWNR
+#endif
+#define I2C_ACTIVE { }
+#define I2C_TRISTATE { }
+#define I2C_READ \
+ (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+ else \
+ fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+ else \
+ fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+ } while (0)
+#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_OSD_SCREENS 1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM 1
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS 0
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+/*
+ * Environment
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+ BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+ BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define CONFIG_HOSTNAME hrcon
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS1\0" \
+ "u-boot=u-boot.bin\0" \
+ "kernel_addr=1000000\0" \
+ "fdt_addr=C00000\0" \
+ "fdtfile=hrcon.dtb\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+ " +${filesize};cp.b ${fileaddr} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp ${kernel_addr} $bootfile;" \
+ "tftp ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND \
+ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
+ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 32bb805f78..7810dd6c30 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -67,11 +67,6 @@
"rootfstype=${mmcrootfstype}\0"
/*
- * Default to a quick boot delay.
- */
-#define CONFIG_BOOTDELAY 1
-
-/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
* we say (for simplicity) that we have 1 bank, always, even when
* we have more. We always start at 0x80000000, and we place the
@@ -288,4 +283,6 @@
#define NETARGS ""
#endif
+#include <config_distro_defaults.h>
+
#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/include/fastboot.h b/include/fastboot.h
new file mode 100644
index 0000000000..db826d20bf
--- /dev/null
+++ b/include/fastboot.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2008 - 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * Copyright 2014 Linaro, Ltd.
+ * Rob Herring <robh@kernel.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _FASTBOOT_H_
+#define _FASTBOOT_H_
+
+/* The 64 defined bytes plus \0 */
+#define FASTBOOT_RESPONSE_LEN (64 + 1)
+
+void fastboot_fail(char *response, const char *reason);
+void fastboot_okay(char *response, const char *reason);
+
+#endif /* _FASTBOOT_H_ */
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 402ba9b1b4..978a1395a1 100644
--- a/include/fb_mmc.h
+++ b/include/fb_mmc.h
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-void fb_mmc_flash_write(const char *cmd, void *download_buffer,
- unsigned int download_bytes, char *response);
+void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
+ void *download_buffer, unsigned int download_bytes,
+ char *response);
void fb_mmc_erase(const char *cmd, char *response);
diff --git a/include/fb_nand.h b/include/fb_nand.h
new file mode 100644
index 0000000000..80ddef5656
--- /dev/null
+++ b/include/fb_nand.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ * Copyright 2015 Free Electrons.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void fb_nand_flash_write(const char *cmd, unsigned int session_id,
+ void *download_buffer, unsigned int download_bytes,
+ char *response);
+void fb_nand_erase(const char *cmd, char *response);
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 8a5efe732a..3b8762df66 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -143,7 +143,7 @@ struct ihs_fpga {
u16 reserved_2[2]; /* 0x001c */
struct ihs_io_ep ep; /* 0x0020 */
u16 reserved_3[9]; /* 0x002e */
- struct ihs_i2c i2c; /* 0x0040 */
+ struct ihs_i2c i2c0; /* 0x0040 */
u16 reserved_4[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
@@ -157,9 +157,9 @@ struct ihs_fpga {
u16 mc_rx_data; /* 0x0072 */
u16 reserved_5[69]; /* 0x0074 */
u16 reflection_high; /* 0x00fe */
- struct ihs_osd osd; /* 0x0100 */
+ struct ihs_osd osd0; /* 0x0100 */
u16 reserved_6[889]; /* 0x010e */
- u16 videomem[31736]; /* 0x0800 */
+ u16 videomem0[2048]; /* 0x0800 */
};
#endif
@@ -171,13 +171,15 @@ struct ihs_fpga {
u16 fpga_features; /* 0x0006 */
u16 reserved_0[1]; /* 0x0008 */
u16 top_interrupt; /* 0x000a */
- u16 reserved_1[4]; /* 0x000c */
+ u16 reserved_1[2]; /* 0x000c */
+ u16 control; /* 0x0010 */
+ u16 extended_control; /* 0x0012 */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
u16 reserved_2[2]; /* 0x001c */
struct ihs_io_ep ep; /* 0x0020 */
u16 reserved_3[9]; /* 0x002e */
- struct ihs_i2c i2c; /* 0x0040 */
+ struct ihs_i2c i2c0; /* 0x0040 */
u16 reserved_4[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
@@ -191,9 +193,82 @@ struct ihs_fpga {
u16 mc_rx_data; /* 0x0072 */
u16 reserved_5[69]; /* 0x0074 */
u16 reflection_high; /* 0x00fe */
- struct ihs_osd osd; /* 0x0100 */
+ struct ihs_osd osd0; /* 0x0100 */
+#ifdef CONFIG_SYS_OSD_DH
+ u16 reserved_6[57]; /* 0x010e */
+ struct ihs_osd osd1; /* 0x0180 */
+ u16 reserved_7[9]; /* 0x018e */
+ struct ihs_i2c i2c1; /* 0x01a0 */
+ u16 reserved_8[1834]; /* 0x01ac */
+ u16 videomem0[2048]; /* 0x1000 */
+ u16 videomem1[2048]; /* 0x2000 */
+#else
+ u16 reserved_6[889]; /* 0x010e */
+ u16 videomem0[2048]; /* 0x0800 */
+#endif
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[1]; /* 0x0008 */
+ u16 top_interrupt; /* 0x000a */
+ u16 reserved_1[3]; /* 0x000c */
+ u16 extended_control; /* 0x0012 */
+ struct ihs_gpio gpio; /* 0x0014 */
+ u16 mpc3w_control; /* 0x001a */
+ u16 reserved_2[2]; /* 0x001c */
+ struct ihs_io_ep ep; /* 0x0020 */
+ u16 reserved_3[9]; /* 0x002e */
+ u16 mc_int; /* 0x0040 */
+ u16 mc_int_en; /* 0x0042 */
+ u16 mc_status; /* 0x0044 */
+ u16 mc_control; /* 0x0046 */
+ u16 mc_tx_data; /* 0x0048 */
+ u16 mc_tx_address; /* 0x004a */
+ u16 mc_tx_cmd; /* 0x004c */
+ u16 mc_res; /* 0x004e */
+ u16 mc_rx_cmd_status; /* 0x0050 */
+ u16 mc_rx_data; /* 0x0052 */
+ u16 reserved_4[62]; /* 0x0054 */
+ struct ihs_i2c i2c0; /* 0x00d0 */
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[1]; /* 0x0008 */
+ u16 top_interrupt; /* 0x000a */
+ u16 reserved_1[4]; /* 0x000c */
+ struct ihs_gpio gpio; /* 0x0014 */
+ u16 mpc3w_control; /* 0x001a */
+ u16 reserved_2[2]; /* 0x001c */
+ struct ihs_io_ep ep; /* 0x0020 */
+ u16 reserved_3[9]; /* 0x002e */
+ struct ihs_i2c i2c0; /* 0x0040 */
+ u16 reserved_4[10]; /* 0x004c */
+ u16 mc_int; /* 0x0060 */
+ u16 mc_int_en; /* 0x0062 */
+ u16 mc_status; /* 0x0064 */
+ u16 mc_control; /* 0x0066 */
+ u16 mc_tx_data; /* 0x0068 */
+ u16 mc_tx_address; /* 0x006a */
+ u16 mc_tx_cmd; /* 0x006c */
+ u16 mc_res; /* 0x006e */
+ u16 mc_rx_cmd_status; /* 0x0070 */
+ u16 mc_rx_data; /* 0x0072 */
+ u16 reserved_5[70]; /* 0x0074 */
+ struct ihs_osd osd0; /* 0x0100 */
u16 reserved_6[889]; /* 0x010e */
- u16 videomem[31736]; /* 0x0800 */
+ u16 videomem0[2048]; /* 0x0800 */
};
#endif
@@ -208,11 +283,13 @@ struct ihs_fpga {
u16 reserved_1[29]; /* 0x001e */
u16 mpc3w_control; /* 0x0058 */
u16 reserved_2[3]; /* 0x005a */
- struct ihs_i2c i2c; /* 0x0060 */
- u16 reserved_3[205]; /* 0x0066 */
- struct ihs_osd osd; /* 0x0200 */
- u16 reserved_4[761]; /* 0x020e */
- u16 videomem[31736]; /* 0x0800 */
+ struct ihs_i2c i2c0; /* 0x0060 */
+ u16 reserved_3[2]; /* 0x006c */
+ struct ihs_i2c i2c1; /* 0x0070 */
+ u16 reserved_4[194]; /* 0x007c */
+ struct ihs_osd osd0; /* 0x0200 */
+ u16 reserved_5[761]; /* 0x020e */
+ u16 videomem0[2048]; /* 0x0800 */
};
#endif
diff --git a/include/aboot.h b/include/image-sparse.h
index 30e4d36df8..0382f5bd26 100644
--- a/include/aboot.h
+++ b/include/image-sparse.h
@@ -9,8 +9,16 @@
#define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1))
-void fastboot_fail(const char *s);
-void fastboot_okay(const char *s);
+typedef struct sparse_storage {
+ unsigned int block_sz;
+ unsigned int start;
+ unsigned int size;
+ const char *name;
+
+ int (*write)(struct sparse_storage *storage, void *priv,
+ unsigned int offset, unsigned int size,
+ char *data);
+} sparse_storage_t;
static inline int is_sparse_image(void *buf)
{
@@ -23,6 +31,5 @@ static inline int is_sparse_image(void *buf)
return 0;
}
-void write_sparse_image(block_dev_desc_t *dev_desc,
- disk_partition_t *info, const char *part_name,
- void *data, unsigned sz);
+int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
+ unsigned int session_id, void *data);
diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h
index 195a4a5426..a374ca98e8 100644
--- a/include/linux/mtd/concat.h
+++ b/include/linux/mtd/concat.h
@@ -1,9 +1,10 @@
/*
* MTD device concatenation layer definitions
*
- * (C) 2002 Robert Kaiser <rkaiser@sysgo.de>
+ * Copyright © 2002 Robert Kaiser <rkaiser@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
*
- * This code is GPL
*/
#ifndef MTD_CONCAT_H
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index ba29d53ec6..a3cfe6bdd9 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -1,12 +1,13 @@
/*
* Linux driver for Disk-On-Chip devices
*
- * Copyright (C) 1999 Machine Vision Holdings, Inc.
- * Copyright (C) 2001-2003 David Woodhouse <dwmw2@infradead.org>
- * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com>
- * Copyright (C) 2002-2003 SnapGear Inc
+ * Copyright © 1999 Machine Vision Holdings, Inc.
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
+ * Copyright © 2002-2003 SnapGear Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
*
- * Released under GPL
*/
#ifndef __MTD_DOC2000_H__
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index c2cd3df1fa..9da77ec144 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,7 +1,7 @@
/*
* Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
*
- * Released under GPL
+ * SPDX-License-Identifier: GPL-2.0+
*
*/
diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h
index 090da50542..02ba9f7e63 100644
--- a/include/linux/mtd/nand_ecc.h
+++ b/include/linux/mtd/nand_ecc.h
@@ -1,11 +1,11 @@
/*
* drivers/mtd/nand_ecc.h
*
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
+ * David Woodhouse <dwmw2@infradead.org>
+ * Thomas Gleixner <tglx@linutronix.de>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*
* This file is the header for the ECC algorithm.
*/
diff --git a/include/part.h b/include/part.h
index 8ea9b3049a..8b5ac12e2b 100644
--- a/include/part.h
+++ b/include/part.h
@@ -93,6 +93,9 @@ typedef struct disk_partition {
#ifdef CONFIG_PARTITION_UUIDS
char uuid[37]; /* filesystem UUID as string, if exists */
#endif
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ char type_guid[37]; /* type GUID as string, if exists */
+#endif
} disk_partition_t;
/* Misc _get_dev functions */
diff --git a/include/part_efi.h b/include/part_efi.h
index 3012b91ade..c8fc8738f9 100644
--- a/include/part_efi.h
+++ b/include/part_efi.h
@@ -43,6 +43,9 @@
#define PARTITION_BASIC_DATA_GUID \
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
+#define PARTITION_LINUX_FILE_SYSTEM_DATA_GUID \
+ EFI_GUID(0x0FC63DAF, 0x8483, 0x4772, \
+ 0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4)
#define PARTITION_LINUX_RAID_GUID \
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
diff --git a/include/uuid.h b/include/uuid.h
index 93027c1b28..c3f423fab4 100644
--- a/include/uuid.h
+++ b/include/uuid.h
@@ -36,6 +36,10 @@ enum {
int uuid_str_valid(const char *uuid);
int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format);
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format);
+#ifdef CONFIG_PARTITION_TYPE_GUID
+int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
+int uuid_guid_get_str(unsigned char *guid_bin, char *guid_str);
+#endif
void gen_rand_uuid(unsigned char *uuid_bin);
void gen_rand_uuid_str(char *uuid_str, int str_format);
#endif
generated by cgit (git 2.34.1) at 2024-12-29 18:57:48 +0000