diff options
Diffstat (limited to 'include')
26 files changed, 1286 insertions, 150 deletions
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 05777e6afe..859f41a0d4 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -117,11 +117,14 @@ struct udevice; struct gpio_desc { struct udevice *dev; /* Device, NULL for invalid GPIO */ unsigned long flags; -#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ -#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ -#define GPIOD_IS_IN (1 << 2) /* GPIO is an input */ -#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ -#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ +#define GPIOD_IS_OUT BIT(1) /* GPIO is an output */ +#define GPIOD_IS_IN BIT(2) /* GPIO is an input */ +#define GPIOD_ACTIVE_LOW BIT(3) /* GPIO is active when value is low */ +#define GPIOD_IS_OUT_ACTIVE BIT(4) /* set output active */ +#define GPIOD_OPEN_DRAIN BIT(5) /* GPIO is open drain type */ +#define GPIOD_OPEN_SOURCE BIT(6) /* GPIO is open source type */ +#define GPIOD_PULL_UP BIT(7) /* GPIO has pull-up enabled */ +#define GPIOD_PULL_DOWN BIT(8) /* GPIO has pull-down enabled */ uint offset; /* GPIO offset within the device */ /* @@ -130,6 +133,12 @@ struct gpio_desc { */ }; +/* helper to compute the value of the gpio output */ +#define GPIOD_FLAGS_OUTPUT_MASK (GPIOD_ACTIVE_LOW | GPIOD_IS_OUT_ACTIVE) +#define GPIOD_FLAGS_OUTPUT(flags) \ + (((((flags) & GPIOD_FLAGS_OUTPUT_MASK) == GPIOD_IS_OUT_ACTIVE) || \ + (((flags) & GPIOD_FLAGS_OUTPUT_MASK) == GPIOD_ACTIVE_LOW))) + /** * dm_gpio_is_valid() - Check if a GPIO is valid * @@ -254,8 +263,6 @@ struct dm_gpio_ops { int value); int (*get_value)(struct udevice *dev, unsigned offset); int (*set_value)(struct udevice *dev, unsigned offset, int value); - int (*get_open_drain)(struct udevice *dev, unsigned offset); - int (*set_open_drain)(struct udevice *dev, unsigned offset, int value); /** * get_function() Get the GPIO function * @@ -290,6 +297,37 @@ struct dm_gpio_ops { */ int (*xlate)(struct udevice *dev, struct gpio_desc *desc, struct ofnode_phandle_args *args); + + /** + * set_dir_flags() - Set GPIO dir flags + * + * This function should set up the GPIO configuration according to the + * information provide by the direction flags bitfield. + * + * This method is optional. + * + * @dev: GPIO device + * @offset: GPIO offset within that device + * @flags: GPIO configuration to use + * @return 0 if OK, -ve on error + */ + int (*set_dir_flags)(struct udevice *dev, unsigned int offset, + ulong flags); + + /** + * get_dir_flags() - Get GPIO dir flags + * + * This function return the GPIO direction flags used. + * + * This method is optional. + * + * @dev: GPIO device + * @offset: GPIO offset within that device + * @flags: place to put the used direction flags by GPIO + * @return 0 if OK, -ve on error + */ + int (*get_dir_flags)(struct udevice *dev, unsigned int offset, + ulong *flags); }; /** @@ -587,63 +625,41 @@ int dm_gpio_get_value(const struct gpio_desc *desc); int dm_gpio_set_value(const struct gpio_desc *desc, int value); /** - * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active - * - * This checks if open-drain-mode for a GPIO is enabled or not. This method is - * optional. - * - * @desc: GPIO description containing device, offset and flags, - * previously returned by gpio_request_by_name() - * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or - * -ve on error - */ -int dm_gpio_get_open_drain(struct gpio_desc *desc); - -/** - * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off - * - * This enables or disables open-drain mode for a GPIO. This method is - * optional; if the driver does not support it, nothing happens when the method - * is called. + * dm_gpio_set_dir() - Set the direction for a GPIO * - * In open-drain mode, instead of actively driving the output (Push-pull - * output), the GPIO's pin is connected to the collector (for a NPN transistor) - * or the drain (for a MOSFET) of a transistor, respectively. The pin then - * either forms an open circuit or a connection to ground, depending on the - * state of the transistor. + * This sets up the direction according to the GPIO flags: desc->flags. * * @desc: GPIO description containing device, offset and flags, * previously returned by gpio_request_by_name() * @return 0 if OK, -ve on error */ -int dm_gpio_set_open_drain(struct gpio_desc *desc, int value); +int dm_gpio_set_dir(struct gpio_desc *desc); /** - * dm_gpio_set_dir() - Set the direction for a GPIO + * dm_gpio_set_dir_flags() - Set direction using description and added flags * - * This sets up the direction according tot the provided flags. It will do - * nothing unless the direction is actually specified. + * This sets up the direction according to the provided flags and the GPIO + * description (desc->flags) which include direction information. + * Note that desc->flags is updated by this function. * * @desc: GPIO description containing device, offset and flags, * previously returned by gpio_request_by_name() - * @return 0 if OK, -ve on error + * @flags: New flags to use + * @return 0 if OK, -ve on error, in which case desc->flags is not updated */ -int dm_gpio_set_dir(struct gpio_desc *desc); +int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); /** - * dm_gpio_set_dir_flags() - Set direction using specific flags + * dm_gpio_get_dir_flags() - Get direction flags * - * This is like dm_gpio_set_dir() except that the flags value is provided - * instead of being used from desc->flags. This is needed because in many - * cases the GPIO description does not include direction information. - * Note that desc->flags is updated by this function. + * read the current direction flags * * @desc: GPIO description containing device, offset and flags, * previously returned by gpio_request_by_name() - * @flags: New flags to use + * @flags: place to put the used flags * @return 0 if OK, -ve on error, in which case desc->flags is not updated */ -int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); +int dm_gpio_get_dir_flags(struct gpio_desc *desc, ulong *flags); /** * gpio_get_number() - Get the global GPIO number of a GPIO diff --git a/include/ata.h b/include/ata.h index 3f4e4a0234..3d870c973f 100644 --- a/include/ata.h +++ b/include/ata.h @@ -6,11 +6,8 @@ /* * Most of the following information was derived from the document - * "Information Technology - AT Attachment-3 Interface (ATA-3)" - * which can be found at: - * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip - * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP - * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip + * "Information Technology - AT Attachment-3 Interface (ATA-3)", + * ANSI X3.298-1997. */ #ifndef _ATA_H @@ -71,42 +68,8 @@ #define ATA_LBA 0xE0 /* - * ATA Commands (only mandatory commands listed here) - */ -#define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */ -#define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */ -#define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/ -#define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/ -#define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */ -#define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */ -#define ATA_CMD_SEEK 0x70 /* Seek */ -#define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */ -#define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */ -#define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */ -#define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */ -#define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */ -#define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */ -#define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */ -#define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */ -#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */ -#define ATA_CMD_IDENT 0xEC /* Identify Device */ -#define ATA_CMD_SETF 0xEF /* Set Features */ -#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */ - -#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */ -#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */ -#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */ - -#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */ -#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */ - -/* * ATAPI Commands */ -#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */ -#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */ - - #define ATAPI_CMD_INQUIRY 0x12 #define ATAPI_CMD_REQ_SENSE 0x03 #define ATAPI_CMD_READ_CAP 0x25 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 0e20d6c728..c34c07a493 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -34,23 +34,49 @@ "ramdisk_addr_r=0x88080000\0" \ #define BOOT_TARGET_DEVICES(func) \ - func(UBIFS, ubifs, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + func(UBIFS, ubifs, 0) #define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" #include <config_distro_bootcmd.h> +#define GUARDIAN_DEFAULT_PROD_ENV \ + "factory_assembly_status=0\0" \ + "main_pcba_part_number=0\0" \ + "main_pcba_supplier=0\0" \ + "main_pcba_timestamp=0\0" \ + "main_pcba_hardware_version=0\0" \ + "main_pcba_id=0\0" \ + "main_pcba_aux_1=0\0" \ + "main_pcba_aux_2=0\0" \ + "main_pcba_aux_3=0\0" \ + "main_pcba_aux_4=0\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ AM335XX_BOARD_FDTFILE \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ - "bootlimit=3\0" \ + GUARDIAN_DEFAULT_PROD_ENV \ "bootubivol=rootfs\0" \ + "distro_bootcmd=" \ + "setenv autoload no; " \ + "setenv rootflags \"bulk_read,chk_data_crc\"; " \ + "setenv ethact usb_ether; " \ + "if test \"${swi_status}\" -eq 1; then " \ + "setenv extrabootargs \"swi_attached\"; " \ + "if dhcp; then " \ + "sleep 1; " \ + "if tftp \"${tftp_load_addr}\" \"bootscript.scr\"; then " \ + "source \"${tftp_load_addr}\"; " \ + "fi; " \ + "fi; " \ + "fi;" \ + "run bootcmd_ubifs0;\0" \ "altbootcmd=" \ - "setenv boot_config \"extlinux-rollback.conf\"; " \ - "run distro_bootcmd\0" + "setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; " \ + "run distro_bootcmd; " \ + "setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \ + "run bootcmd_ubifs0;\0" #endif /* ! CONFIG_SPL_BUILD */ @@ -109,4 +135,9 @@ #endif /* CONFIG_MTD_RAW_NAND */ +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + #endif /* ! __CONFIG_AM335X_GUARDIAN_H */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index d2ff7e9534..fb0037444f 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -146,8 +146,6 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ "fdt_addr_r=0x12100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ "pxefile_addr_r=0x17100000\0" \ "ramdisk_addr_r=0x12200000\0" \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index ea5ba6bfce..2a76f576a8 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -40,8 +40,6 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ "ramdisk_addr_r=0x82200000\0" \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index cbc7501bcc..4cdd3c53af 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -134,8 +134,6 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x12100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ "pxefile_addr_r=0x17100000\0" \ "ramdisk_addr_r=0x12200000\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 603ea3a053..7c00f78ef1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -108,8 +108,6 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x81000000\0" \ "ramdisk_addr_r=0x82100000\0" \ "scriptaddr=0x82500000\0" diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 1478ea844e..b03ccaf094 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -51,8 +51,6 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x81000000\0" \ "pxefile_addr_r=0x87100000\0" \ "ramdisk_addr_r=0x82100000\0" \ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h new file mode 100644 index 0000000000..8e54565f1a --- /dev/null +++ b/include/configs/imxrt1020-evk.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef __IMXRT1020_EVK_H +#define __IMXRT1020_EVK_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_INIT_SP_ADDR 0x20240000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_LOAD_ADDR 0x20209000 +#else +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_LOADADDR 0x80000000 +#endif + +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024) + +#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ + DMAMEM_SZ_ALL) + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x800023FD +#endif +/* For SPL ends */ + +#endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index cdec657fb0..3a6b972d9a 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -30,6 +30,21 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" +#endif + /* * Configuration of the external SDRAM memory */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index f347eeb39f..a30d2c0879 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -172,7 +172,6 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC #define CONFIG_FEC_ENET_DEV 1 #if (CONFIG_FEC_ENET_DEV == 0) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 7cce911314..af335bcfff 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -166,4 +166,13 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 1 +#if (CONFIG_FEC_ENET_DEV == 0) +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + #endif diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index f4113e03c4..ae2c0033d0 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -7,7 +7,7 @@ /* * sbc8548 board configuration file - * Please refer to doc/README.sbc8548 for more info. + * Please refer to board/sbc8548/README for more info. */ #ifndef __CONFIG_H #define __CONFIG_H diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 1ea6332878..895cd0324e 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -28,18 +28,11 @@ #define PHYS_SDRAM_SIZE (SZ_1G) #endif -#define CONFIG_MXC_UART - /* SPI Flash */ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K /* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 @@ -49,11 +42,13 @@ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 +#if !defined(CONFIG_DM_PMIC) #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 +#endif /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 0af52e5565..13b87e9b52 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -30,4 +30,7 @@ /* Bootcounter */ #define CONFIG_SYS_BOOTCOUNT_BE +/* I2C */ +#define CONFIG_SYS_I2C + #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index dc0a2efec6..82bff3608c 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -66,6 +66,12 @@ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_image=Image\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${kernel_image}; " \ + "tftp ${fdt_addr} verdin/${fdtfile}; " \ + "booti ${loadaddr} - ${fdt_addr}\0" \ "setup=setenv setupargs console=${console},${baudrate} " \ "console=tty1 consoleblank=0 earlycon\0" \ "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ diff --git a/include/dm/of_access.h b/include/dm/of_access.h index 92876b3ecb..f95a00d065 100644 --- a/include/dm/of_access.h +++ b/include/dm/of_access.h @@ -104,6 +104,46 @@ const void *of_get_property(const struct device_node *np, const char *name, int *lenp); /** + * of_get_first_property()- get to the pointer of the first property + * + * Get pointer to the first property of the node, it is used to iterate + * and read all the property with of_get_next_property_by_prop(). + * + * @np: Pointer to device node + * @return pointer to property or NULL if not found + */ +const struct property *of_get_first_property(const struct device_node *np); + +/** + * of_get_next_property() - get to the pointer of the next property + * + * Get pointer to the next property of the node, it is used to iterate + * and read all the property with of_get_property_by_prop(). + * + * @np: Pointer to device node + * @property: pointer of the current property + * @return pointer to next property or NULL if not found + */ +const struct property *of_get_next_property(const struct device_node *np, + const struct property *property); + +/** + * of_get_property_by_prop() - get a property value of a node property + * + * Get value for the property identified by node and property pointer. + * + * @node: node to read + * @property: pointer of the property to read + * @propname: place to property name on success + * @lenp: place to put length on success + * @return pointer to property value or NULL if error + */ +const void *of_get_property_by_prop(const struct device_node *np, + const struct property *property, + const char **name, + int *lenp); + +/** * of_device_is_compatible() - Check if the node matches given constraints * @device: pointer to node * @compat: required compatible string, NULL or "" for any match diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index ce5e366c06..618fc10390 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -59,6 +59,31 @@ struct ofnode_phandle_args { }; /** + * ofprop - reference to a property of a device tree node + * + * This struct hold the reference on one property of one node, + * using struct ofnode and an offset within the flat device tree or either + * a pointer to a struct property in the live device tree. + * + * Thus we can reference arguments in both the live tree and the flat tree. + * + * The property reference can also hold a null reference. This corresponds to + * a struct property NULL pointer or an offset of -1. + * + * @node: Pointer to device node + * @offset: Pointer into flat device tree, used for flat tree. + * @prop: Pointer to property, used for live treee. + */ + +struct ofprop { + ofnode node; + union { + int offset; + const struct property *prop; + }; +}; + +/** * _ofnode_to_np() - convert an ofnode to a live DT node pointer * * This cannot be called if the reference contains an offset. @@ -595,7 +620,7 @@ int ofnode_decode_display_timing(ofnode node, int index, struct display_timing *config); /** - * ofnode_get_property()- - get a pointer to the value of a node property + * ofnode_get_property() - get a pointer to the value of a node property * * @node: node to read * @propname: property to read @@ -605,6 +630,42 @@ int ofnode_decode_display_timing(ofnode node, int index, const void *ofnode_get_property(ofnode node, const char *propname, int *lenp); /** + * ofnode_get_first_property()- get the reference of the first property + * + * Get reference to the first property of the node, it is used to iterate + * and read all the property with ofnode_get_property_by_prop(). + * + * @node: node to read + * @prop: place to put argument reference + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int ofnode_get_first_property(ofnode node, struct ofprop *prop); + +/** + * ofnode_get_next_property() - get the reference of the next property + * + * Get reference to the next property of the node, it is used to iterate + * and read all the property with ofnode_get_property_by_prop(). + * + * @prop: reference of current argument and place to put reference of next one + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int ofnode_get_next_property(struct ofprop *prop); + +/** + * ofnode_get_property_by_prop() - get a pointer to the value of a property + * + * Get value for the property identified by the provided reference. + * + * @prop: reference on property + * @propname: If non-NULL, place to property name on success, + * @lenp: If non-NULL, place to put length on success + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +const void *ofnode_get_property_by_prop(const struct ofprop *prop, + const char **propname, int *lenp); + +/** * ofnode_is_available() - check if a node is marked available * * @node: node to check diff --git a/include/dm/read.h b/include/dm/read.h index 77d3bc8db5..03c15b8550 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -495,6 +495,42 @@ const void *dev_read_prop(const struct udevice *dev, const char *propname, int *lenp); /** + * dev_read_first_prop()- get the reference of the first property + * + * Get reference to the first property of the node, it is used to iterate + * and read all the property with dev_read_prop_by_prop(). + * + * @dev: device to check + * @prop: place to put argument reference + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int dev_read_first_prop(const struct udevice *dev, struct ofprop *prop); + +/** + * ofnode_get_next_property() - get the reference of the next property + * + * Get reference to the next property of the node, it is used to iterate + * and read all the property with dev_read_prop_by_prop(). + * + * @prop: reference of current argument and place to put reference of next one + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +int dev_read_next_prop(struct ofprop *prop); + +/** + * dev_read_prop_by_prop() - get a pointer to the value of a property + * + * Get value for the property identified by the provided reference. + * + * @prop: reference on property + * @propname: If non-NULL, place to property name on success, + * @lenp: If non-NULL, place to put length on success + * @return 0 if OK, -ve on error. -FDT_ERR_NOTFOUND if not found + */ +const void *dev_read_prop_by_prop(struct ofprop *prop, + const char **propname, int *lenp); + +/** * dev_read_alias_seq() - Get the alias sequence number of a node * * This works out whether a node is pointed to by an alias, and if so, the @@ -860,6 +896,23 @@ static inline const void *dev_read_prop(const struct udevice *dev, return ofnode_get_property(dev_ofnode(dev), propname, lenp); } +static inline int dev_read_first_prop(const struct udevice *dev, struct ofprop *prop) +{ + return ofnode_get_first_property(dev_ofnode(dev), prop); +} + +static inline int dev_read_next_prop(struct ofprop *prop) +{ + return ofnode_get_next_property(prop); +} + +static inline const void *dev_read_prop_by_prop(struct ofprop *prop, + const char **propname, + int *lenp) +{ + return ofnode_get_property_by_prop(prop, propname, lenp); +} + static inline int dev_read_alias_seq(const struct udevice *dev, int *devnump) { return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name, @@ -941,4 +994,18 @@ static inline int dev_read_alias_highest_id(const char *stem) ofnode_valid(subnode); \ subnode = ofnode_next_subnode(subnode)) +/** + * dev_for_each_property() - Helper function to iterate through property + * + * This creates a for() loop which works through the property in a device's + * device-tree node. + * + * @prop: struct ofprop holding the current property + * @dev: device to use for interation (struct udevice *) + */ +#define dev_for_each_property(prop, dev) \ + for (int ret_prop = dev_read_first_prop(dev, &prop); \ + !ret_prop; \ + ret_prop = dev_read_next_prop(&prop)) + #endif diff --git a/include/dt-bindings/clock/imxrt1020-clock.h b/include/dt-bindings/clock/imxrt1020-clock.h new file mode 100644 index 0000000000..836244358b --- /dev/null +++ b/include/dt-bindings/clock/imxrt1020-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H +#define __DT_BINDINGS_CLOCK_IMXRT1020_H + +#define IMXRT1020_CLK_DUMMY 0 +#define IMXRT1020_CLK_CKIL 1 +#define IMXRT1020_CLK_CKIH 2 +#define IMXRT1020_CLK_OSC 3 +#define IMXRT1020_CLK_PLL2_PFD0_352M 4 +#define IMXRT1020_CLK_PLL2_PFD1_594M 5 +#define IMXRT1020_CLK_PLL2_PFD2_396M 6 +#define IMXRT1020_CLK_PLL2_PFD3_297M 7 +#define IMXRT1020_CLK_PLL3_PFD0_720M 8 +#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9 +#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10 +#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11 +#define IMXRT1020_CLK_PLL2_198M 12 +#define IMXRT1020_CLK_PLL3_120M 13 +#define IMXRT1020_CLK_PLL3_80M 14 +#define IMXRT1020_CLK_PLL3_60M 15 +#define IMXRT1020_CLK_PLL2_BYPASS 16 +#define IMXRT1020_CLK_PLL3_BYPASS 17 +#define IMXRT1020_CLK_PLL6_BYPASS 18 +#define IMXRT1020_CLK_PRE_PERIPH_SEL 19 +#define IMXRT1020_CLK_PERIPH_SEL 20 +#define IMXRT1020_CLK_SEMC_ALT_SEL 21 +#define IMXRT1020_CLK_SEMC_SEL 22 +#define IMXRT1020_CLK_USDHC1_SEL 23 +#define IMXRT1020_CLK_USDHC2_SEL 24 +#define IMXRT1020_CLK_LPUART_SEL 25 +#define IMXRT1020_CLK_ARM_PODF 26 +#define IMXRT1020_CLK_LPUART_PODF 27 +#define IMXRT1020_CLK_USDHC1_PODF 28 +#define IMXRT1020_CLK_USDHC2_PODF 29 +#define IMXRT1020_CLK_SEMC_PODF 30 +#define IMXRT1020_CLK_AHB_PODF 31 +#define IMXRT1020_CLK_USDHC1 32 +#define IMXRT1020_CLK_USDHC2 33 +#define IMXRT1020_CLK_LPUART1 34 +#define IMXRT1020_CLK_SEMC 35 +#define IMXRT1020_CLK_PLL2_SYS 36 +#define IMXRT1020_CLK_PLL3_USB_OTG 37 +#define IMXRT1020_CLK_PLL4_AUDIO 38 +#define IMXRT1020_CLK_PLL6_ENET 39 +#define IMXRT1020_CLK_END 40 + +#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */ diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index 2cc10ae4bb..c029467e82 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -33,4 +33,10 @@ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + #endif diff --git a/include/dt-bindings/gpio/sandbox-gpio.h b/include/dt-bindings/gpio/sandbox-gpio.h new file mode 100644 index 0000000000..e4bfdb3ce1 --- /dev/null +++ b/include/dt-bindings/gpio/sandbox-gpio.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding sandbox,gpio + * + */ +#ifndef _DT_BINDINGS_GPIO_SANDBOX_GPIO_H +#define _DT_BINDINGS_GPIO_SANDBOX_GPIO_H + +/* + * Add a specific binding for sandbox gpio. + * The value need to be after the generic defines of + * dt-bindings/gpio/gpio.h + */ + +/* Bit 16 express GPIO input mode */ +#define GPIO_IN 0x10000 + +/* Bit 17 express GPIO output mode */ +#define GPIO_OUT 0x20000 + +/* Bit 18 express GPIO output is active */ +#define GPIO_OUT_ACTIVE 0x40000 + +#endif diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644 index 0000000000..c6bacb7378 --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h @@ -0,0 +1,763 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H + +/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */ + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x188 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0 0x014 0x188 0x420 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B 0x014 0x188 0x3E0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK 0x014 0x188 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x188 0x3B0 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00 0x014 0x188 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX 0x014 0x188 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02 0x014 0x188 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x18C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1 0x018 0x18C 0x424 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B 0x018 0x18C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT 0x018 0x18C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x18C 0x3AC 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01 0x018 0x18C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX 0x018 0x18C 0x320 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03 0x018 0x18C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x190 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2 0x01C 0x190 0x428 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX 0x01C 0x190 0x3E8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK 0x01C 0x190 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x190 0x3B8 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02 0x01C 0x190 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL 0x01C 0x190 0x37C 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x194 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3 0x020 0x194 0x42C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX 0x020 0x194 0x3E4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK 0x020 0x194 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x194 0x3B4 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03 0x020 0x194 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA 0x020 0x194 0x380 0x6 0x1 + +#define MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x198 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04 0x024 0x198 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT 0x024 0x198 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK 0x024 0x198 0x464 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16 0x024 0x198 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04 0x024 0x198 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x19C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05 0x028 0x19C 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN 0x028 0x19C 0x488 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x19C 0x468 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17 0x028 0x19C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05 0x028 0x19C 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x1A0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06 0x02C 0x1A0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX 0x02C 0x1A0 0x3DC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA 0x02C 0x1A0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18 0x02C 0x1A0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06 0x02C 0x1A0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x1A4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_XBAR1_INOUT07 0x030 0x1A4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_LPUART3_RX 0x030 0x1A4 0x3D8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_SAI2_RX_SYNC 0x030 0x1A4 0x460 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO19 0x030 0x1A4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_07_GPIO2_IO07 0x030 0x1A4 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x1A8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_XBAR1_INOUT08 0x034 0x1A8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXCAN2_TX 0x034 0x1A8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x1A8 0x45C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO20 0x034 0x1A8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_08_GPIO2_IO08 0x034 0x1A8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x1AC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_XBAR1_INOUT09 0x038 0x1AC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXCAN2_RX 0x038 0x1AC 0x324 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_09_SAI2_RX_BCLK 0x038 0x1AC 0x458 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO21 0x038 0x1AC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_09_GPIO2_IO09 0x038 0x1AC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS 0x03C 0x1B0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_XBAR1_INOUT10 0x03C 0x1B0 0x4B0 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_LPI2C4_SDA 0x03C 0x1B0 0x398 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_SAI1_TX_SYNC 0x03C 0x1B0 0x450 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_LPSPI2_SCK 0x03C 0x1B0 0x3B0 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_10_GPIO2_IO10 0x03C 0x1B0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMX00 0x03C 0x1B0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS 0x040 0x1B4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_XBAR1_INOUT11 0x040 0x1B4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_LPI2C4_SCL 0x040 0x1B4 0x394 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_SAI1_TX_BCLK 0x040 0x1B4 0x44C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_LPSPI2_PCS0 0x040 0x1B4 0x3AC 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_11_GPIO2_IO11 0x040 0x1B4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMX01 0x040 0x1B4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0 0x044 0x1B8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_XBAR1_INOUT12 0x044 0x1B8 0x4B4 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_LPUART6_TX 0x044 0x1B8 0x3F8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_SAI1_TX_DATA00 0x044 0x1B8 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_LPSPI2_SDO 0x044 0x1B8 0x3B8 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_12_GPIO2_IO12 0x044 0x1B8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_12_FLEXPWM2_PWMX02 0x044 0x1B8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0 0x048 0x1BC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_XBAR1_INOUT13 0x048 0x1BC 0x4B8 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_LPUART6_RX 0x048 0x1BC 0x3F4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_SAI1_RX_DATA00 0x048 0x1BC 0x438 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_LPSPI2_SDI 0x048 0x1BC 0x3B4 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_13_GPIO2_IO13 0x048 0x1BC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_FLEXPWM2_PWMX03 0x048 0x1BC 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_13_CCM_PMIC_RDY 0x048 0x1BC 0x300 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1 0x04C 0x1C0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_XBAR1_INOUT14 0x04C 0x1C0 0x4A0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_14_LPUART6_CTS_B 0x04C 0x1C0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_SAI1_RX_BCLK 0x04C 0x1C0 0x434 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x1C0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_GPIO2_IO14 0x04C 0x1C0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_14_FLEXCAN1_TX 0x04C 0x1C0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10 0x050 0x1C4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_XBAR1_INOUT15 0x050 0x1C4 0x4A4 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_15_LPUART6_RTS_B 0x050 0x1C4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_SAI1_RX_SYNC 0x050 0x1C4 0x448 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_15_WDOG1_B 0x050 0x1C4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_GPIO2_IO15 0x050 0x1C4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_15_FLEXCAN1_RX 0x050 0x1C4 0x320 0x6 0x3 + +#define MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00 0x054 0x1C8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_MQS_RIGHT 0x054 0x1C8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_SAI2_MCLK 0x054 0x1C8 0x454 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_16_GPIO2_IO16 0x054 0x1C8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_16_SRC_BOOT_MODE00 0x054 0x1C8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01 0x058 0x1CC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_MQS_LEFT 0x058 0x1CC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_SAI3_MCLK 0x058 0x1CC 0x46C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_17_GPIO2_IO17 0x058 0x1CC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_17_SRC_BOOT_MODE01 0x058 0x1CC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02 0x05C 0x1D0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_XBAR1_INOUT16 0x05C 0x1D0 0x4A8 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_18_LPI2C2_SDA 0x05C 0x1D0 0x388 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC 0x05C 0x1D0 0x448 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_18_FLEXIO1_FLEXIO22 0x05C 0x1D0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_GPIO2_IO18 0x05C 0x1D0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_18_SRC_BT_CFG00 0x05C 0x1D0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03 0x060 0x1D4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_XBAR1_INOUT17 0x060 0x1D4 0x4AC 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_19_LPI2C2_SCL 0x060 0x1D4 0x384 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK 0x060 0x1D4 0x434 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_19_FLEXIO1_FLEXIO23 0x060 0x1D4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_GPIO2_IO19 0x060 0x1D4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_19_SRC_BT_CFG01 0x060 0x1D4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04 0x064 0x1D8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXPWM1_PWMA03 0x064 0x1D8 0x334 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_20_LPUART2_CTS_B 0x064 0x1D8 0x3CC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_20_SAI1_MCLK 0x064 0x1D8 0x430 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_EMC_20_FLEXIO1_FLEXIO24 0x064 0x1D8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_GPIO2_IO20 0x064 0x1D8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_20_SRC_BT_CFG02 0x064 0x1D8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05 0x068 0x1DC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXPWM1_PWMB03 0x068 0x1DC 0x344 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_21_LPUART2_RTS_B 0x068 0x1DC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00 0x068 0x1DC 0x438 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_21_FLEXIO1_FLEXIO25 0x068 0x1DC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_GPIO2_IO21 0x068 0x1DC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_21_SRC_BT_CFG03 0x068 0x1DC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06 0x06C 0x1E0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXPWM1_PWMA02 0x06C 0x1E0 0x330 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_22_LPUART2_TX 0x06C 0x1E0 0x3D4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_22_SAI1_TX_DATA03 0x06C 0x1E0 0x43C 0x3 0x1 + +#define MXRT1020_IOMUXC_GPIO_EMC_22_FLEXIO1_FLEXIO26 0x06C 0x1E0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_GPIO2_IO22 0x06C 0x1E0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_22_SRC_BT_CFG04 0x06C 0x1E0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07 0x070 0x1E4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMB02 0x070 0x1E4 0x340 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_LPUART2_RX 0x070 0x1E4 0x3D0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_SAI1_TX_DATA02 0x070 0x1E4 0x440 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_23_FLEXIO1_FLEXIO27 0x070 0x1E4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_GPIO2_IO23 0x070 0x1E4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_23_SRC_BT_CFG05 0x070 0x1E4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08 0x074 0x1E8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMA01 0x074 0x1E8 0x32C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_24_LPUART8_CTS_B 0x074 0x1E8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_SAI1_TX_DATA01 0x074 0x1E8 0x444 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_24_FLEXIO1_FLEXIO28 0x074 0x1E8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_GPIO2_IO24 0x074 0x1E8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_24_SRC_BT_CFG06 0x074 0x1E8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09 0x078 0x1EC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMB01 0x078 0x1EC 0x33C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_25_LPUART8_RTS_B 0x078 0x1EC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00 0x078 0x1EC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_FLEXIO1_FLEXIO29 0x078 0x1EC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_GPIO2_IO25 0x078 0x1EC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_25_SRC_BT_CFG07 0x078 0x1EC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11 0x07C 0x1F0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMA00 0x07C 0x1F0 0x328 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_26_LPUART8_TX 0x07C 0x1F0 0x408 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK 0x07C 0x1F0 0x44C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO30 0x07C 0x1F0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_GPIO2_IO26 0x07C 0x1F0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_26_SRC_BT_CFG08 0x07C 0x1F0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12 0x080 0x1F4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMB00 0x080 0x1F4 0x338 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_27_LPUART8_RX 0x080 0x1F4 0x404 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC 0x080 0x1F4 0x450 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO31 0x080 0x1F4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_GPIO2_IO27 0x080 0x1F4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_27_SRC_BT_CFG09 0x080 0x1F4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS 0x084 0x1F8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM2_PWMA03 0x084 0x1F8 0x354 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_28_XBAR1_INOUT18 0x084 0x1F8 0x4BC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_SAI3_MCLK 0x084 0x1F8 0x46C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_28_EWM_OUT_B 0x084 0x1F8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_GPIO2_IO28 0x084 0x1F8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_GPT2_CAPTURE2 0x084 0x1F8 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMX00 0x084 0x1F8 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE 0x088 0x1FC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM2_PWMB03 0x088 0x1FC 0x364 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_29_XBAR1_INOUT19 0x088 0x1FC 0x4C0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_SAI3_RX_BCLK 0x088 0x1FC 0x470 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_29_WDOG2_RST_B_DEB 0x088 0x1FC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_GPIO2_IO29 0x088 0x1FC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_GPT2_COMPARE2 0x088 0x1FC 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_29_FLEXPWM1_PWMX01 0x088 0x1FC 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK 0x08C 0x200 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM2_PWMA02 0x08C 0x200 0x350 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_LPUART4_CTS_B 0x08C 0x200 0x3E0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_SAI3_RX_SYNC 0x08C 0x200 0x478 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_30_WDOG1_RST_B_DEB 0x08C 0x200 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_GPIO2_IO30 0x08C 0x200 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_GPT2_COMPARE3 0x08C 0x200 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_30_FLEXPWM1_PWMX02 0x08C 0x200 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01 0x090 0x204 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM2_PWMB02 0x090 0x204 0x360 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_31_LPUART4_RTS_B 0x090 0x204 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_SAI3_RX_DATA 0x090 0x204 0x474 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_31_WDOG2_B 0x090 0x204 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_GPIO2_IO31 0x090 0x204 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_GPT2_CLK 0x090 0x204 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_31_FLEXPWM1_PWMX03 0x090 0x204 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08 0x094 0x208 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_32_QTIMER1_TIMER0 0x094 0x208 0x410 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_32_LPUART4_TX 0x094 0x208 0x3E8 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_32_SAI3_TX_DATA 0x094 0x208 0x000 0x3 0x4 +#define MXRT1020_IOMUXC_GPIO_EMC_32_LPSPI4_SCK 0x094 0x208 0x3C0 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_32_GPIO3_IO00 0x094 0x208 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_32_REF_24M_OUT 0x094 0x208 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09 0x098 0x20C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_33_QTIMER1_TIMER1 0x098 0x20C 0x414 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_LPUART4_RX 0x098 0x20C 0x3E4 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_33_SAI3_TX_BCLK 0x098 0x20C 0x47C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_LPSPI4_PCS0 0x098 0x20C 0x3BC 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_33_GPIO3_IO01 0x098 0x20C 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10 0x09C 0x210 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_34_QTIMER1_TIMER2 0x09C 0x210 0x418 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_LPUART7_TX 0x09C 0x210 0x400 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_SAI3_TX_SYNC 0x09C 0x210 0x480 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_LPSPI4_SDO 0x09C 0x210 0x3C8 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_34_GPIO3_IO02 0x09C 0x210 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_34_ENET_CRS 0x09C 0x210 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11 0x0A0 0x214 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_35_QTIMER1_TIMER3 0x0A0 0x214 0x41C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_LPUART7_RX 0x0A0 0x214 0x3FC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_USDHC2_WP 0x0A0 0x214 0x49C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_LPSPI4_SDI 0x0A0 0x214 0x3C4 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_35_GPIO3_IO03 0x0A0 0x214 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_35_ENET_COL 0x0A0 0x214 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12 0x0A4 0x218 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_FLEXPWM2_PWMA01 0x0A4 0x218 0x34C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_36_LPUART5_CTS_B 0x0A4 0x218 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_CCM_PMIC_RDY 0x0A4 0x218 0x300 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_LPSPI4_PCS1 0x0A4 0x218 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_GPIO3_IO04 0x0A4 0x218 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_ENET_RX_CLK 0x0A4 0x218 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x218 0x494 0x7 0x4 + +#define MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13 0x0A8 0x21C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_FLEXPWM2_PWMB01 0x0A8 0x21C 0x35C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_37_LPUART5_RTS_B 0x0A8 0x21C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_MQS_RIGHT 0x0A8 0x21C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_LPSPI4_PCS2 0x0A8 0x21C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_GPIO3_IO05 0x0A8 0x21C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_ENET_RDATA03 0x0A8 0x21C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_37_USDHC1_VSELECT 0x0A8 0x21C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14 0x0AC 0x220 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_FLEXPWM2_PWMA00 0x0AC 0x220 0x348 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_38_LPUART5_TX 0x0AC 0x220 0x3F0 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_38_MQS_LEFT 0x0AC 0x220 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_LPSPI4_PCS3 0x0AC 0x220 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_GPIO3_IO06 0x0AC 0x220 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_ENET_RDATA02 0x0AC 0x220 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_38_USDHC1_CD_B 0x0AC 0x220 0x490 0x7 0x3 + +#define MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15 0x0B0 0x224 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_FLEXPWM2_PWMB00 0x0B0 0x224 0x358 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_39_LPUART5_RX 0x0B0 0x224 0x3EC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_39_USB_OTG1_OC 0x0B0 0x224 0x48C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x224 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_GPIO3_IO07 0x0B0 0x224 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_ENET_TX_ER 0x0B0 0x224 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_39_GPT1_CLK 0x0B0 0x224 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_40_SEMC_CSX00 0x0B4 0x228 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_XBAR1_INOUT18 0x0B4 0x228 0x4BC 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_40_SPDIF_OUT 0x0B4 0x228 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_USB_OTG1_ID 0x0B4 0x228 0x2FC 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_MDIO 0x0B4 0x228 0x308 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_EMC_40_GPIO3_IO08 0x0B4 0x228 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_ENET_TDATA03 0x0B4 0x228 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_40_GPT1_COMPARE3 0x0B4 0x228 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_EMC_41_SEMC_READY 0x0B8 0x22C 0x484 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_XBAR1_INOUT19 0x0B8 0x22C 0x4C0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_SPDIF_IN 0x0B8 0x22C 0x488 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_USB_OTG1_PWR 0x0B8 0x22C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_MDC 0x0B8 0x22C 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_EMC_41_GPIO3_IO09 0x0B8 0x22C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_ENET_TDATA02 0x0B8 0x22C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_EMC_41_GPT1_COMPARE2 0x0B8 0x22C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_JTAG_TMS 0x0BC 0x230 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x230 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_00_GPT1_COMPARE1 0x0BC 0x230 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_JTAG_TCK 0x0C0 0x234 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x234 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_01_GPT1_CAPTURE2 0x0C0 0x234 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_JTAG_MOD 0x0C4 0x238 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x238 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_02_GPT1_CAPTURE1 0x0C4 0x238 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_JTAG_TDI 0x0C8 0x23C 0x000 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC2_CD_B 0x0C8 0x23C 0x498 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_WDOG1_B 0x0C8 0x23C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_SAI1_MCLK 0x0C8 0x23C 0x430 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USDHC1_WP 0x0C8 0x23C 0x494 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x23C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x23C 0x48C 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_03_CCM_PMIC_RDY 0x0C8 0x23C 0x300 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_JTAG_TDO 0x0CC 0x240 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_FLEXCAN1_TX 0x0CC 0x240 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USDHC1_WP 0x0CC 0x240 0x494 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_QTIMER2_TIMER0 0x0CC 0x240 0x420 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_ENET_MDIO 0x0CC 0x240 0x308 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x240 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_USB_OTG1_PWR 0x0CC 0x240 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_04_EWM_OUT_B 0x0CC 0x240 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_JTAG_TRSTB 0x0D0 0x244 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_FLEXCAN1_RX 0x0D0 0x244 0x320 0x1 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USDHC1_CD_B 0x0D0 0x244 0x490 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_QTIMER2_TIMER1 0x0D0 0x244 0x424 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_ENET_MDC 0x0D0 0x244 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x244 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_USB_OTG1_ID 0x0D0 0x244 0x2FC 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_05_NMI_GLUE_NMI 0x0D0 0x244 0x40C 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_PIT_TRIGGER00 0x0D4 0x248 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_MQS_RIGHT 0x0D4 0x248 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX 0x0D4 0x248 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_QTIMER2_TIMER2 0x0D4 0x248 0x428 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_FLEXPWM2_PWMA03 0x0D4 0x248 0x354 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x248 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_06_REF_32K_OUT 0x0D4 0x248 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_PIT_TRIGGER01 0x0D8 0x24C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_MQS_LEFT 0x0D8 0x24C 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX 0x0D8 0x24C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_QTIMER2_TIMER3 0x0D8 0x24C 0x42C 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_FLEXPWM2_PWMB03 0x0D8 0x24C 0x364 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x24C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_07_REF_24M_OUT 0x0D8 0x24C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK 0x0DC 0x250 0x31C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL 0x0DC 0x250 0x38C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_LPUART1_CTS_B 0x0DC 0x250 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_KPP_COL00 0x0DC 0x250 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1 0x0DC 0x250 0x304 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x250 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_08_ARM_CM7_TXEV 0x0DC 0x250 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ENET_RDATA01 0x0E0 0x254 0x310 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA 0x0E0 0x254 0x390 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_LPUART1_RTS_B 0x0E0 0x254 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_KPP_ROW00 0x0E0 0x254 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x254 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_09_ARM_CM7_RXEV 0x0E0 0x254 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ENET_RDATA00 0x0E4 0x258 0x30C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK 0x0E4 0x258 0x3A0 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_LPUART5_TX 0x0E4 0x258 0x3F0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_KPP_COL01 0x0E4 0x258 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_FLEXPWM2_PWMA02 0x0E4 0x258 0x350 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x258 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_10_ARM_CM7_TRACE_CLK 0x0E4 0x258 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ENET_RX_EN 0x0E8 0x25C 0x314 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 0x0E8 0x25C 0x39C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_LPUART5_RX 0x0E8 0x25C 0x3EC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_KPP_ROW01 0x0E8 0x25C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_FLEXPWM2_PWMB02 0x0E8 0x25C 0x360 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x25C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_11_ARM_CM7_TRACE_SWO 0x0E8 0x25C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ENET_RX_ER 0x0EC 0x260 0x318 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO 0x0EC 0x260 0x3A8 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_LPUART3_CTS_B 0x0EC 0x260 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_KPP_COL02 0x0EC 0x260 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_FLEXPWM2_PWMA01 0x0EC 0x260 0x34C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x260 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_ARM_CM7_TRACE00 0x0EC 0x260 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_12_SNVS_HP_VIO_5_CTL 0x0EC 0x260 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ENET_TX_EN 0x0F0 0x264 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI 0x0F0 0x264 0x3A4 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_LPUART3_RTS_B 0x0F0 0x264 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_KPP_ROW02 0x0F0 0x264 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_FLEXPWM2_PWMB01 0x0F0 0x264 0x35C 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x264 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_ARM_CM7_TRACE01 0x0F0 0x264 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_13_SNVS_HP_VIO_5_B 0x0F0 0x264 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ENET_TDATA00 0x0F4 0x268 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x268 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_LPUART3_TX 0x0F4 0x268 0x3DC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_KPP_COL03 0x0F4 0x268 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_FLEXPWM2_PWMA00 0x0F4 0x268 0x348 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x268 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_ARM_CM7_TRACE02 0x0F4 0x268 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_14_WDOG1_ANY 0x0F4 0x268 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ENET_TDATA01 0x0F8 0x26C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x26C 0x324 0x1 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_LPUART3_RX 0x0F8 0x26C 0x3D8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_KPP_ROW03 0x0F8 0x26C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_FLEXPWM2_PWMB00 0x0F8 0x26C 0x358 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x26C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B0_15_ARM_CM7_TRACE03 0x0F8 0x26C 0x000 0x6 0x2 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SEMC_READY 0x0FC 0x270 0x484 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x0FC 0x270 0x374 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXCAN2_TX 0x0FC 0x270 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_SAI1_MCLK 0x0FC 0x270 0x430 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_FLEXIO1_FLEXIO15 0x0FC 0x270 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x270 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_ENET_1588_EVENT2_OUT 0x0FC 0x270 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_00_KPP_COL04 0x0FC 0x270 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SEMC_CSX00 0x100 0x274 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x100 0x274 0x378 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXCAN2_RX 0x100 0x274 0x324 0x2 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_SAI1_TX_BCLK 0x100 0x274 0x44C 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_FLEXIO1_FLEXIO14 0x100 0x274 0x000 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x274 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_ENET_1588_EVENT2_IN 0x100 0x274 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_01_KPP_ROW04 0x100 0x274 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SEMC_CSX01 0x104 0x278 0x000 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x104 0x278 0x368 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_LPSPI4_SCK 0x104 0x278 0x3C0 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_SAI1_TX_SYNC 0x104 0x278 0x450 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_FLEXIO1_FLEXIO13 0x104 0x278 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x278 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT3_OUT 0x104 0x278 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_02_KPP_COL05 0x104 0x278 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SEMC_CSX02 0x108 0x27C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x108 0x27C 0x370 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_LPSPI4_PCS0 0x108 0x27C 0x3BC 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_SAI1_TX_DATA00 0x108 0x27C 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_FLEXIO1_FLEXIO12 0x108 0x27C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x27C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT3_IN 0x108 0x27C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_03_KPP_ROW05 0x108 0x27C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SEMC_CSX03 0x10C 0x280 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x10C 0x280 0x36C 0x1 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI4_SDO 0x10C 0x280 0x3C8 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_SAI1_RX_SYNC 0x10C 0x280 0x448 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_FLEXIO1_FLEXIO11 0x10C 0x280 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x280 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_LPSPI1_PCS1 0x10C 0x280 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_04_KPP_COL06 0x10C 0x280 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_USDHC1_WP 0x110 0x284 0x494 0x0 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x110 0x284 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI4_SDI 0x110 0x284 0x3C4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_SAI1_RX_DATA00 0x110 0x284 0x438 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_FLEXIO1_FLEXIO10 0x110 0x284 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x284 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_LPSPI1_PCS2 0x110 0x284 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_05_KPP_ROW06 0x110 0x284 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_USDHC1_RESET_B 0x114 0x288 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXPWM1_PWMA00 0x114 0x288 0x328 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPUART2_CTS_B 0x114 0x288 0x3CC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_SAI1_RX_BCLK 0x114 0x288 0x434 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_FLEXIO1_FLEXIO09 0x114 0x288 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x288 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_LPSPI1_PCS3 0x114 0x288 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_06_KPP_COL07 0x114 0x288 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_USDHC1_VSELECT 0x118 0x28C 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXPWM1_PWMB00 0x118 0x28C 0x338 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPUART2_RTS_B 0x118 0x28C 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_SAI1_TX_DATA01 0x118 0x28C 0x444 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_FLEXIO1_FLEXIO08 0x118 0x28C 0x000 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x28C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_LPSPI3_PCS3 0x118 0x28C 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_07_KPP_ROW07 0x118 0x28C 0x000 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL 0x11C 0x290 0x384 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXPWM1_PWMA01 0x11C 0x290 0x32C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPUART2_TX 0x11C 0x290 0x3D4 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_SAI1_TX_DATA02 0x11C 0x290 0x440 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_FLEXIO1_FLEXIO07 0x11C 0x290 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x290 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_LPSPI3_PCS2 0x11C 0x290 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_08_XBAR1_INOUT12 0x11C 0x290 0x4B4 0x7 0x1 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA 0x120 0x294 0x388 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXPWM1_PWMB01 0x120 0x294 0x33C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPUART2_RX 0x120 0x294 0x3D0 0x2 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_SAI1_TX_DATA03 0x120 0x294 0x43C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_FLEXIO1_FLEXIO26 0x120 0x294 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x294 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_LPSPI3_PCS1 0x120 0x294 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_09_XBAR1_INOUT13 0x120 0x294 0x4B8 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USB_OTG1_PWR 0x124 0x298 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXPWM1_PWMA02 0x124 0x298 0x330 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_LPUART4_TX 0x124 0x298 0x3E8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_USDHC1_CD_B 0x124 0x298 0x490 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_FLEXIO1_FLEXIO05 0x124 0x298 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x298 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_10_GPT2_CAPTURE1 0x124 0x298 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USB_OTG1_ID 0x128 0x29C 0x2FC 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXPWM1_PWMB02 0x128 0x29C 0x340 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_LPUART4_RX 0x128 0x29C 0x3E4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_USDHC1_WP 0x128 0x29C 0x494 0x3 0x3 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_FLEXIO1_FLEXIO04 0x128 0x29C 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x29C 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_11_GPT2_COMPARE1 0x128 0x29C 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USB_OTG1_OC 0x12C 0x2A0 0x48C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x2A0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_LPSPI3_SCK 0x12C 0x2A0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_USDHC2_CD_B 0x12C 0x2A0 0x498 0x3 0x2 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXIO1_FLEXIO03 0x12C 0x2A0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x2A0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_12_FLEXPWM1_PWMA03 0x12C 0x2A0 0x334 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPI2C1_HREQ 0x130 0x2A4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x2A4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_LPSPI3_PCS0 0x130 0x2A4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_USDHC2_WP 0x130 0x2A4 0x49C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXIO1_FLEXIO02 0x130 0x2A4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x2A4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_13_FLEXPWM1_PWMB03 0x130 0x2A4 0x344 0x6 0x1 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL 0x134 0x2A8 0x37C 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x2A8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x2A8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_ENET_1588_EVENT0_OUT 0x134 0x2A8 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_FLEXIO1_FLEXIO01 0x134 0x2A8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x2A8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA 0x138 0x2AC 0x380 0x0 0x1 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x2AC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_LPSPI3_SDI 0x138 0x2AC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_ENET_1588_EVENT0_IN 0x138 0x2AC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_FLEXIO1_FLEXIO00 0x138 0x2AC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x2AC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 0x13C 0x2B0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_QTIMER1_TIMER0 0x13C 0x2B0 0x410 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI1_MCLK 0x13C 0x2B0 0x430 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_SAI2_MCLK 0x13C 0x2B0 0x454 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x13C 0x2B0 0x38C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_GPIO3_IO13 0x13C 0x2B0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x13C 0x2B0 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT14 0x13C 0x2B0 0x4A0 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 0x140 0x2B4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_QTIMER1_TIMER1 0x140 0x2B4 0x414 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_REF_24M_OUT 0x140 0x2B4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_SAI2_RX_SYNC 0x140 0x2B4 0x460 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x140 0x2B4 0x390 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_GPIO3_IO14 0x140 0x2B4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x140 0x2B4 0x000 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT15 0x140 0x2B4 0x4A4 0x7 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD 0x144 0x2B8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_QTIMER1_TIMER2 0x144 0x2B8 0x418 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPUART7_CTS_B 0x144 0x2B8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_SAI2_RX_BCLK 0x144 0x2B8 0x458 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_LPSPI1_SCK 0x144 0x2B8 0x3A0 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_GPIO3_IO15 0x144 0x2B8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_ENET_MDIO 0x144 0x2B8 0x308 0x6 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT16 0x144 0x2B8 0x4A8 0x7 0x1 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK 0x148 0x2BC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_QTIMER1_TIMER3 0x148 0x2BC 0x41C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPUART7_RTS_B 0x148 0x2BC 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_SAI2_RX_DATA 0x148 0x2BC 0x45C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_LPSPI1_PCS0 0x148 0x2BC 0x39C 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_GPIO3_IO16 0x148 0x2BC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_03_ENET_MDC 0x148 0x2BC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 0x14C 0x2C0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXCAN2_TX 0x14C 0x2C0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPUART7_TX 0x14C 0x2C0 0x400 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_SAI2_TX_DATA 0x14C 0x2C0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_LPSPI1_SDO 0x14C 0x2C0 0x3A8 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_GPIO3_IO17 0x14C 0x2C0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x14C 0x2C0 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 0x150 0x2C4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXCAN2_RX 0x150 0x2C4 0x324 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPUART7_RX 0x150 0x2C4 0x3FC 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_SAI2_TX_BCLK 0x150 0x2C4 0x464 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_LPSPI1_SDI 0x150 0x2C4 0x3A4 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_GPIO3_IO18 0x150 0x2C4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x150 0x2C4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B 0x154 0x2C8 0x490 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_RESET_B 0x154 0x2C8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_REF_32K_OUT 0x154 0x2C8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_SAI2_TX_SYNC 0x154 0x2C8 0x468 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_WDOG1_B 0x154 0x2C8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_GPIO3_IO19 0x154 0x2C8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B0_06_XBAR1_INOUT17 0x154 0x2C8 0x4AC 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA2 0x158 0x2CC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03 0x158 0x2CC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_LPUART6_TX 0x158 0x2CC 0x3F8 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT10 0x158 0x2CC 0x4B0 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX 0x158 0x2CC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_00_GPIO3_IO20 0x158 0x2CC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA3 0x15C 0x2D0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK 0x15C 0x2D0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_LPUART6_RX 0x15C 0x2D0 0x3F4 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXSPI_A_SS1_B 0x15C 0x2D0 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX 0x15C 0x2D0 0x320 0x4 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_01_GPIO3_IO21 0x15C 0x2D0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_USDHC2_CMD 0x160 0x2D4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00 0x160 0x2D4 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPUART8_TX 0x160 0x2D4 0x408 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL 0x160 0x2D4 0x394 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_ENET_1588_EVENT1_OUT 0x160 0x2D4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_GPIO3_IO22 0x160 0x2D4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_02_CCM_CLKO1 0x160 0x2D4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_USDHC2_CLK 0x164 0x2D8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02 0x164 0x2D8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPUART8_RX 0x164 0x2D8 0x404 0x2 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA 0x164 0x2D8 0x398 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_ENET_1588_EVENT1_IN 0x164 0x2D8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_GPIO3_IO23 0x164 0x2D8 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_03_CCM_CLKO2 0x164 0x2D8 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_USDHC2_DATA0 0x168 0x2DC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01 0x168 0x2DC 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_TX_CLK 0x168 0x2DC 0x31C 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_ENET_REF_CLK1 0x168 0x2DC 0x304 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_EWM_OUT_B 0x168 0x2DC 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_GPIO3_IO24 0x168 0x2DC 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_04_CCM_WAIT 0x168 0x2DC 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1 0x16C 0x2E0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x16C 0x2E0 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_ENET_RDATA01 0x16C 0x2E0 0x310 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_SAI3_MCLK 0x16C 0x2E0 0x46C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B 0x16C 0x2E0 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_GPIO3_IO25 0x16C 0x2E0 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_05_CCM_PMIC_RDY 0x16C 0x2E0 0x300 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_USDHC2_CD_B 0x170 0x2E4 0x498 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03 0x170 0x2E4 0x374 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_ENET_RDATA00 0x170 0x2E4 0x30C 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_SAI3_TX_BCLK 0x170 0x2E4 0x47C 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x170 0x2E4 0x3AC 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_GPIO3_IO26 0x170 0x2E4 0x000 0x5 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_06_CCM_STOP 0x170 0x2E4 0x000 0x6 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_USDHC2_RESET_B 0x174 0x2E8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x174 0x2E8 0x378 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_ENET_RX_EN 0x174 0x2E8 0x314 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_SAI3_TX_SYNC 0x174 0x2E8 0x480 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x174 0x2E8 0x3B0 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_07_GPIO3_IO27 0x174 0x2E8 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x178 0x2EC 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00 0x178 0x2EC 0x368 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_ENET_RX_ER 0x178 0x2EC 0x318 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_SAI3_TX_DATA 0x178 0x2EC 0x000 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x178 0x2EC 0x3B8 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_08_GPIO3_IO28 0x178 0x2EC 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x17C 0x2F0 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02 0x17C 0x2F0 0x370 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_ENET_TX_EN 0x17C 0x2F0 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_SAI3_RX_BCLK 0x17C 0x2F0 0x470 0x3 0x1 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x17C 0x2F0 0x3B4 0x4 0x2 +#define MXRT1020_IOMUXC_GPIO_SD_B1_09_GPIO3_IO29 0x17C 0x2F0 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x180 0x2F4 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01 0x180 0x2F4 0x36C 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_ENET_TDATA00 0x180 0x2F4 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_SAI3_RX_SYNC 0x180 0x2F4 0x478 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x180 0x2F4 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_10_GPIO3_IO30 0x180 0x2F4 0x000 0x5 0x0 + +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x184 0x2F8 0x000 0x0 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B 0x184 0x2F8 0x000 0x1 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_ENET_TDATA01 0x184 0x2F8 0x000 0x2 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_SAI3_RX_DATA 0x184 0x2F8 0x474 0x3 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x184 0x2F8 0x000 0x4 0x0 +#define MXRT1020_IOMUXC_GPIO_SD_B1_11_GPIO3_IO31 0x184 0x2F8 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H */ diff --git a/include/generic-phy.h b/include/generic-phy.h index 95caf58341..73537025c2 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -7,6 +7,8 @@ #ifndef __GENERIC_PHY_H #define __GENERIC_PHY_H +#include <dm/ofnode.h> + struct ofnode_phandle_args; /** @@ -194,6 +196,33 @@ int generic_phy_get_by_index(struct udevice *user, int index, struct phy *phy); /** + * generic_phy_get_by_node() - Get a PHY device by integer index on ofnode + * + * @node: the device node + * @index: The index in the list of available PHYs + * @phy: A pointer to the PHY port + * + * This looks up a PHY device for a client device based on its ofnode and on + * its position in the list of the possible PHYs. + * + * example: + * usb1: usb_otg_ss@xxx { + * compatible = "xxx"; + * reg = <xxx>; + * . + * . + * phys = <&usb2_phy>, <&usb3_phy>; + * . + * . + * }; + * the USB2 phy can be accessed by passing index '0' and the USB3 phy can + * be accessed by passing index '1' + * + * @return 0 if OK, or a negative error code + */ +int generic_phy_get_by_node(ofnode node, int index, struct phy *phy); + +/** * generic_phy_get_by_name() - Get a PHY device by its name. * * @user: the client device diff --git a/include/image.h b/include/image.h index 2388c1f204..de55b2fb57 100644 --- a/include/image.h +++ b/include/image.h @@ -453,6 +453,15 @@ typedef struct table_entry { } table_entry_t; /* + * Compression type and magic number mapping table. + */ +struct comp_magic_map { + int comp_id; + const char *name; + unsigned char magic[2]; +}; + +/* * get_table_entry_id() scans the translation table trying to find an * entry that matches the given short name. If a matching entry is * found, it's id is returned to the caller. @@ -869,6 +878,18 @@ static inline int image_check_target_arch(const image_header_t *hdr) #endif /* USE_HOSTCC */ /** + * image_decomp_type() - Find out compression type of an image + * + * @buf: Address in U-Boot memory where image is loaded. + * @len: Length of the compressed image. + * @return compression type or IH_COMP_NONE if not compressed. + * + * Note: Only following compression types are supported now. + * lzo, lzma, gzip, bzip2 + */ +int image_decomp_type(const unsigned char *buf, ulong len); + +/** * image_decomp() - decompress an image * * @comp: Compression algorithm that is used (IH_COMP_...) diff --git a/include/libata.h b/include/libata.h index 25296ac66d..b03b29960d 100644 --- a/include/libata.h +++ b/include/libata.h @@ -133,49 +133,49 @@ enum { ATA_REG_IRQ = ATA_REG_NSECT, /* ATA device commands */ - ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */ - ATA_CMD_CHK_POWER = 0xE5, /* check power mode */ - ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */ - ATA_CMD_IDLE = 0xE3, /* place in idle power mode */ - ATA_CMD_EDD = 0x90, /* execute device diagnostic */ - ATA_CMD_FLUSH = 0xE7, - ATA_CMD_FLUSH_EXT = 0xEA, - ATA_CMD_ID_ATA = 0xEC, - ATA_CMD_ID_ATAPI = 0xA1, - ATA_CMD_READ = 0xC8, - ATA_CMD_READ_EXT = 0x25, - ATA_CMD_WRITE = 0xCA, - ATA_CMD_WRITE_EXT = 0x35, - ATA_CMD_WRITE_FUA_EXT = 0x3D, - ATA_CMD_FPDMA_READ = 0x60, - ATA_CMD_FPDMA_WRITE = 0x61, - ATA_CMD_PIO_READ = 0x20, - ATA_CMD_PIO_READ_EXT = 0x24, - ATA_CMD_PIO_WRITE = 0x30, - ATA_CMD_PIO_WRITE_EXT = 0x34, - ATA_CMD_READ_MULTI = 0xC4, - ATA_CMD_READ_MULTI_EXT = 0x29, - ATA_CMD_WRITE_MULTI = 0xC5, - ATA_CMD_WRITE_MULTI_EXT = 0x39, - ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE, - ATA_CMD_SET_FEATURES = 0xEF, - ATA_CMD_SET_MULTI = 0xC6, - ATA_CMD_PACKET = 0xA0, - ATA_CMD_VERIFY = 0x40, - ATA_CMD_VERIFY_EXT = 0x42, - ATA_CMD_STANDBYNOW1 = 0xE0, - ATA_CMD_IDLEIMMEDIATE = 0xE1, - ATA_CMD_SLEEP = 0xE6, - ATA_CMD_INIT_DEV_PARAMS = 0x91, - ATA_CMD_READ_NATIVE_MAX = 0xF8, + ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */ + ATA_CMD_PIO_READ = 0x20, /* Read sectors with retry */ + ATA_CMD_PIO_READ_EXT = 0x24, + ATA_CMD_READ_EXT = 0x25, ATA_CMD_READ_NATIVE_MAX_EXT = 0x27, - ATA_CMD_SET_MAX = 0xF9, - ATA_CMD_SET_MAX_EXT = 0x37, - ATA_CMD_READ_LOG_EXT = 0x2f, - ATA_CMD_PMP_READ = 0xE4, - ATA_CMD_PMP_WRITE = 0xE8, - ATA_CMD_CONF_OVERLAY = 0xB1, - ATA_CMD_SEC_FREEZE_LOCK = 0xF5, + ATA_CMD_READ_MULTI_EXT = 0x29, + ATA_CMD_READ_LOG_EXT = 0x2f, + ATA_CMD_PIO_WRITE = 0x30, /* write sectors with retry */ + ATA_CMD_PIO_WRITE_EXT = 0x34, + ATA_CMD_WRITE_EXT = 0x35, + ATA_CMD_SET_MAX_EXT = 0x37, + ATA_CMD_WRITE_MULTI_EXT = 0x39, + ATA_CMD_WRITE_FUA_EXT = 0x3D, + ATA_CMD_VERIFY = 0x40, /* read verify sectors with retry */ + ATA_CMD_VERIFY_EXT = 0x42, + ATA_CMD_FPDMA_READ = 0x60, + ATA_CMD_FPDMA_WRITE = 0x61, + ATA_CMD_EDD = 0x90, /* execute device diagnostic */ + ATA_CMD_INIT_DEV_PARAMS = 0x91, /* initialize device parameters */ + ATA_CMD_PACKET = 0xA0, /* ATAPI packet */ + ATA_CMD_ID_ATAPI = 0xA1, /* ATAPI identify device */ + ATA_CMD_CONF_OVERLAY = 0xB1, + ATA_CMD_READ_MULTI = 0xC4, /* read multiple */ + ATA_CMD_WRITE_MULTI = 0xC5, /* write multiple */ + ATA_CMD_SET_MULTI = 0xC6, /* set multiple mode */ + ATA_CMD_READ = 0xC8, /* read DMA with retry */ + ATA_CMD_WRITE = 0xCA, /* write DMA with retry */ + ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE, + ATA_CMD_STANDBYNOW1 = 0xE0, /* standby immediate */ + ATA_CMD_IDLEIMMEDIATE = 0xE1, /* idle immediate */ + ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */ + ATA_CMD_IDLE = 0xE3, /* place in idle power mode */ + ATA_CMD_PMP_READ = 0xE4, /* read buffer */ + ATA_CMD_CHK_POWER = 0xE5, /* check power mode */ + ATA_CMD_SLEEP = 0xE6, /* sleep */ + ATA_CMD_FLUSH = 0xE7, + ATA_CMD_PMP_WRITE = 0xE8, /* write buffer */ + ATA_CMD_FLUSH_EXT = 0xEA, + ATA_CMD_ID_ATA = 0xEC, /* identify device */ + ATA_CMD_SET_FEATURES = 0xEF, /* set features */ + ATA_CMD_SEC_FREEZE_LOCK = 0xF5, /* security freeze */ + ATA_CMD_READ_NATIVE_MAX = 0xF8, + ATA_CMD_SET_MAX = 0xF9, /* READ_LOG_EXT pages */ ATA_LOG_SATA_NCQ = 0x10, |