diff options
Diffstat (limited to 'include')
41 files changed, 890 insertions, 202 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 02a3ed6838..7c2220643b 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -137,7 +137,7 @@ typedef struct global_data { #if defined(CONFIG_TRANSLATION_OFFSET) fdt_addr_t translation_offset; /* optional translation offset */ #endif -#if defined(CONFIG_WDT) +#if CONFIG_IS_ENABLED(WDT) struct udevice *watchdog_dev; #endif } gd_t; diff --git a/include/clk.h b/include/clk.h index d24e99713a..f8f56d9cf0 100644 --- a/include/clk.h +++ b/include/clk.h @@ -20,7 +20,7 @@ * clock provider. This API provides a standard means for drivers to enable and * disable clocks, and to set the rate at which they oscillate. * - * A driver that implements UCLASS_CLOCK is a clock provider. A provider will + * A driver that implements UCLASS_CLK is a clock provider. A provider will * often implement multiple separate clocks, since the hardware it manages * often has this capability. clk-uclass.h describes the interface which * clock providers must implement. @@ -40,6 +40,10 @@ struct udevice; * other clock APIs to identify which clock signal to operate upon. * * @dev: The device which implements the clock signal. + * @rate: The clock rate (in HZ). + * @flags: Flags used across common clock structure (e.g. CLK_) + * Clock IP blocks specific flags (i.e. mux, div, gate, etc) are defined + * in struct's for those devices (e.g. struct clk_mux). * @id: The clock signal ID within the provider. * @data: An optional data field for scenarios where a single integer ID is not * sufficient. If used, it can be populated through an .of_xlate op and @@ -55,6 +59,8 @@ struct udevice; */ struct clk { struct udevice *dev; + long long rate; /* in HZ */ + u32 flags; /* * Written by of_xlate. In the future, we might add more fields here. */ @@ -253,6 +259,24 @@ int clk_free(struct clk *clk); ulong clk_get_rate(struct clk *clk); /** + * clk_get_parent() - Get current clock's parent. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return pointer to parent's struct clk, or error code passed as pointer + */ +struct clk *clk_get_parent(struct clk *clk); + +/** + * clk_get_parent_rate() - Get parent of current clock rate. + * + * @clk: A clock struct that was previously successfully requested by + * clk_request/get_by_*(). + * @return clock rate in Hz, or -ve error code. + */ +long long clk_get_parent_rate(struct clk *clk); + +/** * clk_set_rate() - Set current clock rate. * * @clk: A clock struct that was previously successfully requested by @@ -321,4 +345,15 @@ static inline bool clk_valid(struct clk *clk) { return !!clk->dev; } + +/** + * clk_get_by_id() - Get the clock by its ID + * + * @id: The clock ID to search for + * + * @clkp: A pointer to clock struct that has been found among added clocks + * to UCLASS_CLK + * @return zero on success, or -ENOENT on error + */ +int clk_get_by_id(ulong id, struct clk **clkp); #endif diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 22d1e41bc8..a037349162 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -223,7 +223,6 @@ #define CONFIG_IMX_VIDEO_SKIP #endif -#define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_CMD_PCI diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e0521abe90..2e8481890f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -28,6 +28,8 @@ * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 + #ifdef CONFIG_USB_MUSB_AM35X #ifdef CONFIG_USB_MUSB_HOST diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index e69e800f61..e181b30564 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -22,7 +22,9 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define CONSOLEDEV "ttyS2" #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index db37fa7b73..974571df43 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -176,27 +176,6 @@ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ "sdrootpart=2\0" - -#define USB_BOOTCMD \ - "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} ro,noatime " \ - "rootfstype=ext4 rootwait\0" \ - "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \ - "setenv bootargs ${defargs} ${setupargs} " \ - "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ - "run usbdtbload; load usb " \ - "${usbdev}:${usbbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "usbbootpart=1\0" \ - "usbdev=0\0" \ - "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} "\ - "${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam \" - " \ - "${fdt_addr_r}\" && true\0" \ - "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \ - "usbrootpart=2\0" - - #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 #define FDT_FILE "imx6q-apalis-eval.dtb" #define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" @@ -219,7 +198,6 @@ MEM_LAYOUT_ENV_SETTINGS \ NFS_BOOTCMD \ SD_BOOTCMD \ - USB_BOOTCMD \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index a24814673c..e998d9b1b2 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -196,7 +196,6 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 00e5667499..361e6ac654 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -45,9 +45,6 @@ #define CONFIG_LG4573_BUS 0 #define CONFIG_LG4573_CS 0 -#define CONFIG_PWM_IMX -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #include "aristainetos-common.h" #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h index cfe0e053b6..cdeb7a3b03 100644 --- a/include/configs/aristainetos2b.h +++ b/include/configs/aristainetos2b.h @@ -45,9 +45,6 @@ #define CONFIG_LG4573_BUS 0 #define CONFIG_LG4573_CS 1 -#define CONFIG_PWM_IMX -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #include "aristainetos-common.h" #endif /* __ARISTAINETOS2B_CONFIG_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 21d9a3da01..2c43862800 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -123,7 +123,7 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ - "vidargs=video=mxsfb:640x480-16@60" + "vidargs=video=mxsfb:640x480M-16@60" #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 86f3f0d4fa..147f801353 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -165,25 +165,6 @@ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ "sdrootpart=2\0" -#define USB_BOOTCMD \ - "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \ - "rootfstype=ext4 rootwait\0" \ - "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \ - "setenv bootargs ${defargs} ${setupargs} " \ - "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ - "run usbdtbload; " \ - "load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "usbbootpart=1\0" \ - "usbdev=0\0" \ - "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \ - "${fdt_addr_r} " \ - "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \ - "true\0" \ - "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \ - "usbrootpart=2\0" - #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ @@ -201,7 +182,6 @@ MEM_LAYOUT_ENV_SETTINGS \ NFS_BOOTCMD \ SD_BOOTCMD \ - USB_BOOTCMD \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 40173b18fa..49cdd61038 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -46,6 +46,46 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 +#ifndef PARTS_DEFAULT +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=boot,start=1M,size=32M,uuid=${uuid_gpt_boot};" \ + "name=environment,size=4M,uuid=${uuid_gpt_environment};" \ + "name=recovery,size=16M,uuid=${uuid_gpt_recovery};" \ + "name=system,size=1536M,uuid=${uuid_gpt_system};" \ + "name=cache,size=512M,uuid=${uuid_gpt_cache};" \ + "name=device,size=8M,uuid=${uuid_gpt_device};" \ + "name=misc,size=4M,uuid=${uuid_gpt_misc};" \ + "name=datafooter,size=2M,uuid=${uuid_gpt_datafooter};" \ + "name=metadata,size=2M,uuid=${uuid_gpt_metadata};" \ + "name=persistdata,size=2M,uuid=${uuid_gpt_persistdata};" \ + "name=userdata,size=128M,uuid=${uuid_gpt_userdata};" \ + "name=fbmisc,size=-,uuid=${uuid_gpt_fbmisc}\0" +#endif /* PARTS_DEFAULT */ + +#define EMMC_ANDROID_BOOTCMD \ + "android_args=androidboot.storage_type=emmc\0" \ + PARTS_DEFAULT \ + "android_fdt_addr=0x83700000\0" \ + "android_mmc_dev=0\0" \ + "m4binary=rpmsg_imu_freertos.elf\0" \ + "androidboot=ext4load mmc 0:a ${loadaddr} media/0/${m4binary}; "\ + "bootaux ${loadaddr}; " \ + "setenv loadaddr 0x88000000; " \ + "setenv bootm_boot_mode sec;" \ + "setenv bootargs androidboot.serialno=${serial#} " \ + "$android_args; " \ + "part start mmc ${android_mmc_dev} boot boot_start; " \ + "part size mmc ${android_mmc_dev} boot boot_size; " \ + "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \ + "part start mmc ${android_mmc_dev} environment env_start; " \ + "part size mmc ${android_mmc_dev} environment env_size; " \ + "mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \ + "bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 " + #define EMMC_BOOTCMD \ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \ "rootfstype=ext4 rootwait\0" \ @@ -63,7 +103,6 @@ "emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \ "emmcrootpart=2\0" - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ @@ -125,7 +164,8 @@ "setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;" #define MODULE_EXTRA_ENV_SETTINGS \ "variant=-emmc\0" \ - EMMC_BOOTCMD + EMMC_BOOTCMD \ + EMMC_ANDROID_BOOTCMD #endif #if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index ccdac0abec..2dab17afab 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -19,14 +19,6 @@ #endif /* -* Disable DM_* for SPL build and can be re-enabled after adding -* DM support in SPL -*/ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_I2C -#undef CONFIG_DM_I2C_COMPAT -#endif -/* * SoC Configuration */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH @@ -268,12 +260,8 @@ #endif /* USB Configs */ -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm" #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3b1d0a99a1..7d2e573846 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -48,14 +48,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* MMC Configs */ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/display5.h b/include/configs/display5.h index 8829cbad91..1d3334ff12 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -55,11 +55,8 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) -/*#define CONFIG_MXC_UART*/ #define CONFIG_MXC_UART_BASE UART5_BASE -/* SPI NOR Flash */ - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC @@ -358,8 +355,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Commands */ - /* Watchdog */ #define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 9c8141de2e..7ec6e691c7 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -26,9 +26,9 @@ #endif #if (CONFIG_CONS_INDEX == 1) -#define CONSOLEDEV "ttyO0" +#define CONSOLEDEV "ttyS0" #elif (CONFIG_CONS_INDEX == 3) -#define CONSOLEDEV "ttyO2" +#define CONSOLEDEV "ttyS2" #endif #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 0481ed06a9..31214a6aa7 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -198,7 +198,6 @@ #define CONFIG_IMX_VIDEO_SKIP #define CONFIG_CMD_BMP -#define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 #define CONFIG_PCI diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h new file mode 100644 index 0000000000..5b35e22c85 --- /dev/null +++ b/include/configs/j721e_evm.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 J721E EVM + * + * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ + +#ifndef __CONFIG_J721E_EVM_H +#define __CONFIG_J721E_EVM_H + +#include <linux/sizes.h> +#include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h> + +#define CONFIG_ENV_SIZE (128 << 10) + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +/* SPL Loader Configuration */ +#ifdef CONFIG_TARGET_J721E_A72_EVM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000 +#else +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +#endif + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_CQSPI_REF_CLK 133333333 + +/* U-Boot general configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv fdtfile ${default_device_tree};" \ + "setenv overlay_files ${name_overlays}\0" \ + "loadaddr=0x80080000\0" \ + "fdtaddr=0x82000000\0" \ + "overlayaddr=0x83000000\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $overlay_files;" \ + "do;" \ + "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${overlayaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS \ + EXTRA_ENV_J721E_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#endif /* __CONFIG_J721E_EVM_H */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h new file mode 100644 index 0000000000..b011cb2a84 --- /dev/null +++ b/include/configs/ls1021atsn.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_DEEP_SLEEP + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + "board/freescale/ls1021atsn/ls102xa_pbi.cfg" +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_SECURE_BOOT */ + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw U-Boot image instead of FIT image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_BAUDRATE 115200 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* QSPI */ +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x80008000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x8f000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0x80008000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + BOOTENV \ + "boot_scripts=ls1021atsn_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "run scan_dev_for_extlinux; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo && mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* Environment */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif + +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ + +#endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index de0c9c7f26..31abee81ed 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -260,33 +260,7 @@ */ #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 +#define CONFIG_ETHPRIME "ethernet@2d10000" #endif /* PCIe */ @@ -444,7 +418,7 @@ #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt" #elif defined(CONFIG_SD_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 896d7a33b5..a6c7c3753d 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -194,4 +194,8 @@ #include <asm/fsl_secure_boot.h> #endif +/* Ethernet */ +/* smallest ENETC BD ring has 8 entries */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + #endif /* __L1028A_COMMON_H */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 7b68c1c0a1..e98dbfbb7e 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -242,4 +242,9 @@ "fi ; " \ "fi\0" +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG +#endif + #endif /* __M53MENLO_CONFIG_H__ */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index a1774c027a..667dac7340 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -65,13 +65,6 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } #define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } -/* MTD support */ - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - /* Ethernet Configuration */ #define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR @@ -85,6 +78,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "boot_os=yes\0" \ + "disable_giga=yes\0" \ "download_kernel=" \ "tftpboot ${kernel_addr} ${kernel_file};" \ "tftpboot ${fdt_addr} ${fdtfile};\0" \ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 2d6715cba2..d5b54dfa15 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -211,7 +211,6 @@ #define CONFIG_BCH /* Backlight Control */ -#define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66666000 #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 6b7104db5f..1fbd371a50 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -30,6 +30,10 @@ /* I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#ifdef CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 +#endif + /* Board NAND Info. */ #ifdef CONFIG_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 27e47327d3..3710a71ae9 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -53,7 +53,7 @@ /* USB Networking options */ -#define CONSOLEDEV "ttyO2" +#define CONSOLEDEV "ttyS2" #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 7007b5f6af..858b7a7da1 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -18,12 +18,12 @@ #define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ func(DHCP, dhcp, na) @@ -33,11 +33,15 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x80600000\0" \ - "fdt_addr_r=0x82200000\0" \ - "scriptaddr=0x82300000\0" \ - "pxefile_addr_r=0x82400000\0" \ - "ramdisk_addr_r=0x82500000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" + #endif /* __CONFIG_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index d4db9b4a56..33f06c00b1 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -83,7 +83,6 @@ #define CONFIG_IMX_THERMAL -#define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 #define CONFIG_ENV_OFFSET (8 * SZ_64K) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 8ceaa0c6c6..73541fe176 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -27,10 +27,23 @@ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ +/* When booting with FIT specify the node entry containing boot.scr */ +#if defined(CONFIG_FIT) +#define BOOT_SCR_STRING "source ${bootscriptaddr}:${bootscr_fitimage_name}\0" +#else +#define BOOT_SCR_STRING "source ${bootscriptaddr}\0" +#endif + +#ifndef CONFIG_OPTEE_LOAD_ADDR +#define CONFIG_OPTEE_LOAD_ADDR 0 +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ + "bootscr_fitimage_name=bootscr\0" \ "script_signed=boot.scr.imx-signed\0" \ + "bootscriptaddr=0x83200000\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "ethact=usb_ether\0" \ @@ -38,6 +51,7 @@ "initrd_high=0xffffffff\0" \ "fdt_file=imx7s-warp.dtb\0" \ "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \ + "fdtovaddr=0x83100000\0" \ "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -51,16 +65,16 @@ "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \ "do_bootscript_hab=" \ "if test ${hab_enabled} -eq 1; then " \ - "setexpr hab_ivt_addr ${loadaddr} - ${ivt_offset}; " \ + "setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset}; " \ "setenv script ${script_signed}; " \ "load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \ "run warp7_auth_or_fail; " \ "run bootscript; "\ "fi;\0" \ "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ + BOOT_SCR_STRING \ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index a67521cdc4..ce0cd38f56 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -35,4 +35,7 @@ #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h new file mode 100644 index 0000000000..8f2a7360b6 --- /dev/null +++ b/include/dt-bindings/soc/ti,sci_pm_domain.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H +#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H + +#define TI_SCI_PD_EXCLUSIVE 1 +#define TI_SCI_PD_SHARED 0 + +#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */ diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 54e9b2de4d..e55a4aec57 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -10,7 +10,7 @@ #define __TI_BOOT_H #ifndef CONSOLEDEV -#define CONSOLEDEV "ttyO2" +#define CONSOLEDEV "ttyS2" #endif #define VBMETA_PART_SIZE (64 * 1024) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h new file mode 100644 index 0000000000..43a25e9c6a --- /dev/null +++ b/include/linux/clk-provider.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> + */ +#ifndef __LINUX_CLK_PROVIDER_H +#define __LINUX_CLK_PROVIDER_H + +static inline void clk_dm(ulong id, struct clk *clk) +{ + if (!IS_ERR(clk)) + clk->id = id; +} + +/* + * flags used across common struct clk. these flags should only affect the + * top-level framework. custom flags for dealing with hardware specifics + * belong in struct clk_foo + * + * Please update clk_flags[] in drivers/clk/clk.c when making changes here! + */ +#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ +#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ +#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ +#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ + /* unused */ +#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ +#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ +#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ +#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ +#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ +#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ +#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ +/* parents need enable during gate/ungate, set rate and re-parent */ +#define CLK_OPS_PARENT_ENABLE BIT(12) +/* duty cycle call may be forwarded to the parent clock */ +#define CLK_DUTY_CYCLE_PARENT BIT(13) + +#define CLK_MUX_INDEX_ONE BIT(0) +#define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) +#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ +#define CLK_MUX_ROUND_CLOSEST BIT(4) + +struct clk_mux { + struct clk clk; + void __iomem *reg; + u32 *table; + u32 mask; + u8 shift; + u8 flags; + + /* + * Fields from struct clk_init_data - this struct has been + * omitted to avoid too deep level of CCF for bootloader + */ + const char * const *parent_names; + u8 num_parents; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_mux_val; +#endif + +}; + +#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk) + +struct clk_div_table { + unsigned int val; + unsigned int div; +}; + +struct clk_divider { + struct clk clk; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_divider_val; +#endif +}; + +#define clk_div_mask(width) ((1 << (width)) - 1) +#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk) + +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) +#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define CLK_DIVIDER_READ_ONLY BIT(5) +#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) + +struct clk_fixed_factor { + struct clk clk; + unsigned int mult; + unsigned int div; +}; + +#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\ + clk) + +int clk_register(struct clk *clk, const char *drv_name, const char *name, + const char *parent_name); + +struct clk *clk_register_fixed_factor(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); + +struct clk *clk_register_divider(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags); + +struct clk *clk_register_mux(struct device *dev, const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags); + +const char *clk_hw_get_name(const struct clk *hw); +ulong clk_generic_get_rate(struct clk *clk); + +static inline struct clk *dev_get_clk_ptr(struct udevice *dev) +{ + return (struct clk *)dev_get_uclass_priv(dev); +} +#endif /* __LINUX_CLK_PROVIDER_H */ diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index c57802f293..1cba8d9b79 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -105,6 +105,9 @@ struct ti_sci_board_ops { * -reset_state: pointer to u32 which will retrieve resets * Returns 0 for successful request, else returns * corresponding error message. + * @release_exclusive_devices: Command to release all the exclusive devices + * attached to this host. This should be used very carefully + * and only at the end of execution of your software. * * NOTE: for all these functions, the following parameters are generic in * nature: @@ -117,7 +120,10 @@ struct ti_sci_board_ops { */ struct ti_sci_dev_ops { int (*get_device)(const struct ti_sci_handle *handle, u32 id); + int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id); int (*idle_device)(const struct ti_sci_handle *handle, u32 id); + int (*idle_device_exclusive)(const struct ti_sci_handle *handle, + u32 id); int (*put_device)(const struct ti_sci_handle *handle, u32 id); int (*is_valid)(const struct ti_sci_handle *handle, u32 id); int (*get_context_loss_count)(const struct ti_sci_handle *handle, @@ -134,6 +140,7 @@ struct ti_sci_dev_ops { u32 reset_state); int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id, u32 *reset_state); + int (*release_exclusive_devices)(const struct ti_sci_handle *handle); }; /** @@ -263,6 +270,8 @@ struct ti_sci_core_ops { * @set_proc_boot_ctrl: Setup limited control flags in specific cases. * @proc_auth_boot_image: * @get_proc_boot_status: Get the state of physical processor + * @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a + * response. * * NOTE: for all these functions, the following parameters are generic in * nature: @@ -284,6 +293,8 @@ struct ti_sci_proc_ops { int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid, u64 *bv, u32 *cfg_flags, u32 *ctrl_flags, u32 *sts_flags); + int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle, + u8 pid); }; #define TI_SCI_RING_MODE_RING (0) diff --git a/include/mxs_nand.h b/include/mxs_nand.h new file mode 100644 index 0000000000..4bd65cded9 --- /dev/null +++ b/include/mxs_nand.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NXP GPMI NAND flash driver + * + * Copyright (C) 2018 Toradex + * Authors: + * Stefan Agner <stefan.agner@toradex.com> + */ + +#include <linux/mtd/mtd.h> +#include <asm/cache.h> +#include <nand.h> +#include <asm/mach-imx/dma.h> + +/** + * @gf_len: The length of Galois Field. (e.g., 13 or 14) + * @ecc_strength: A number that describes the strength of the ECC + * algorithm. + * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note + * the first chunk in the page includes both data and + * metadata, so it's a bit larger than this value. + * @ecc_chunk_count: The number of ECC chunks in the page, + * @block_mark_byte_offset: The byte offset in the ECC-based page view at + * which the underlying physical block mark appears. + * @block_mark_bit_offset: The bit offset into the ECC-based page view at + * which the underlying physical block mark appears. + */ +struct bch_geometry { + unsigned int gf_len; + unsigned int ecc_strength; + unsigned int ecc_chunk_size; + unsigned int ecc_chunk_count; + unsigned int block_mark_byte_offset; + unsigned int block_mark_bit_offset; +}; + +struct mxs_nand_info { + struct nand_chip chip; + struct udevice *dev; + unsigned int max_ecc_strength_supported; + bool use_minimum_ecc; + int cur_chip; + + uint32_t cmd_queue_len; + uint32_t data_buf_size; + struct bch_geometry bch_geometry; + + uint8_t *cmd_buf; + uint8_t *data_buf; + uint8_t *oob_buf; + + uint8_t marking_block_bad; + uint8_t raw_oob_mode; + + struct mxs_gpmi_regs *gpmi_regs; + struct mxs_bch_regs *bch_regs; + + /* Functions with altered behaviour */ + int (*hooked_read_oob)(struct mtd_info *mtd, + loff_t from, struct mtd_oob_ops *ops); + int (*hooked_write_oob)(struct mtd_info *mtd, + loff_t to, struct mtd_oob_ops *ops); + int (*hooked_block_markbad)(struct mtd_info *mtd, + loff_t ofs); + + /* DMA descriptors */ + struct mxs_dma_desc **desc; + uint32_t desc_index; +}; + +int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); +int mxs_nand_init_spl(struct nand_chip *nand); +int mxs_nand_setup_ecc(struct mtd_info *mtd); diff --git a/include/netdev.h b/include/netdev.h index 0a1a3a2d8d..a40c4adaad 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -30,7 +30,6 @@ int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); int bfin_EMAC_initialize(bd_t *bis); int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); -int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); diff --git a/include/power-domain.h b/include/power-domain.h index 07370709fe..ef15dc9f60 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -55,23 +55,12 @@ struct udevice; * * @dev: The device which implements the power domain. * @id: The power domain ID within the provider. - * - * Currently, the power domain API assumes that a single integer ID is enough - * to identify and configure any power domain for any power domain provider. If - * this assumption becomes invalid in the future, the struct could be expanded - * to either (a) add more fields to allow power domain providers to store - * additional information, or (b) replace the id field with an opaque pointer, - * which the provider would dynamically allocate during its .of_xlate op, and - * process during is .request op. This may require the addition of an extra op - * to clean up the allocation. + * @priv: Private data corresponding to each power domain. */ struct power_domain { struct udevice *dev; - /* - * Written by of_xlate. We assume a single id is enough for now. In the - * future, we might add more fields here. - */ unsigned long id; + void *priv; }; /** diff --git a/include/power/bd71837.h b/include/power/bd71837.h index 38c69b2b90..75e07e1de3 100644 --- a/include/power/bd71837.h +++ b/include/power/bd71837.h @@ -1,62 +1,103 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2018 ROHM Semiconductors */ -#ifndef BD71837_H_ -#define BD71837_H_ +#ifndef BD718XX_H_ +#define BD718XX_H_ -#define BD71837_REGULATOR_DRIVER "bd71837_regulator" +#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator" enum { - BD71837_REV = 0x00, - BD71837_SWRESET = 0x01, - BD71837_I2C_DEV = 0x02, - BD71837_PWRCTRL0 = 0x03, - BD71837_PWRCTRL1 = 0x04, - BD71837_BUCK1_CTRL = 0x05, - BD71837_BUCK2_CTRL = 0x06, - BD71837_BUCK3_CTRL = 0x07, - BD71837_BUCK4_CTRL = 0x08, - BD71837_BUCK5_CTRL = 0x09, - BD71837_BUCK6_CTRL = 0x0a, - BD71837_BUCK7_CTRL = 0x0b, - BD71837_BUCK8_CTRL = 0x0c, - BD71837_BUCK1_VOLT_RUN = 0x0d, - BD71837_BUCK1_VOLT_IDLE = 0x0e, - BD71837_BUCK1_VOLT_SUSP = 0x0f, - BD71837_BUCK2_VOLT_RUN = 0x10, - BD71837_BUCK2_VOLT_IDLE = 0x11, - BD71837_BUCK3_VOLT_RUN = 0x12, - BD71837_BUCK4_VOLT_RUN = 0x13, - BD71837_BUCK5_VOLT = 0x14, - BD71837_BUCK6_VOLT = 0x15, - BD71837_BUCK7_VOLT = 0x16, - BD71837_BUCK8_VOLT = 0x17, - BD71837_LDO1_VOLT = 0x18, - BD71837_LDO2_VOLT = 0x19, - BD71837_LDO3_VOLT = 0x1a, - BD71837_LDO4_VOLT = 0x1b, - BD71837_LDO5_VOLT = 0x1c, - BD71837_LDO6_VOLT = 0x1d, - BD71837_LDO7_VOLT = 0x1e, - BD71837_TRANS_COND0 = 0x1f, - BD71837_TRANS_COND1 = 0x20, - BD71837_VRFAULTEN = 0x21, - BD71837_MVRFLTMASK0 = 0x22, - BD71837_MVRFLTMASK1 = 0x23, - BD71837_MVRFLTMASK2 = 0x24, - BD71837_RCVCFG = 0x25, - BD71837_RCVNUM = 0x26, - BD71837_PWRONCONFIG0 = 0x27, - BD71837_PWRONCONFIG1 = 0x28, - BD71837_RESETSRC = 0x29, - BD71837_MIRQ = 0x2a, - BD71837_IRQ = 0x2b, - BD71837_IN_MON = 0x2c, - BD71837_POW_STATE = 0x2d, - BD71837_OUT32K = 0x2e, - BD71837_REGLOCK = 0x2f, - BD71837_MUXSW_EN = 0x30, - BD71837_REG_NUM, + ROHM_CHIP_TYPE_BD71837 = 0, + ROHM_CHIP_TYPE_BD71847, + ROHM_CHIP_TYPE_BD70528, + ROHM_CHIP_TYPE_AMOUNT }; +enum { + BD718XX_REV = 0x00, + BD718XX_SWRESET = 0x01, + BD718XX_I2C_DEV = 0x02, + BD718XX_PWRCTRL0 = 0x03, + BD718XX_PWRCTRL1 = 0x04, + BD718XX_BUCK1_CTRL = 0x05, + BD718XX_BUCK2_CTRL = 0x06, + BD71837_BUCK3_CTRL = 0x07, + BD71837_BUCK4_CTRL = 0x08, + BD718XX_1ST_NODVS_BUCK_CTRL = 0x09, + BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a, + BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b, + BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c, + BD718XX_BUCK1_VOLT_RUN = 0x0d, + BD718XX_BUCK1_VOLT_IDLE = 0x0e, + BD718XX_BUCK1_VOLT_SUSP = 0x0f, + BD718XX_BUCK2_VOLT_RUN = 0x10, + BD718XX_BUCK2_VOLT_IDLE = 0x11, + BD71837_BUCK3_VOLT_RUN = 0x12, + BD71837_BUCK4_VOLT_RUN = 0x13, + BD718XX_1ST_NODVS_BUCK_VOLT = 0x14, + BD718XX_2ND_NODVS_BUCK_VOLT = 0x15, + BD718XX_3RD_NODVS_BUCK_VOLT = 0x16, + BD718XX_4TH_NODVS_BUCK_VOLT = 0x17, + BD718XX_LDO1_VOLT = 0x18, + BD718XX_LDO2_VOLT = 0x19, + BD718XX_LDO3_VOLT = 0x1a, + BD718XX_LDO4_VOLT = 0x1b, + BD718XX_LDO5_VOLT = 0x1c, + BD718XX_LDO6_VOLT = 0x1d, + BD71837_LDO7_VOLT = 0x1e, + BD718XX_TRANS_COND0 = 0x1f, + BD718XX_TRANS_COND1 = 0x20, + BD718XX_VRFAULTEN = 0x21, + BD718XX_MVRFLTMASK0 = 0x22, + BD718XX_MVRFLTMASK1 = 0x23, + BD718XX_MVRFLTMASK2 = 0x24, + BD718XX_RCVCFG = 0x25, + BD718XX_RCVNUM = 0x26, + BD718XX_PWRONCONFIG0 = 0x27, + BD718XX_PWRONCONFIG1 = 0x28, + BD718XX_RESETSRC = 0x29, + BD718XX_MIRQ = 0x2a, + BD718XX_IRQ = 0x2b, + BD718XX_IN_MON = 0x2c, + BD718XX_POW_STATE = 0x2d, + BD718XX_OUT32K = 0x2e, + BD718XX_REGLOCK = 0x2f, + BD718XX_MUXSW_EN = 0x30, + BD718XX_REG_OTPVER = 0xff, + BD718XX_MAX_REGISTER = 0x100, +}; + +#define BD718XX_REGLOCK_PWRSEQ 0x1 +#define BD718XX_REGLOCK_VREG 0x10 + +#define BD718XX_BUCK_EN 0x01 +#define BD718XX_LDO_EN 0x40 +#define BD718XX_BUCK_SEL 0x02 +#define BD718XX_LDO_SEL 0x80 + +#define DVS_BUCK_RUN_MASK 0x3f +#define BD718XX_1ST_NODVS_BUCK_MASK 0x07 +#define BD718XX_3RD_NODVS_BUCK_MASK 0x07 +#define BD718XX_4TH_NODVS_BUCK_MASK 0x3f + +#define BD71847_BUCK3_MASK 0x07 +#define BD71847_BUCK3_RANGE_MASK 0xc0 +#define BD71847_BUCK4_MASK 0x03 +#define BD71847_BUCK4_RANGE_MASK 0x40 + +#define BD71837_BUCK5_RANGE_MASK 0x80 +#define BD71837_BUCK6_MASK 0x03 + +#define BD718XX_LDO1_MASK 0x03 +#define BD718XX_LDO1_RANGE_MASK 0x20 +#define BD718XX_LDO2_MASK 0x20 +#define BD718XX_LDO3_MASK 0x0f +#define BD718XX_LDO4_MASK 0x0f +#define BD718XX_LDO6_MASK 0x0f + +#define BD71837_LDO5_MASK 0x0f +#define BD71847_LDO5_MASK 0x0f +#define BD71847_LDO5_RANGE_MASK 0x20 +#define BD71837_LDO7_MASK 0x0f + #endif diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h new file mode 100644 index 0000000000..37c9838f76 --- /dev/null +++ b/include/sandbox-clk.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#ifndef __SANDBOX_CLK_H__ +#define __SANDBOX_CLK_H__ + +#include <linux/clk-provider.h> + +enum { + SANDBOX_CLK_PLL2 = 1, + SANDBOX_CLK_PLL3, + SANDBOX_CLK_PLL3_60M, + SANDBOX_CLK_PLL3_80M, + SANDBOX_CLK_ECSPI_ROOT, + SANDBOX_CLK_ECSPI0, + SANDBOX_CLK_ECSPI1, + SANDBOX_CLK_USDHC1_SEL, + SANDBOX_CLK_USDHC2_SEL, +}; + +enum sandbox_pllv3_type { + SANDBOX_PLLV3_GENERIC, + SANDBOX_PLLV3_USB, +}; + +struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name, + const char *parent_name, void __iomem *base, + u32 div_mask); + +static inline struct clk *sandbox_clk_fixed_factor(const char *name, + const char *parent, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static inline struct clk *sandbox_clk_divider(const char *name, + const char *parent, + void __iomem *reg, u8 shift, + u8 width) +{ + return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, shift, width, 0); +} + +struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 cgr_val, u8 clk_gate_flags); + +static inline struct clk *sandbox_clk_gate2(const char *name, + const char *parent, + void __iomem *reg, u8 shift) +{ + return sandbox_clk_register_gate2(NULL, name, parent, + CLK_SET_RATE_PARENT, reg, shift, + 0x3, 0); +} + +static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, + const char * const *parents, + int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0); +} + +#endif /* __SANDBOX_CLK_H__ */ diff --git a/include/tsec.h b/include/tsec.h index e90095121b..b17fa957df 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -17,6 +17,8 @@ #include <config.h> #include <phy.h> +#define TSEC_MDIO_REGS_OFFSET 0x520 + #ifndef CONFIG_DM_ETH #ifdef CONFIG_ARCH_LS1021A @@ -27,7 +29,7 @@ #define TSEC_MDIO_OFFSET 0x01000 #endif -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET) #define TSEC_GET_REGS(num, offset) \ (struct tsec __iomem *)\ diff --git a/include/wdt.h b/include/wdt.h index aa77d3e9b4..5bcff24ab3 100644 --- a/include/wdt.h +++ b/include/wdt.h @@ -106,7 +106,7 @@ struct wdt_ops { int (*expire_now)(struct udevice *dev, ulong flags); }; -#if defined(CONFIG_WDT) +#if CONFIG_IS_ENABLED(WDT) #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS #define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000) #endif |