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2018-12-07configs: am335x_hs_evm_uart: Add YMODEM SPL support for UART bootAndrew F. Davis
UART booting requires YMODEM support. Add this here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07ARM: at91: lds: add test for SPL binary size and bss sizeEugen.Hristev@microchip.com
Add test for the SPL binary size and the bss section size. This will throw an error at build time if the SPL sections do not fit in the designated RAM area, thus avoiding oversizing the SPL. Based on original work by Wenyou Yang. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-12-07pinctrl: meson: axg: Fix GPIO pin offsetsCarlo Caione
The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-06pinctrl: stm32: make pinctrl use hwspinlockBenjamin Gaignard
Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06hwspinlock: add stm32 hardware spinlock supportBenjamin Gaignard
Implement hardware spinlock support for STM32MP1. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06clk: stm32: add hardware spinlock clockBenjamin Gaignard
Add hardware spinlock in the list of the clocks. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06dm: Add Hardware Spinlock classBenjamin Gaignard
This is uclass for Hardware Spinlocks. It implements two mandatory operations: lock and unlock and one optional relax operation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06board: ti: ks2_evm: Over ride spl_get_load_buffer functionKeerthy
Currently k2 spi boot is broken as the image header is getting copied to an invalid memory location CONFIG_SYS_TEXT_BASE - sizeof (struct image_size) which maps to 0xc000000 - 0x40 = 0xbffffc0 being a reserved location. We cannot change the CONFIG_SYS_TEXT_BASE address as the single stage boots like UART boot will need the address to be 0xc000000 hence override the spl_get_load_buffer to have image_header address as CONFIG_SYS_TEXT_BASE aka 0xc000000 Signed-off-by: Keerthy <j-keerthy@ti.com>
2018-12-06clk: Allow clock defaults to be set during re-reloc state for SPL onlyPhilipp Tomsich
In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") the earlier guard against setting clock defaults in pre-reloc state was removed. While it is easy to filter 'assigned-clocks' properties for SPL using CONFIG_OF_SPL_REMOVE_PROPS, no such mechanism exists for the pre-reloc stage of the full U-Boot. With the default defconfig for the RK3399-Q7 (which filter the 'assigned-clocks' property for the DTS used by SPL anyway), this caused a pause during startup of the full U-Boot stage that lasted for almost 10s (due to the CPU not having been clocked up yet). This reintroduces the guard from commit f4fcba5c5baa ("clk: Allow clock defaults to be set also during re-reloc state") and extends it to only apply outside of a TPL/SPL build: i.e. clk_set_defaults will now run in pre-reloc state for SPL, but only after reloc for the full U-Boot. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") References: commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06fs: fix FAT name extractionPatrick Wildt
The long name apparently can be accumulated using multiple 13-byte slots. Unfortunately we never checked how many we can actually fit in the buffer we are reading to. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2018-12-06fs: check FAT cluster sizePatrick Wildt
The cluster size specifies how many sectors make up a cluster. A cluster size of zero makes no sense, as it would mean that the cluster is made up of no sectors. This will later lead into a division by zero in sect_to_clust(), so better take care of that early. The MAX_CLUSTSIZE define can reduced using a define to make some room in low-memory system. Unfortunately if the code reads a filesystem with a bigger cluster size it will overflow the buffer. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2018-12-06configs: stm32f746-disco: Fix stm32f746-disco bootPatrice Chotard
Since commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops") stm32f746-disco can't boot. This is due to new memory allocation into STM32 pinctrl driver, increase SYS_MALLOC_F_LEN from 0xC00 to 0xE00. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06main: Drop more #ifdefsSimon Glass
Now that many things are converted to Kconfig we can drop most of the Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06board/freescale/vid: Add vdd table for NXP LX2160A SoCPriyanka Jain
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: lsch3: Add support of serdes3 modulePriyanka Jain
Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06board/freescale/vid: Add correction for ltc3882 read error.Priyanka Jain
Voltage regulator LTC3882 device has 0.5% voltage read error. So for NXP SoC devices this generally equates to 2mV Update set_voltage_to_LTC for below: 1.Add coorection of upto 2mV in voltage comparison to take care of voltage read error of voltage regulator 2.Add loop max count kept as 100 to avoid infinte loop. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06ls1088a: Move CONFIG_FSL_QSPI to defconfigAshish Kumar
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1088ardb_pb: Add support for board detectionPramod Kumar
ls1088ardb-pb and ls1088ardb both boards are ls1088a based soc, board type detection is dynamic at boot time Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06arm: ls1021a: Add timer_init() in board_init_f for SPLAlison Wang
I2C is used to access DDR SPD in the DDR initialization for SPL. In i2c_write process, get_timer() will be called. In board_init_f for SPL, timer_init() is not called before. The system counter is not enabled and the counter frequency is not set to 12.5MHz in SPL. The parameters for do_div() are zero too. It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its own set of libgcc functions. As the parameters for do_div() are zero, __div0 will be called. Then the processor will stay in an endless loop after calling hang(). This patch will add timer_init() in board_init_f for SPL and fix a series of issues it caused. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06arm64: ls2080a: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> [YS: moveconfig -s -d] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls2080a: add sata node supportPeng Ma
One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06scsi: ceva: add ls2080a soc supportPeng Ma
Add ahci compatible support for ls2080a soc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Acked-by: Michal Simek <michal.simek@xilinx.com> [YS: add fallthrough comment] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06arm64: ls1088a: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> [YS: moveconfig.py -s -d] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls1088a: add sata node supportPeng Ma
One ls1088a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06scsi: ceva: add ls1088a soc supportPeng Ma
Add ahci compatible support for ls1088a soc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06arm64: ls1046aqds: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> [YS: moveconfig.py -s -d] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06arm64: ls1046ardb: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> [YS: moveconfig.py -s -d] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls1046a: add sata node supportPeng Ma
One ls1046a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06scsi: ceva: add ls1046a soc supportPeng Ma
Add ahci compatible support for ls1046a soc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1012afrx: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1012a2g5rdb/ls1012afrdm/ls1012afrwy_tfa_defconfig to be loaded by trusted firmware - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1012aqds: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1012aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1012aqds: fix secure boot compilationRajesh Bhagat
Includes environment.h file in ls1012aqds.c Also, enables pfe validation Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1012ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1012ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT - enable PFE validation for secure boot Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1043aqds: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1043aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1043ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1043ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN and QE address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1046aqds: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1046aqds_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: ls1046ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls1046ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - FMAN address changes for TFABOOT - define BOOTCOMMAND for TFABOOT Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06armv8: fsl-layerscape: add support of MC framework for TFAPankit Garg
Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06drivers: qe: add TFABOOT supportRajesh Bhagat
Adds TFABOOT support and allows to pick QE firmware on basis of boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: remove line continuation in quoted string] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06net: fm: add TFABOOT supportRajesh Bhagat
Adds TFABOOT support and allows to pick FMAN firmware on basis of boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: return job ring status as true in TFABOOTPankit Garg
Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: change el2_to_aarch32 SMC IDRajesh Bhagat
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: Update parsing boot sourceYork Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: skip OCRAM init for TFABOOTRajesh Bhagat
OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: add SMC calls for DDR size and bank infoRajesh Bhagat
Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: bootcmd identification for TFABOOTPankit Garg
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: remove EL3 specific erratas for TFABOOTRajesh Bhagat
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: identify boot source from PORSR registerRajesh Bhagat
PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit (git 2.34.1) at 2025-02-23 15:59:38 +0000