summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-09-25ata: ahci: Don't cap AHCI port count under CONFIG_DM_SCSITuomas Tynkkynen
When using device model this sort of hardcoded limits aren't used or necessary. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-25ata: ahci: Loop over the actual number of ports, not the maximumTuomas Tynkkynen
The loop in ahci_start_ports() is looping over the maximum number of SCSI devices in the system, which can be larger than the amount of ports a particular AHCI controller has. The extra looping isn't directly harmful because the link_port_map bitmap won't have the bit set for a nonexistent port, but it is wasteful. Replace the loop limit with the port count of the AHCI controller instead. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-25xtensa: use asm-generic/atomic.hChris Packham
Make use of asm-generic/atomic.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-25mips: use asm-generic/atomic.hChris Packham
Make use of asm-generic/atomic.h. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-09-25ARM: use asm-generic/atomic.hChris Packham
Make use of asm-generic/atomic.h retaining the smp_mb_... definitions. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25Add include/asm-generic/atomic.hChris Packham
The arm, xtensa and mips version of atomic.h were already very similar (the mips one was a copy of xtensa). Combine these implementations together to produce a generic atomic.h that can be included by these architectures (and any others that need it in future). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25cmd: add conitrace commandHeinrich Schuchardt
The 'conitrace' command prints the codes received from the console input as hexadecimal numbers. This developer utility is useful for testing the handling of special keys by keyboard drivers. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-09-25mmc: omap_hsmmc: Fix pbias for omap3_logic to enable CD pinAdam Ford
The MMC card detect pin is connected to gpio127 on omap3_logic. When setting up the pbias register for MMC, let's also enable gpio_127 for the card detect. As part of the package deal, gpio_126 and gpio_129 are also enabled. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-25dm: Update README.txt to clarify device tree usageTom Rini
In the section about Device Trees add a paragraph at the end that clarifies how we decide of a tree is valid or not. We say that all bindings must either be in the specification (link provided) or in our device-tree-bindings directory. We say that most of these come from the Linux Kernel and as such some design decisions are made for us already, but that in most cases we wish to retain compatibility. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-25arm: spear: fix enabling of SSP2 clockQuentin Schulz
The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike the current 0x70 which enables the clock of UART2, SSP1 and SSP2. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Stefan Roese <sr@denx.de>
2018-09-25arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is builtQuentin Schulz
SPI controllers SSP1, 2 and 3 require to enable their respective clocks. Let's enable them only when the SPI controller driver is built. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-25spi: add support for ARM PL022 SPI controllerQuentin Schulz
This adds support for the ARM PL022 SPI controller for the standard variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX FIFO. A few parts were borrowed from the Linux kernel driver. Cc: Armando Visconti <armando.visconti@st.com> Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-25configs: am335x_evm: enable OF_BOARD_SETUPSekhar Nori
Enable CONFIG_OF_BOARD_SETUP as it is needed for Beaglebone black to overwrite the Ethernet phy address present in DT in case the phy latches on to a different address. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25board: ti: am335x: add support to fixup phy addressSekhar Nori
On beaglebone black, it can so happen that PHY address is not latched correctly on reset and board boots with PHY responding to a different address than that programmed in device-tree. For example, see this report: https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J Workaround this by fixing up device-tree passed to kernel by using the PHY address detected in hardware. Beaglebone itself uses only one ethernet port and its DT currently uses phy_id (obsoleted). But the function has been written to handle multiple ports and phy_id as well as phy-handle to make the function more generically useful. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25drivers: net: cpsw: add support to update phy addressSekhar Nori
On some boards using TI CPSW, it may be possible that PHY address was not latched correctly, and the actual address that the phy responds on is different from that set in device-tree. For example, see this problem report on beaglebone black: https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J Add support to check for this condition and use the detected phy address when its safe to do so. Also, add a public API that exposes the phy address of a given slave. This can be used to update device-tree that is passed to Linux kernel. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25configs: sama5d27_som1_ek: Add defconfig for ENV/boot from uSDCodrin Ciubotariu
This adds a defconfig for sama5d27_som1_ek board to get environment from uSD. The defconfig is made from sama5d27_som1_ek_mmc_defconfig, with 'bootcmd' and 'bootargs' changed to kernel, device-tree and rootfs from uSD. The environment is expected to be found in uSD's FAT partition. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
2018-09-25configs: sama5d27_som1_ek: Set CONFIG_BOOTARGS using KconfigCodrin Ciubotariu
CONFIG_BOOTARGS can be set using Kconfig, so we no longer need it in the config files. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
2018-09-25configs: sama5d27_som1_ek: Remove unnecessary FAT_ENV_xxx macrosCodrin Ciubotariu
FAT_ENV_xxx options can now be set using Kconfig, so we no longer need them in the config files. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
2018-09-25configs: sama5d2_xplained: Add defconfig for ENV/boot from eMMCCodrin Ciubotariu
This adds a defconfig for sama5d2_xplained board to get environment from eMMC. The defconfig is made from sama5d2_xplained_mmc_defconfig, with 'bootcmd' and 'bootargs' changed to kernel, device-tree and rootfs from eMMC. The environment is expected to be found in eMMC's FAT partition. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
2018-09-25spl: Weed out CONFIG_SYS_TEXT_BASE usageMarek Vasut
The SPL loaders assume that the CONFIG_SYS_TEXT_BASE memory location is available and can be corrupted by loading ie. uImage or fitImage headers there. Sometimes it could be beneficial to load the headers elsewhere, ie. if CONFIG_SYS_TEXT_BASE is not yet writable while we still want to parse the image headers in some local onchip memory to ie. extract firmware from that image. Add the possibility to override the location where the headers get loaded by introducing new function, spl_get_load_buffer() which takes two arguments -- offset from the CONFIG_SYS_TEXT_BASE and size of the data that are to be loaded there -- and returns a valid buffer address or hangs the system. The default behavior is the same as before, add the offset to CONFIG_SYS_TEXT_BASE and return that address. User can override the weak spl_get_load_buffer() function though. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-09-25board: st: stm32mp1: Add usb gadget supportPatrice Chotard
Enable USB gadget support using DWC2 driver Populate board_usb_init() to initialize clocks, phy, reset and data needed for DWC2 IP. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-25configs: stm32mp15: Enable USB relative flagsPatrice Chotard
Enable config USB relative flags in order to enable USB EHCI, DWC2 gadget, download and mass_storage support. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-25ARM: dts: stm32mp1: Add EHCI support for stm32mp157c-ev1 boardPatrice Chotard
Add DT nodes to enable EHCI support Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-25ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 boardPatrice Chotard
Add DT nodes to enable DWC2 gadget support Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-23Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2018-09-23mips: mt7628a.dtsi: Add SPI clock-frequency propertyStefan Roese
This patch adds the clock-frequency property to the SPI controller DT node. It will be used by the SPI driver to calculate the baud rate. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23mips: mt76xx: Add sysreset supportStefan Roese
This patch adds the necessary sysreset DT node and enables the required drivers via Kconfig. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23mips: Add Gardena Smart-Gateway board supportStefan Roese
The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23mips: Add LinkIt Smart 7688 supportStefan Roese
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22mips: Add basic MediaTek MT7620/88 supportStefan Roese
This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git The mt7628a.dtsi file is imported from Linux v4.17. Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22mips: Add arch/mips/include/asm/atomic.hStefan Roese
This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODEDaniel Schwierzeck
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: cache: make index base address configurableDaniel Schwierzeck
The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: cache: optimise changing of k0 CCA modeDaniel Schwierzeck
Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: cache: reimplement dcache_[status, enable, disable]Daniel Schwierzeck
Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22MIPS: start.S: make boot config at offset 0x10 configurableDaniel Schwierzeck
Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22bcm968380gerg: enable pinctrlPhilippe Reynes
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-22dt: bcm6838: add pinctrlPhilippe Reynes
Add pinctrl node and related syscon node for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-22pinctrl: bcm6838: add pinctrl supportPhilippe Reynes
Add pinctrl support for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-19Merge git://git.denx.de/u-boot-imxTom Rini
- changes in pico-* boards - fix imx6ull pinmux
2018-09-19Merge git://git.denx.de/u-boot-marvellTom Rini
- Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards
2018-09-19arm: mvebu: clearfog: enable eMMC boot partitions supportBaruch Siach
The Clearfog SOM can optionally have eMMC installed. Enable support for eMMC boot partitions by default. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19phy: marvell: add SATA comphy RX/TX polarity invert supportRabeeh Khoury
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: cmd: mvebu: Exclude mvebu commands from SPL buildsKonstantin Porotchkin
Exclude mvebu commands from SPL builds Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: mvebu: Add SPI parameters for environment setupKonstantin Porotchkin
Add definitions for CONFIG_ENV_SPI_BUS and CONFIG_ENV_SPI_CS to Armada-388-GP board configuration Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: env: Fix the SPI flash device setup for DM modeKonstantin Porotchkin
For some reason the spi_flash_probe_bus_cs() is called inside the setup_flash_device() with zero values in place of configurated SPI flash mode and maximum flash speed. This code causes HALT error during startup environment relocation on some platforms - namely Armada-38x-GP board. Fix the function call by replacing zeros with the appropriate values - CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: nand: pxa3xx: Add WA for eliminating flash ready timeoutDavid Sniatkiwicz
add delay before processing the status flags in pxa3xx_nand_irq(). Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> c: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NANDKonstantin Porotchkin
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: cosmetic: add comments to the timing layout structuresKonstantin Porotchkin
Add comments with timing parameter names and some details about nand layout fileds. Remove unneeded definition. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: nand: Replace hardcoded page chunk size with calculated oneKonstantin Porotchkin
Replace the hardcoded value of page chink with value that depends on flash page size and ECC strength. This fixes nand access errors for 2K page flashes with 8-bit ECC. Move the initial flash commannd function assignment past the ECC structures initialization for eliminating usage of hardcoded page chunk size value. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit (git 2.34.1) at 2024-12-24 19:57:18 +0000