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2014-12-16arm: socfpga: board: Repair Micrel PHY tuningPavel Machek
Add proper error checking into the PHY tuning patch. Make the PHY tunning only happen in case the KSZ9021 PHY is enabled in config. Call the config callback after the tuning finished. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
2014-12-06socfpga: correctly increment freeze_controller_base addressDinh Nguyen
Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2014-12-06socfpga: add missing struct member fifo_triple_byteDinh Nguyen
socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2014-12-06arm: socfpga: DW_SPI: Remove clock info from config headerStefan Roese
Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06spi: designware_spi: Some fixes / changesStefan Roese
As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bitsStefan Roese
As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiersStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06arm: socfpga: Add Designware (DW) SPI support to config headerStefan Roese
Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-12-06arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probingStefan Roese
Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devicesStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06spi: Add designware master SPI DM driver used on SoCFPGAStefan Roese
This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06arm: socfpga: Add Cadence QSPI support to config headerStefan Roese
With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06arm: socfpga: dts: Add spi0 alias for Cadence QSPI driverStefan Roese
Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsiStefan Roese
This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06spi: Add Cadence QSPI DM driver used by SoCFPGAStefan Roese
This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06arm: socfpga: dts: Move to SPDX license identifiersStefan Roese
The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com>
2014-12-06arm: socfpga: set skew settings for ethernet phyDinh Nguyen
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
2014-12-06arm: socfpga: Add myself as maintainer for the SoCrates boardStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-04Merge branch 'sandbox' of git://git.denx.de/u-boot-x86Tom Rini
2014-12-03Revert "image-fdt: boot_get_fdt() return value when no DTB exists"Tom Rini
It has been found that this change breaks the case of an appended device tree file, so for the problem in question some other solution must be found. This reverts commit c6150aaf2f2745141a7c2ceded58d7efbfeace7d. Reported-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Reported-by: Pantelis Antoniou <panto@antoniou-consulting.com> Confirmed-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Tom Rini <trini@ti.com>
2014-12-01Merge git://git.denx.de/u-boot-fdtTom Rini
2014-12-01Merge git://git.denx.de/u-boot-x86Tom Rini
2014-12-01fs/ext4/ext4fs.c, fs/fs.c fs/fat/fat_write.c: Adjust 64bit math methodsTom Rini
The changes to introduce loff_t into filesize means that we need to do 64bit math on 32bit platforms. Make sure we use the right wrappers for these operations. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Suriyan Ramasami <suriyan.r@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Pierre Aubert <p.aubert@staubli.com>
2014-12-01fdt: Fix regression in fdt_pack_reg()Hans de Goede
After commit 933cdbb479: "fdt: Try to use fdt_address_cells()/fdt_size_cells()" I noticed that allwinner boards would no longer boot. Switching to fdt_address_cells / fdt_size_cells changes the result from bytes to 32 bit words, so when we increment pointers into the blob, we must do so by 32 bit words now. This commit makes allwinner boards boot again. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Vince Hsu <vinceh@nvidia.com>
2014-11-27Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2014-11-28ARM: UniPhier: move CONFIG_CMD_* and CONFIG_FIT* defines to defconfigMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28ARM: UniPhier: enable Device Tree controlMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28usb: UniPhier: support OF configurationMasahiro Yamada
If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
2014-11-28serial: UniPhier: support OF configurationMasahiro Yamada
This commit implements the ofdata_to_platdata handler for the UniPhier serial driver and adds serial device nodes to the device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28ARM: UniPhier: add device tree sourcesMasahiro Yamada
This commit adds basic device tree sources for UniPhier SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROLMasahiro Yamada
If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. Consequently, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. In the first place, GPIO has nothing to do with OF_CONTROL. It is wrong that lib/fdtdec.c includes GPIO functions; it should be split into two files, FDT-common things and GPIO things. It is, however, a pretty big work to fix that correctly. This is a compromised commit to add a dummy <asm/arch/gpio.h> to support OF_CONTROL for UniPhier platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2014-11-28ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=yMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-27fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada
The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-27Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2014-11-27MIPS: bootm: remove unused or redundant header filesDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: bootm: add missing initramfs relocationDaniel Schwierzeck
The initramfs is currently only relocated if the user calls the bootm ramdisk subcommand. If bootm should be used without subcommands, the arch-specific bootm code needs to implement the relocation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: remove board.cDaniel Schwierzeck
After all MIPS boards are switched to generic-board, the MIPS specific board.c can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: vct: switch to generic boardDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
2014-11-27MIPS: qemu_mips: switch to generic boardDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: pb1x00: switch to generic boardDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: dbau1x00: switch to generic boardDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27MIPS: fix setup of initial stack frameDaniel Schwierzeck
To get correct stack walking and backtrace functionality in gdb, registers fp and ra should be initialized before calling board_init_f or board_init_r. Thus allocating stack space and zeroing it as it is currently done in board.c becomes obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-26mtd: nand: s3c: Unify the register definition and namingMarek Vasut
Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Vladimir Zapolskiy <vz@mleia.com>
2014-11-26buildman: Don't default to -e when building current sourceSimon Glass
We probably don't need to enable this option by default. It is useful to display only failure boards (not errors) and it is easy to add -e if it is required. Also update the docs. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
2014-11-26buildman: Fix repeating board list with -lSimon Glass
Ensure that we don't print duplicate board names when -l is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
2014-11-26patman: Use the full commit hash for 'git checkout'Simon Glass
Even with the initial 8 characeters of the hash we will sometimes get a collision. Use the full hash. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-26buildman: Save *.img files tooTom Rini
When saving binary files we likely want to keep any .img files that have been generated as well. Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-26sandbox: Fix warnings in cpu.c and os.cSimon Glass
This fixes the following two problems: cppcheck reports: [arch/sandbox/cpu/start.c:132]: (error) Uninitialized variable: err [arch/sandbox/cpu/os.c:371]: (error) Memory leak: fname Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Denk <wd@denx.de>
2014-11-26sandbox: Fix warnings due to 64-bit printf() stringsSimon Glass
Now that we have inttypes.h, use it in a few more places to avoid compiler warnings on sandbox when building on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org>
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