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2018-07-16sf: add Gigadevice gd25q16c entryLudwig Zenz
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi_flash: add a bunch of winbond flashes to id-tableHannes Schmelzer
This commit adds the following flashes to the id-table - W25Q16JV - W25Q32JV - W25Q64JV - W25Q128JV - W25Q256JV Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boardsSiva Durga Prasad Paladugu
This patch adds qspi driver support for all ZynqMP ZCU102 boards. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: zynqmp_gqspi: Add support for ZynqMP qspi driverSiva Durga Prasad Paladugu
This patch adds qspi driver support for ZynqMP SoC. This driver is responsible for communicating with qspi flash devices. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> [jagan: removed GQSPI_MIO_NUM_ macros] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: convert to livetreeVipul Kumar
Update the xilinx spi driver to support a live tree. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Added support to read JEDEC-id twice at the boot timeVipul Kumar
This patch is for the startup block issue in the spi controller. SPI clock is passing through STARTUP block to FLASH. STARTUP block don't provide clock as soon as QSPI provides command. So, first command fails. This patch added support to read JEDEC id in xilinx_spi_xfer (). Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() functionVipul Kumar
This patch modify xilinx_spi_xfer() function and add rxfifo() and txfifo() functions to add the modularity so that these functions can be used by other functions within the same file. This patch also added support to read fifo_size from dts. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi: xilinx: Read reg base address from DTS fileMichal Simek
This patch added support to read register base address from DTS file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16configs: Bananapi_M2_Ultra: enable gigabit ethernetLothar Felten
Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40) Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16sunxi: R40: add gigabit ethernet devicetree nodeLothar Felten
Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins. Updated to match the Linux kernel's device tree. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: support R40 GMACLothar Felten
Add support for the GMAC found in the Allwinner R40/V40 SoC. The R40 GMAC interface is not controlled by the syscon register but has a separate configuration register in the CCU. The clock gate and reset bits are in a different register compared to the other SoCs supported by this driver. The driver uses the -gmac suffix for the R40 because the R40 also has a different 100 MBit MAC (EMAC). Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16net: sun8i-emac: set mux and clock by driver dataLothar Felten
Use driver data->variant information to select device specific pin mux and phy clock settings. Suggested by Jagan Teki Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16net: sun8i-emac: fix printing NULL characterLothar Felten
If the variant is not set and therefore NULL, do not attempt to print the variant. Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
2018-07-16sunxi: R40: add gigabit ethernet clocksLothar Felten
Add clock control entries for the gigabit interface of the Allwinner R40/V40 CPU Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2018-07-16dm: sunxi: Use DM for MMC and SATA on all A10 boardsAdam Sampson
Use the driver model for MMC and SATA, in preparation for CONFIG_BLK defaulting to y. Tested on A10 Cubieboard. Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2018-07-16dm: mmc: sunxi: Add A10/A20 compatible stringsAdam Sampson
Commit dd27918c2252 ("dm: mmc: sunxi: Add support for driver model") only added the allwinner,sun5i-a13-mmc compatible string for this driver. The DM initialisation code here also works with (at least) A10 and A20, so add the appropriate compatible strings as per Linux 4.17's driver. Tested on A10 Cubieboard and A20 pcDuino3 Nano with CONFIG_DM_MMC. (A20 worked already, because sun7i-a20.dtsi specifies both the A13 and A20 strings.) Signed-off-by: Adam Sampson <ats@offog.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2018-07-16sunxi: DT: A64: add proper SoPine baseboard device treeAndre Przywara
When the defconfig for the SoPine baseboard was added, there wasn't any proper DT for the board yet, so we used the Pine64 DT as a placeholder. Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use them in our defconfig. This is as of v4.18-rc3, exactly Linux commit: commit 7d556bfc49adddf2beb0d16c91945c3b8b783282 Author: Jagan Teki <jagannadh.teki@gmail.com> Date: Mon Dec 4 10:23:07 2017 +0530 arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: H3: update board .dts files from LinuxAndre Przywara
Update the .dts file for the various boards with an Allwinner H3 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 721afaa2aeb860067decdddadc84ed16f42f2048 (HEAD) Merge: 7c00e8ae041b 87815dda5593 Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Mon Jun 11 17:57:38 2018 -0700 Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc This also includes the OrangePi Zero .dts, which technically has an Allwinner H2+ SoC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: H5: update board .dts files from LinuxAndre Przywara
Update the .dts file for the various boards with an Allwinner H5 SoC. This is as of v4.18-rc3, exactly Linux commit: commit af5d05bdc99c211729cba0a3d5417bccfa308caf Author: Neil Armstrong <narmstrong@baylibre.com> Date: Tue Apr 24 13:47:14 2018 +0200 arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: update device tree files for Allwinner H3 and H5 SoCsAndre Przywara
Update the device tree files from the Linux tree as of v4.18-rc3, exactly Linux commit: commit 55c5ba5e49a0a124ed416880e8227b493474495e Author: Chen-Yu Tsai <wens@csie.org> Date: Tue Apr 24 19:34:22 2018 +0800 arm64: dts: allwinner: h5: Add cpu0 label for first cpu Since the H3 and H5 are very similar (aside from the actual ARM cores), they share most the SoC .dtsi and thus have to be updated together. One tiny change is the removal of the "arm/" prefix from the include path in the sun50i-h5.dtsi, which is needed because we don't share the same sophisticated DT directory layout of Linux. Also we need to fix up the board .dts files already, since the .dtsi removes some pins, so the .dts can't reference them anymore. This is to maintain bisectability. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: A64: update board .dts files from LinuxAndre Przywara
Update the .dts files for the various boards with an Allwinner A64 SoC. This is as of v4.18-rc3, exactly Linux commit: commit 818668055c9d588c9a9d151e3b258ed1adacba0b Author: Jagan Teki <jagan@amarulasolutions.com> Date: Mon Apr 23 12:02:39 2018 +0530 arm64: dts: allwinner: a64: bananapi-m64: add usb otg It updates the existing DT files, adds the newly added axp803.dtsi and removes our temporary kludge file to get Ethernet support in U-Boot. I left the amarula-relic alone, as this DT has not reached mainline yet. The changes are not critical anyway, and the next sync will fix this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-16sunxi: DT: A64: update device tree file for Allwinner A64 SoCAndre Przywara
Updates the device tree file from the the Linux tree as of v4.18-rc3, exactly Linux commit: commit c1cff65f9b16b31e731e2e75bbe06638c86e1996 Author: Harald Geyer <harald@ccbib.org> Date: Thu Mar 15 16:25:08 2018 +0000 arm64: dts: allwinner: a64: add simplefb for A64 SoC This also pulls in the newly required include files for the clock and reset bindings, also removes the now redundant part from our *-u-boot.dtsi overlay file. I kept the PWM node from U-Boot, as we recently gained this explicitly for U-Boot's own usage and I don't want to regress here. This node is in the queue for mainline Linux already, so the next sync will make it all equal again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-13mach-stm32: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESETLey Foon Tan
CONFIG_SPL_RESET_SUPPORT has been renamed to CONFIG_SPL_DM_RESET, update this Kconfig file. Fixes: bfc6bae8fa1f ("reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-13Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-12Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
2018-07-12arm: socfpga: Fixes: include <debug_uart.h>Ley Foon Tan
Fix compilation warning when enable CONFIG_DEBUG_UART. arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’: arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration] debug_uart_init(); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit onlyLey Foon Tan
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: dts: socfpga: stratix10: Fix memory nodeLey Foon Tan
Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini
2018-07-12lpi2c: Add bus busy error handlingYe Li
When doing "i2c dev 4; i2c probe" with ENET daughter card connected on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of lpi2c always show busy, but the master is idle, and stop is detected (SDF set). This patch addes a handling to re-init the lpi2c master for this case. Then the issue can be worked around. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12lpi2c: Fix bus stop problem in xferYe Li
In xfer function, both bus_i2c_read and bus_i2c_write will send a STOP command. This causes a problem when reading register data from i2c device. Generally two operations comprise the register data reading: 1. Write the register address to i2c device. START | chip_addr | W | ACK | register_addr | ACK | 2. Read the Data from i2c device. START | chip_addr | R | ACK | DATA | NACK | STOP The STOP command should happen at the end of the transfer, otherwise we will always get data from register address 0 Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12imx: lpi2c: fix clock issue when NACK detectedGao Pan
For LPI2C IP, NACK is detected by the rising edge of the ninth clock. In current uboot driver, once NACK is detected, it will reset and then disable LPI2C master. As a result, we can never see the falling edge of the ninth clock. Signed-off-by: Gao Pan <pandy.gao@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12imx_lpi2c: Update lpi2c driver to support imx8Ye Li
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory to u-boot include directory as a common header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-07-12ARM: socfpga: Assure correct ACTLR configurationMarek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ARM: socfpga: Make DRAM node available in SPLMarek Vasut
The SPL can also parse the DRAM configuration node to figure out the memory layout, make sure it is available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ARM: socfpga: Pull DRAM size from DTMarek Vasut
Pull the DRAM size from DT instead of hardcoding it into U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut
The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut
This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-12arm: socfpga: Add do_bridge_reset for Arria 10Ley Foon Tan
Add do_bridge_reset() function for Arria 10, it is required by misc.c. arch/arm/mach-socfpga/built-in.o: In function `do_bridge': arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset' make[1]: *** [u-boot] Error 1 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan
Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-07-12board: altera: stratix10: Add socdk board support for Stratix10 SoCLey Foon Tan
Add socdk board support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan
Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add timer support for Stratix10 SoCLey Foon Tan
Add timer support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add SPL driver for Stratix10 SoCLey Foon Tan
Add SPL driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: Restructure the SPL fileLey Foon Tan
Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: stratix10: Add MMU support for Stratix10 SoCLey Foon Tan
Add MMU memory mapping table for Stratix SoC. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add mailbox support for Stratix10 SoCLey Foon Tan
Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-07-12arm: socfpga: stratix10: Add misc support for Stratix10 SoCLey Foon Tan
Add misc support such as EMAC and cpu info printout for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12arm: socfpga: misc: Move bridge command to misc commonLey Foon Tan
Move bridge command to misc common driver, in preparation to used by other platforms. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-12spi: cadence_qspi: Fix warning cast from pointer to integer of different sizeLey Foon Tan
Use "%p" to print cmdbuf. Compilation warning as below: CC spl/drivers/spi/cadence_qspi_apb.o LD spl/lib/built-in.o drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’: drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] cmdlen, (unsigned int)cmdbuf); Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de>
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