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2020-04-01Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dmTom Rini
Vboot vulnerability fix
2020-04-01Merge tag 'u-boot-stm32-20200401' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix device tree of Avenger96 board from Arrow Electronics and add compatibility with stm32mp15_dhcom_basic_defconfig
2020-04-01test: vboot: Reduce fake kernel size to 500 bytesSimon Glass
We don't need 5KB to test things out. A smaller size makes it easier to look at the FIT with fdtdump. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01test: vboot: Move key creation into a functionSimon Glass
This code is repeated so move it into a function with a parameter. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Use constants for 'required' and 'key-name-hint'Simon Glass
These are used in multiple places so update them to use a shared #define. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-04-01test: vboot: Fix pylint errorsSimon Glass
Fix various minor things noticed by pylint. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01test: vboot: Tidy up the code a littleSimon Glass
Fix some long lines and comments. Use a distinct name for the 'required key' test. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01fit_check_sign: Allow selecting the configuration to verifySimon Glass
This tool always verifies the default configuration. It is useful to be able to verify a specific one. Add a command-line flag for this and plumb the logic through. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Load the correct configuration in fit_check_signSimon Glass
At present bootm_host_load_images() is passed the configuration that has been verified, but ignores it and just uses the default configuration. This may not be the same. Update this function to use the selected configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Check hash-nodes when checking configurationsSimon Glass
It is currently possible to use a different configuration's signature and thus bypass the configuration check. Make sure that the configuration node that was hashed matches the one being checked, to catch this problem. Also add a proper function comment to fit_config_check_sig() and make it static. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01test: vboot: Parameterise the testSimon Glass
This test is actually made up of five separate tests. Split them out so that they appear as separate tests. Unfortunately this restarts U-Boot multiple times which adds about a second to the already-long vboot test, about 8 seconds total on my machine. We could add a special 'teardown' test afterwards but if the tests are executed out of order that would not work. Changing test_vboot into a class causes it not to be discovered and makes it different from all other tests. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01test: vboot: Add a test for a forged configurationSimon Glass
Add a check to make sure that it is not possible to add a new configuration and use the hashed nodes and hash of another configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01test: vboot: Drop unnecessary parameter for fit_check_signSimon Glass
This tool only uses the last -k parameter provided. Drop the earlier one since it has no effect. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Return an error message from fit_config_verify_sig()Simon Glass
This function only returns an error message sometimes. Update it to always return an error message if one is available. This makes it easier to see what went wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Be a little more verbose when checking signaturesSimon Glass
It is useful to be a little more specific about what is being checked. Update a few messages to help with this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01image: Correct comment for fit_conf_get_node()Simon Glass
This should mention that conf_uname can be NULL and should be in the header file. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01ARM: dts: stm32: Repair PMIC configuration on AV96Marek Vasut
The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add missing ethernet PHY reset on AV96Marek Vasut
Add PHY reset GPIO on AV96 ethernet PHY. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair ethernet operation on AV96Marek Vasut
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for ethernet RGMIIMarek Vasut
Add another mux option for DWMAC RGMII, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add configuration EEPROM on AV96Marek Vasut
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42
2020-04-01ARM: dts: stm32: Use DT alias for the configuration EEPROMMarek Vasut
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add QSPI NOR on AV96Marek Vasut
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e
2020-04-01ARM: dts: stm32: Repair SDMMC2 operationMarek Vasut
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7Marek Vasut
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair SDMMC1 operation on AV96Marek Vasut
The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pinsMarek Vasut
Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96Marek Vasut
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this. This fixes booting from SD1 X9 slot on the AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-03-31Merge tag 'arc-last-minute-fixes-for-2020.04' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc This last minute pull-request is intended to fix some drivers when used on ARC boards. The problem was introduced by https://gitlab.denx.de/u-boot/u-boot/-/commit/07906b3dad157bd58411664bcc6a2a7976d5e0a9 What happened while doing one pretty simple improvement to make U-Boot port more flexible and portable (by switching accessors from assembly-written to plain C version) we implicitly added 2 problems: 1. Downgraded accessors from being volatile which signalled to the compiler that it's now possible to do all kinds of optimizations which may easily include merge of subsequent byte reads/writes into word operations. Which is OK for accessing mormal memory but breaks operation of peripherals if we access its memory-mapped regs in such a "creative" manner. 2. As a part of assembly-written implementation we had compiler barriers in form of the following construction 'asm volatile("" : : : "memory")', and we dropped it in C implemntation. This in its turn enabled compiler to mess with instruction ordering. Guess what it gives us in the end :) So with all that we had in some corner-cases veeery funny instruction flows generated. And in particular it broke DW SPI functionality when we were writing large amount of data. Funny enough our tests which were writing small amount of data still worked and only by the chance we caught that breakage and unrolled that quite interesting loop of unexpected problems. The road to hell is paved with good intentions. Amen :)
2020-03-31ARC: IO: add MB for __raw_* memory accessorsEugeniy Paltsev
We add memory barriers for __raw_readX / __raw_writeX accessors same way as it is done for readX and writeX accessors as lots of U-boot driver uses __raw_readX / __raw_writeX instead of proper accessor with barrier. It will save us from lot's of debugging in the future and it is OK as U-Boot is not that performance oriented as real run-time software like OS or user bare-metal app so we may afford being not super fast as we only being executed once. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31ARC: IO: add compiler barriers to IO accessorsEugeniy Paltsev
We must use compiler barriers in C-version read/write IO accessors before and after operation (read or write) so it won't be reordered by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31ARC: IO: add volatile to accessorsEugeniy Paltsev
We must use 'volatile' in C-version read/write IO accessors implementation to avoid merging several reads (writes) into one read (write), or optimizing them out by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31Merge branch '2020-03-31-master-imports'Tom Rini
- mpc8xxx GPIO, SPI bugfixes - Add VxWorks to FIT images - macb ethernet driver bugfix
2020-03-31net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.Michal Simek
When MACB_ZYNQ is enabled there is compilation warnings drivers/net/macb.c: In function ‘_macb_init’: drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function); did you mean ‘MACB_MCF’? writel((value), (port)->regs + MACB_##reg) ^~~~~ It has been caused by changing macros name by commit below. Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-31mpc8xxx_spi: implement real ->set_speedRasmus Villemoes
Not all boards have the same CSB frequency, nor do every SPI slave necessarily support running at 16.7 MHz. So implement ->set_speed; that also allows using a smaller PM (i.e., 0) for slaves that do support a higher speed. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: always use 8-bit characters, don't read or write garbageRasmus Villemoes
There are a few problems with the current driver. First, it unconditionally reads from dout/writes to din whether or not those pointers are NULL. So for example a simple "sf probe" ends up writing four bytes at address 0: => md.l 0x0 8 00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ => sf probe 0 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48 SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB => md.l 0x0 8 00000000: ff000000 45454545 05050505 05050505 ....EEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ (here I've change the first debug statement to a printf, and made it print the din/dout pointers rather than the uints they point at). Second, as we can also see above, it always writes a full 32 bits, even if a smaller amount was requested. So for example => mw.l $loadaddr 0xaabbccdd 8 => md.l $loadaddr 8 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ 02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x400 6 device 0 offset 0x400, size 0x6 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48 SF: 6 bytes @ 0x400 Read: OK => sf read 0x02000010 0x400 8 device 0 offset 0x400, size 0x8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64 SF: 8 bytes @ 0x400 Read: OK => md.l $loadaddr 8 02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE.......... 02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........ Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7 bytes), the last three bytes and up being the wrong ones, since the driver does a full 32 bit read and then shifts the wrong byte out: => mw.l $loadaddr 0xaabbccdd 4 => md.l $loadaddr 4 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x444 10 device 0 offset 0x444, size 0x10 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128 SF: 16 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0 => mw.l $loadaddr 0xaabbccdd 4 => sf read $loadaddr 0x444 0xb device 0 offset 0x444, size 0xb mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88 SF: 11 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219...... Fix all of that by always using a character size of 8, and reject transfers that are not a whole number of bytes. While it ends being more work for the CPU, we're mostly bounded by the speed of the SPI bus, and we avoid writing to the mode register in every loop. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: put max_cs to useRasmus Villemoes
Currently, max_cs is write-only; it's just set in mpc8xxx_spi_ofdata_to_platdata and not otherwise used. My mpc8309 was always resetting during an "sf probe 0". It turns out dm_gpio_set_dir_flags() was being called with garbage, since nothing had initialized priv->gpios[0] - our device tree used "cs-gpios" rather than "gpios", so gpio_request_list_by_name() had returned 0. That would have been a lot easier to figure out if the chip select index was sanity checked, so rename max_cs to cs_count, and reject a xfer with a too large cs index. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gazerbeam: add clocks property to SPI nodeRasmus Villemoes
Prepare for supporting setting different speeds in mpc8xxx_spi.c. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signalKlaus H. Sorensen
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi chip select, SPISEL_BOOT, that is used by the boot code to boot from flash. This chip select will typically be used to select a SPI boot flash. The SPISEL_BOOT signal is controlled by a single bit in the SPI_CS register. Implement a gpio driver for the spi chip select register. This allows a spi driver capable of using gpios as chip select, to bind a chip select to SPISEL_BOOT. It may be a little odd to do this as a GPIO driver, since the signal is neither GP or I, but it is quite convenient to present it to the spi driver that way. The alternative it to teach mpc8xxx_spi to handle the SPISEL_BOOT signal itself (that is how it's done in the linux kernel, see commit 69b921acae8a) Signed-off-by: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio: mpc8xxx: don't do RMW on gpdat register when setting valueRasmus Villemoes
The driver correctly handles reading back the value of an output gpio by reading from the shadow register for output, and from gpdat for inputs. Unfortunately, when setting the value of some gpio, we do a RMW cycle on the gpdat register without taking the shadow register into account, thus accidentally setting other output gpios (at least those whose value cannot be read back) to 0 at the same time. When changing a gpio from input to output, we still need to make sure it initially has the requested value. So, the procedure is - update the shadow register - compute the new gpdir register - write the bitwise and of the shadow and new gpdir register to gpdat - write the new gpdir register Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio: mpc8xxx: don't modify gpdat when setting gpio as inputRasmus Villemoes
Since some chips don't support reading back the value of output gpios from the gpdat register, we should not do a RMW cycle (i.e., the clrbits_be32) on the gpdat register when setting a gpio as input, as that might accidentally change the value of some other (still configured as output) gpio. The extra indirection through mpc8xxx_gpio_set_in() does not help readability, so just fold the gpdir update into mpc8xxx_gpio_direction_input(). Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31cmd: mmc: fix typo 'a EMMC'Heinrich Schuchardt
%s/a EMMC/an eMMC/g Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-03-31image-fit: Allow loading FIT image for VxWorksLihua Zhao
This adds the check against IH_OS_VXWORKS during FIT image load, to allow loading FIT image for VxWorks. Signed-off-by: Lihua Zhao <lihua.zhao@windriver.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-31Merge tag 'efi-2020-04-rc5' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc5 This series fixes: * UEFI Python tests CONFIG_OF_CONTROL=y. * int to pointer cast warning for cmd/efidebug.c * memory reservation even if fdt node is disabled Now that the Python test is fixed reintroduce the reverted patch for vexpress_ca9x4 to enable EFI_LOADER and define the dtb file name.
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Fixes for Gen 2 V2H Blanche
2020-03-31arm: dts: agilex: Enable QSPILey Foon Tan
Enable QSPI for Agilex SoC devkit. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: arria10: Add save_boot_params()Ley Foon Tan
Add save_boot_params() to save reset status value from bootrom. Bootrom will clear the status register in reset manager and stores the reset status value in shared memory. Bootrom stores shared data at last 2KB of onchip RAM. This function save reset status provided by bootrom to rst_mgr_status. More information about reset status register value can be found in reset manager register description. When running in debugger without bootrom, r0 to r3 are random values. So, skip save the value when r0 is not bootrom shared data address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macroLey Foon Tan
Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: Add onchip RAM size macroLey Foon Tan
Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>