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2017-03-28pcie-layerscape: Fixup iommu-map property of pci nodeBharat Bhushan
This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pcie-layerscape: Initialize pci-lut for NXP chasis-2 socsBharat Bhushan
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1012aBharat Bhushan
LS1012A is Chassis-2 type SOC and shares same streamid definition. This patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1046aBharat Bhushan
LS1046A is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for LS1046A. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2Bharat Bhushan
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they are behind SMMU. This patch defines the stream-ids for Chassis-2 devices. DPAA1 is reserved for future use. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Rewrite comment for stream IDsBharat Bhushan
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.hBharat Bhushan
The stream ID allocation for Chasis 3.0 devices can be shared among LS1088, LS2088 and LS2080. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND bootHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND FlashHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: PPA: add support PPA image loading from NAND and SDHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28mtd: nand: remove nand size print from nand_init functionHou Zhiqiang
Add nand_size() function to move the nand size print into initr_nand(). Remove nand size print from nand_init() to allow other function to call nand_init() without printing nand size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28mtd: nand: add initialization flagHou Zhiqiang
Add initialization flag to avoid initializing NAND Flash multiple times, otherwise it will calculate a wrong total size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012AYingxi Yu
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup. Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on NOR flashWenbin Song
Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman partitions. Add user partitions for general usage. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28board: freescale: ls2080a/ls2088a: Enable PPASantan Kumar
Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: Fixup device tree node for ls2088aHou Zhiqiang
LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28tools: plbimage support generate rcw fileyuan linyu
some system will not generate pbl format u-boot, but require rcw. Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203Ashish kumar
This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: dts: fsl-ls1012a: Change number of CS in SPI nodeSuresh Gupta
LS1012A has only one chip select for QSPI flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28spi: fsl_qspi: Add support for single chip selectSuresh Gupta
SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8:fsl-layerscape: Avoid RCWSR28 register hard-codingPrabhakar Kushwaha
SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28arm: fsl-layerscape: Move QSGMII wriop_init to SoC filePrabhakar Kushwaha
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: Update erratum A009635 implementationPriyanka Jain
Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: enable PCIe config readyHou Zhiqiang
In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: Secure Boot: Enable IE (Key extention) FeatureUdit Agarwal
For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: ls2080ardb, ls2080aqds: Add mcmemsize in default env settingSantan Kumar
Initialize mcmemsize to 0x40000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl-layerscape/ppa: cleanup ppa.hHou Zhiqiang
Moved the ifdef into ppa.h and removed the duplicated macros. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: LS2080A: Move sec_init to board_initUdit Agarwal
Moves sec_init to board_init rather than in misc_init function beacuse PPA will be initialised in board_init function and for PPA validation sec_init has to be done prior to PPA init. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080AUdit Agarwal
Add header address for PPA to be validated during ESBC phase for LS2080A platform based on Layescape Chasis 3. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28i2c: Set default I2C bus numberLukasz Majewski
This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc) without the need to first select the bus number with e.g. "i2c dev 0". This is the "i2c" command behavior similar to the one from pre DM, where by default bus 0 was immediately accessible. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: ti: Update method to calculate psc, sscl and ssch I2C parametersLukasz Majewski
This patch updates the way in which psc, sscl and ssch I2C parameters are calculated to be in sync with v4.9 Linux kernel SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826 in the ./drivers/i2c/busses/i2c-omap.c The previous method was causing several issues: - The internal I2C frequency (after prescaler) was far above recommended one (7 - 12 MHz [*]) - the current approach brings better noise suppression (as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb) - The values calculated (psc, sscl and ssch) were far from optimal, which caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast Mode) of ~1.0us (the standard requires > 1.3 us). [*] for AM57xx TRM SPRUHZ6G, Table 24,7 "HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: ti: Update SCLH and SCLL to be in sync with v4.9 Linux kernelLukasz Majewski
v4.9 Linux release: SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826 in the ./drivers/i2c/busses/i2c-omap.c recommends to use SCLH=5 and SCLL=7 values. This patch sets them to default. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: lpc32xx: Force consistent bus numberingLiam Beguin
Normally, this would probably be done by adding devicetree aliases to the main dtsi file for the lpc32xx and using bus->req_seq instead. Since we want to have consistent i2c numbering, we cannot force the bus->req_seq because. If for instance we have 3 buses numbered from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled; i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands because a bus can be probed using req_seq or seq interchangeably. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Move definitions to header fileLiam Beguin
Since the lpc32xx i2c driver does not yet support the devicetree bindings, this structure is also needed by the board file as the hardware description is done there. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Remove note for DM conversationSylvain Lemieux
Removed note in the LPC32xx I2C driver for DM conversation. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Add DM for lpc32xx I2CLiam Beguin
Adding DM specific wrapper functions and definitions. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Factor out i2c_adapter parameterLiam Beguin
This is part of the prep work for the migration to the driver model. It will enable the driver to support DM and non-DM configurations using the same functions. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Prepare compatibility functionsLiam Beguin
This is part of the prep work for the migration to the driver model. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Rename probe functionLiam Beguin
This is part of the prep work for the migration to the driver model. What used to be the probe function is now called probe_chip. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-26Add single register pin controller driverFelix Brack
This patch adds a pin controller driver supporting devices using a single configuration register per pin. Signed-off-by: Felix Brack <fb@ltec.ch>
2017-03-26reset: Add STi reset supportPatrice Chotard
This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-26pci: correct a function descriptionHou Zhiqiang
In the description of function pci_match_one_id(), there are some problems on arguments list and return value description, so correct them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-03-26lib: tpm: Add command to list resourcesmario.six@gdsys.cc
It is sometimes convenient to know how many and/or which resources are currently loaded into a TPG, e.g. to test is a flush operation succeeded. Hence, we add a command that lists the resources of a given type currently loaded into the TPM. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26cmd: tpm: Fix flush commandmario.six@gdsys.cc
Commit 7690be35de ("lib: tpm: Add command to flush resources") added a command to flush resources from a TPM. However, a previous development version was accidentially used to generate the patch, resulting in a non-functional command. This patch fixes the flush command. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26tpm: Add function to load keys via their parent's SHA1 hashmario.six@gdsys.cc
If we want to load a key into a TPM, we need to know the designated parent key's handle, so that the TPM is able to insert the key at the correct place in the key hierarchy. However, if we want to load a key whose designated parent key we also previously loaded ourselves, we first need to memorize this parent key's handle (since the handles for the key are chosen at random when they are inserted into the TPM). If we are, however, unable to do so, for example if the parent key is loaded into the TPM during production, and its child key during the actual boot, we must find a different mechanism to identify the parent key. To solve this problem, we add a function that allows U-Boot to load a key into the TPM using their designated parent key's SHA1 hash, and the corresponding auth data. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-26libfdt: use CONFIG_IS_ENABLED for OF_LIBFDTVignesh R
Use CONFIG_IS_ENABLED() macro to check whether OF_TRANSLATE is enabled, so that code block is compiled irrespective of SPL or U-Boot build and fdt address translation is used. Signed-off-by: Vignesh R <vigneshr@ti.com>
2017-03-26Ensure device tree DTS is compiledJames Balean
Enables custom DTS files, or those not associated with a specific target, to be compiled into a boot image. Signed-off-by: James Balean <james@balean.com.au> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Simon Glass <sjg@chromium.org>
2017-03-26drivers/net/phy: add fixed-phy / fixed-link supportHannes Schmelzer
This patch adds support for having a "fixed-link" to some other MAC (like some embedded switch-device). For this purpose we introduce a new phy-driver, called "Fixed PHY". Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is described with a subnode below ethernet interface. Most ethernet drivers (unfortunately not all are following same scheme for searching/attaching phys) are calling "phy_connect(...)" for getting a phy-device. At this point we link in, we search here for a subnode called "fixed- link", once found we start phy_device_create(...) with the special phy- id PHY_FIXED_ID (0xa5a55a5a). During init the "Fixed PHY" driver has registered with this id and now gets probed, during probe we get all the details about fixed-link out of dts, later on the phy reports this values. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-03-26fdt_support: Fixup 'ethernet' aliases not ending in digitsTuomas Tynkkynen
The Raspberry Pi device tree files since Linux v4.9 have a "ethernet" alias pointing to the on-board Ethernet device node. However, U-Boot's fdt_fixup_ethernet() only looks at ethernet aliases ending in digits. As the spec doesn't mandate that aliases must end in numbers and there have been much older uses of an "ethernet" aliases in the wild (according to Tom Rini), change the code to accept "ethernet" as well. Without this Linux isn't told of the MAC address provided by the RPI firmware and the ethernet interface is always assigned a random MAC address. Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>