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These describe the GPIOs in enough detail for U-Boot's GPIO driver to
operate.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These describe the GPIOs in enough detail for U-Boot's GPIO driver to
operate.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We don't include the pinctrl functions for U-Boot as they use up quite
a bit of space and are not used.
We could instead perhaps eliminate this material with fdtgrep, but so far
this tool has not made it to upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Bring in required device tree files for pinctrl from Linux v3.14. These
are initially unchanged and have a number of pieces not needed by U-Boot.
Note that exynos5420 is renamed to exynos54xx here since we want to
support exynos5422 also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We should be consistent about this. The kernel has moved to #include
which breaks error reporting to some extent but does allow us to include
binding files.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add proper initialization of GPIO pins used by software i2c.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The driver model supports two ways for passing device parameters;
Device Tree and platform_data (board file).
Each driver should generally support both of them because some
popular IPs are used on various platforms.
Assume the following scenario:
- The driver Foo is used on SoC Bar and SoC Baz
- The SoC Bar uses Device Tree control (CONFIG_OF_CONTROL=y)
- The SoC Baz does not support Device Tree; uses a board file
In this situation, the device driver Foo should work with/without
the device tree control. The driver should have .of_match and
.ofdata_to_platdata members for SoC Bar, while they are meaningless
for SoC Baz; therefore those device-tree control code should go
inside #ifdef CONFIG_OF_CONTROL.
The driver code will be like this:
#ifdef CONFIG_OF_CONTROL
static const struct udevice_id foo_of_match = {
{ .compatible = "foo_driver" },
{},
}
static int foo_ofdata_to_platdata(struct udevice *dev)
{
...
}
#endif
U_BOOT_DRIVER(foo_driver) = {
...
.of_match = of_match_ptr(foo_of_match),
.ofdata_to_platdata = of_match_ptr(foo_ofdata_to_platdata),
...
}
This idea has been borrowed from Linux.
(In Linux, this macro is defined in include/linux/of.h)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The header files include/dm/platdata.h and include/dm/uclass.h
use ll_entry_declare(); therefore they depend on
include/linker_lists.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The header file include/linker_lists.h uses __aligned();
therefore it depends on include/linux/compiler.h
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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if (strncmp(name, entry->name, len))
continue;
/* Full match */
if (len == strlen(entry->name))
return entry;
is equivalent to:
if (!strcmp(name, entry->name))
return entry;
The latter is simpler.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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The function uclass_add() checks uc_drv->ops as follows:
if (uc_drv->ops) {
dm_warn("No ops for uclass id %d\n", id);
return -EINVAL;
}
It seems odd because it warns "No ops" when uc_drv->ops has
non-NULL pointer. (Looks opposite.)
Anyway, most of UCLASS_DRIVER entries have no .ops member.
This check makes no sense.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The struct udevice stands for a device, not a driver.
The driver_info.name is a driver's name, which is referenced
to bind devices.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Update Apalis T30 as per the following commits
c369139234c03b1494394d12cd27009f47aa6606
tegra: dts: Add serial port details
461be2f96e4b87e5065208c6659a47dd0ad9e9f8
kconfig: remove redundant "string" type in arch and board Kconfigs
f1ef2b62339526df3b921bcfefd174ce76d4c624
kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Add missing chosen stdout-path device tree node. This got missed by
commit
c369139234c03b1494394d12cd27009f47aa6606
tegra: dts: Add serial port details
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Clean-up a spurious new line which got introduced resp. left behind by
commit
f1ef2b62339526df3b921bcfefd174ce76d4c624
kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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On popular request this now completes the Warren's work started for
TK1:
aeb3fcb35956461077804720b8a252d50758d7e0
ARM: tegra: Use mem size from MC rather than ODMDATA
In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
<supposed to be used in each and every U-Boot port>TM. Added benefit is
that it should <catch 99% of hardware related (i. e. reliably
reproducible) memory errors> as well.
Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.
Based-on-work-by: Stephen Warren <swarren@nvidia.com>
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Wondering what exactly that one should bring (;-p). Looks like a remnant of the last commit
783e6a72b8278d59854ced41a4696c9a14abbb0b
kconfig: move CONFIG_OF_* to Kconfig
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Fix ASIX USB to Ethernet reset which due to the new driver model Tegra
GPIO driver changes now requires a label string to be provided
otherwise the reservation and subsequent direction/value calls will
fail.
This fixes a regression introduced by commit:
2fccd2d96badcdf6165658a99771a4c475586279
tegra: Convert tegra GPIO driver to use driver model
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Fix Tegra GPIO driver to not crash resp. misbehave upon requesting
GPIOs with an empty aka NULL label. As the driver uses exclusively the
label to check for reservation status actually supplying one is
mandatory!
This fixes a regression introduced by commit:
2fccd2d96badcdf6165658a99771a4c475586279
tegra: Convert tegra GPIO driver to use driver model
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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During rigorous testing of our latest update infrastructure I came
across quite consistent timeouts on certain eMMC parts (e.g. Hynix
H26M21001ECR) when writing big (e.g. in excess of 400 MB) file system
images:
MMC write: dev # 0, block # 40960, count 944128 ...
mmc_send_cmd_bounced: MMC Timeout
Interrupt status 0x00000001
Interrupt status enable 0xdfff003b
Interrupt signal enable 0xdfff0002
Present status 0x01870106
mmc write failed
Comparing the various data sheets I came across the following timeout
specification:
Secure Erase/TRIM Timeout=300ms*2*10=6000ms
Unfortunately empirical testing still failed albeit much more rarely.
Increasing the timeout to 8000ms made it finally disappear entirely.
This patch allows us writing various eMMC parts without seeing any
further issues.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Use architecture specific memcpy to speed up things.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This patch adds board support for the Toradex Apalis T30 a computer on
module which can be used on different carrier boards.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot and environment storage
- Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210
fixes hit mainline)
- MMC/SD cards (both 8-bit as well as 4-bit slot)
- USB client/host (dual role port as client e.g. for DFU/UMS, other two
ports as host)
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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GDT limit should be one less than an integral multiple of eight.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Add a new setup@ section to the FIT which can be used to provide a setup
binary for booting Linux on x86. This makes it possible to boot x86 from
a FIT.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This uses cfg instead of conf, and img instead of image. Fix these and
update in a few other places.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Since sandbox is used for testing, it should be able to 'boot' an image
from any archhitecture. This allows us to test an image by loading it in
sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
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If we are passing this using the device tree then we may not want to
set this up here.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The x86 bootm code is quite special, and geared to zimage. Adjust it
to support device tree and make it more like the ARM code, with
separate bootm stages and functions for each stage.
Create a function announce_and_cleanup() to handle printing the
"Starting kernel ..." message and put it in bootm so it is in one
place and can be used by any loading code. Also move the
board_final_cleanup() function into bootm.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These options are used by the image code. To allow us to use the generic
code more easily, define these for x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Enable blob commands for platforms having SEC 4.0 or greater
for secure boot scenarios
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Freescale's SEC block has built-in Blob Protocol which provides
a method for protecting user-defined data across system power
cycles. SEC block protects data in a data structure called a Blob,
which provides both confidentiality and integrity protection.
Encapsulating data as a blob
Each time that the Blob Protocol is used to protect data, a
different randomly generated key is used to encrypt the data.
This random key is itself encrypted using a key which is derived
from SoC's non volatile secret key and a 16 bit Key identifier.
The resulting encrypted key along with encrypted data is called a blob.
The non volatile secure key is available for use only during secure boot.
During decapsulation, the reverse process is performed to get back
the original data.
Commands added
--------------
blob enc - encapsulating data as a cryptgraphic blob
blob dec - decapsulating cryptgraphic blob to get the data
Commands Syntax
---------------
blob enc src dst len km
Encapsulate and create blob of data $len bytes long
at address $src and store the result at address $dst.
$km is the 16 byte key modifier is also required for
generation/use as key for cryptographic operation. Key
modifier should be 16 byte long.
blob dec src dst len km
Decapsulate the blob of data at address $src and
store result of $len byte at addr $dst.
$km is the 16 byte key modifier is also required for
generation/use as key for cryptographic operation. Key
modifier should be 16 byte long.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them once the control reaches the bootloader.
For non-secure boot, PAMU's are already bypassed in the default
SoC configuration.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Enable CAAM in platforms supporting the hardware block.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's
The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam.
The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to
enable initialization of this hardware IP.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.
So update acessor functions with common SEC acessor functions to take care
both type of endianness.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Freescale SEC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
SEC to common include
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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U-boot binary size has been increased from 512KB to 768KB.
So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for
P1010 SPI Flash Secure boot target.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Modified subject to P1010RDB]
Reviewed-by: York Sun <yorksun@freescale.com>
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The ipu display insists on having a lower_margin smaller
then 2. If this is not the case it will attempt to force
it and adjust the pixclk accordingly. This multiplies pixclk
in Hz with the width and height, since this is typically
a * 10^7 * b * 10^2 * c * 10^2 this will overflow the
uint_32 and make things even worse. Since this is a
bootloader and the adjustment is neglectible, just force
it to two and warn about it.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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- fix debug pixel clk display and add unit
- fix some comments
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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Add a block to avoid a build error with the variable declaration.
Enable the option on sandbox to prevent an error being introduced in
future.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Rini <trini@ti.com>
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Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste
error introduced when adding the axp152_mvolt_to_target during review of the
axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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