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2014-12-18x86: Convert microcode format to device-tree-onlySimon Glass
To avoid having two microcode formats, adjust the build system to support obtaining the microcode from the device tree, even in the case where it must be made available before the device tree can be accessed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: Add basic support to queensbay platform and crownbay boardBin Meng
Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18x86: Integrate Tunnel Creek processor microcodeBin Meng
Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18x86: Correct problems in the microcode loadingSimon Glass
There are several problems in the code. The device tree decode is incorrect in ways that are masked due to a matching bug. Both are fixed. Also microcode_read_rev() should be inline and called before the microcode is written. Note: microcode writing does not work correctly on ivybridge for me. Further work is needed to resolve this. But this patch tidies up the existing code so that will be easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18x86: ivybridge: Update the microcodeSimon Glass
There are new microcode revisions available. Update them. Also change the format so that the first 48 bytes are not omitted from the device tree data. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18x86: Move microcode updates into a separate directorySimon Glass
We might end up with a few of these, so put them in their own directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: ifdtool: Add support for early microcode accessSimon Glass
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible means of starting up the CPU. One result is that microcode updates can only be done before RAM is available and therefore parsing of the device tree is impracticle. Worse, the addess of the microcode update must be stored in ROM since a pointer to its start address and size is passed to the 'FSP' blob. It is not possible to perform any calculations to obtain the address and size. To work around this, ifdtool is enhanced to work out the address and size of the first microcode update it finds in the supplied device tree. It then writes these into the correct place in the ROM. U-Boot can then start up the FSP correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: ifdtool: Use a structure for the file/address listSimon Glass
Rather than two independent arrays, use a single array of a suitable structure. Also add a 'type' member since we will shortly add additional types. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: ifdtool: Display filename when file errors are reportedSimon Glass
When a file is missing it helps to know which file. Update the error message to print this information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: ifdtool: Correct a debug() missing parameterSimon Glass
This is missing a parameter. Fix it to avoid a warning when debug is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18net: rtl8169: Add support for RTL-8168/8111gThierry Reding
This network interface card is found on the NVIDIA Jetson TK1. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18net: rtl8169: Use non-cached memory if availableThierry Reding
To work around potential issues with explicit cache maintenance of the RX and TX descriptor rings, allocate them from a pool of uncached memory if the architecture supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18net: rtl8169: Properly align buffersThierry Reding
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't have to be manually aligned later on. Also make sure that the buffers do align to cache-line boundaries in case the cache-line is higher than the 256 byte alignment requirements of the NIC. Also add a warning if the cache-line size is larger than the descriptor size, because the driver may discard changes to descriptors made by the hardware when requeuing RX buffers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFERThierry Reding
According to the top-level README file, this configuration setting can be used to override the number of receive buffers that an ethernet NIC uses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable non-cached memoryThierry Reding
Some boards, most notably those with a PCIe ethernet NIC, require this to avoid cache coherency problems. Since the option adds very little code and overhead enable it across all Tegra generations. Other drivers may also start supporting this functionality at some point, so enabling it now will automatically reap the benefits later on. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: Implement non-cached memory supportThierry Reding
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add Tegra124 PCIe device tree nodeThierry Reding
Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add GIC for Tegra124Thierry Reding
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable PCIe on BeaverThierry Reding
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. In addition the board has a mini-PCIe expansion slot. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable PCIe on CardhuThierry Reding
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding
Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add GIC for Tegra30Thierry Reding
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable PCIe on TrimSliceThierry Reding
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding
Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18pci: tegra: Add Tegra PCIe driverThierry Reding
Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Enable XUSB pad controller on Jetson TK1Thierry Reding
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Add XUSB pad controller on Tegra124Thierry Reding
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Implement XUSB pad controllerThierry Reding
This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Implement powergate supportThierry Reding
Implement the powergate API that allows various power partitions to be power up and down. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Provide PCIEXCLK reset IDThierry Reding
This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: tegra: Implement tegra_plle_enable()Thierry Reding
This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18power: Add AMS AS3722 PMIC supportThierry Reding
The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18ARM: Implement non-cached memory supportThierry Reding
Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18ARM: tegra: colibri_t30: comment style fixMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2014-12-18ARM: UniPhier: enable CONFIG_CMD_DMMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: select CONFIG_SPLMasahiro Yamada
Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: use DRAM area for init stack of normal imageMasahiro Yamada
The normal image is working on DRAM. It is better to use DRAM also for init stack than L2 cache. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada
init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada
The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18sf: sf_params: Add S25FL164K flash identifier infoAdnan Ali
Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18sf: sf_params: Add S25FL116K flash supportAdnan Ali
Added S25FL116K flash and tested on Marvell 88F6281 based system. Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18mtd/spi: Add support for SST25WF040BShengzhou Liu
Add support for SST25WF040B-40I-SN flash. Tested on T1024QDS board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18mtd: sf: Zap ramtron driverJagannadha Sutradharudu Teki
Removed ramtron driver since the EMK boards are no longer been active, and these are the only boards used this flash driver. Commit details for EMK zap: "ppc/arm: zap EMK boards" (sha1: d58a9451e7339ed4cf2b2627e534611f427fb791) Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
2014-12-18fastboot: handle flash write to GPT partitionsSteve Rae
Implement a feature to allow fastboot to write the downloaded image to the space reserved for the Protective MBR and the Primary GUID Partition Table. Additionally, prepare and write the Backup GUID Partition Table. Signed-off-by: Steve Rae <srae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [Test HW: Exynos4412 - Trats2]
2014-12-18disk: part_efi: move code to static functionsSteve Rae
Signed-off-by: Steve Rae <srae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [Test HW: Exynos4412 - Trats2]
2014-12-18dfu: dfu_get_buf: check the value of env dfu_bufsiz before usePrzemyslaw Marczak
In function dfu_get_buf(), the size of allocated buffer could be defined by the env variable. The size from this variable was passed for memalign() without checking its value. And the the memalign will return non null pointer for size 0. This could possibly cause data abort, so now the value of var is checked before use. And if this variable is set to 0 then the default size will be used. This commit also changes the base passed to simple_strtoul() to 0. Now decimal and hex values can be used for the variable dfu_bufsiz. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
2014-12-18gadget: f_thor: check pointers before use in download_tail()Przemyslaw Marczak
Some pointers in function download_tail() were not checked before the use. This could possibly cause the data abort. To avoid this, check if the pointers are not null is added. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
2014-12-18dfu: mmc: check if mmc device exists in mmc_block_op()Przemyslaw Marczak
The function mmc_block_op() is the last function before the physicall data write, but the mmc device pointer is not checked. If mmc device not exists, then data abort will occur. To avoid this, first the mmc device pointer is checked. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [TestHW: Exynos4412-Trats2]
generated by cgit (git 2.34.1) at 2025-01-08 00:17:15 +0000