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2018-12-19bmips: enable wap-5813n enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19net: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19bmips: enable nb4-ser enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable hg556a enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable ct-5361 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable f@st1704 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19net: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19bmips: bcm6318: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm63268: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6362: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6328: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19dma: add bcm6348-iudma supportÁlvaro Fernández Rojas
BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-18doc: README.ae350: Sync for ax25-ae350 renameRick Chen
Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18riscv: configs: Rename ax25-ae350 defconfigRick Chen
Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Also sync MAINTAINERS: Rename a25-ae350_32_defconfig as ae350_rv32_defconfig ax25-ae350_64_defconfig as ae350_rv64_defconfig Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18riscv: qemu: Imply SIFIVE_SERIAL for emulationAnup Patel
This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18drivers: serial: Add SiFive UART driverAnup Patel
This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18riscv: Remove ae350.dtsBin Meng
This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng
Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Save boot hart id to the global dataBin Meng
At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add exception codes for xcause registerBin Meng
This adds all exception codes in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add CSR numbersBin Meng
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Probe cpus during bootBin Meng
This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng
Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel
This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel
So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng
There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-18timer: Add generic driver for RISC-V privileged architecture defined timerBin Meng
RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18cpu: Add a RISC-V CPU driverBin Meng
This adds a driver for RISC-V CPU. Note the driver will bind a RISC-V timer driver if "timebase-frequency" property is present in the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng
To enumerate devices on the /soc/ node, create a "simple-bus" driver to match "riscv-virtio-soc". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18dm: cpu: Add timebase frequency to the platdataBin Meng
This adds a timebase_freq member to the 'struct cpu_platdata', to hold the "timebase-frequency" value in the cpu or /cpus node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer
RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-17Prepare v2019.01-rc2Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2025-01-08 17:40:41 +0000