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2018-09-27armv8: ls1043a: advertise QMan v3 in configurationLaurentiu Tudor
The QMan IP block in this SoC is version 3.2 so advertise this in the SoC configuration header. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: fsl-layerscape: add missing qe base address defineLaurentiu Tudor
Add define for QUICC Engine register block base address. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27driver: net: fsl-mc: Memset MC reserve ram memory before usagePrabhakar Kushwaha
Memory reserved for Management Complex needs to be cleaned before any usage. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27u-boot: fixup the iommu-map property of fsl-mc nodeNipun Gupta
The iommu-map property in the fsl-mc node is updated by valid stream-ids by u-boot. This patch is to fixup this property for LS208x and LS1088. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ls1012afrwy: Add ls1012afrwy revC board support.Pramod Kumar
LS1012AFRWY supports three board revisions. Revision A and B board are collectively identified as revA/B, Revision C board is identifies as revC. Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> [York S: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27scsi: ceva: add ls1021a soc support.Peng Ma
Add ahci compatible support for ls1021a soc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27arm: ls1021atwr: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv7: dts: fsl-ls1021a: add sata node support enable sata for ls1021a-qds ↵Peng Ma
and ls1021a-twr Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv7: fsl: remove sata supportPeng Ma
Remove the old implementation in order to enable DM for sata Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27arm64: ls1043aqds: enable DM support for sataPeng Ma
Enable related configs to support sata DM feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27scsi: ceva: add ls1043a soc supportPeng Ma
Add ahci compatible support for ls1043a soc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: dts: fsl-ls1043a: add sata node supportPeng Ma
Add sata node to support ls1043a. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27Enable CONFIG_BLK and CONFIG_DM_MMC to KconfigYinbo Zhu
This enables the folowing to Kconfig: CONFIG_BLK CONFIG_DM_MMC Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv7: ls1021a: enable esdhcYinbo Zhu
This patch is to enable eSDHC for ls1021a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls1046a: add eSDHC nodeYinbo Zhu
This patch is to add eSDHC node for ls1046a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls1043a: add eSDHC nodeYinbo Zhu
This patch is to add eSDHC node for ls1043a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls1088a: add eSDHC nodeYinbo Zhu
This patch is to add eSDHC node for ls1088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls2088a: add eSDHC nodeYinbo Zhu
This patch is to add eSDHC node for ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8/ls1088a/ls2088a: esdhc: Add esdhc clock supportYinbo Zhu
This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ppa/fm/qe: use block layer in ppa/fm/qe driverYinbo Zhu
At present the MMC subsystem maintains its own list of MMC devices. This cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to replace previous mmc read interface, use mmc_get_blk_desc to get the mmc device property. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> [York S: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-19Merge git://git.denx.de/u-boot-imxTom Rini
- changes in pico-* boards - fix imx6ull pinmux
2018-09-19Merge git://git.denx.de/u-boot-marvellTom Rini
- Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards
2018-09-19arm: mvebu: clearfog: enable eMMC boot partitions supportBaruch Siach
The Clearfog SOM can optionally have eMMC installed. Enable support for eMMC boot partitions by default. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19phy: marvell: add SATA comphy RX/TX polarity invert supportRabeeh Khoury
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: cmd: mvebu: Exclude mvebu commands from SPL buildsKonstantin Porotchkin
Exclude mvebu commands from SPL builds Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: mvebu: Add SPI parameters for environment setupKonstantin Porotchkin
Add definitions for CONFIG_ENV_SPI_BUS and CONFIG_ENV_SPI_CS to Armada-388-GP board configuration Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: env: Fix the SPI flash device setup for DM modeKonstantin Porotchkin
For some reason the spi_flash_probe_bus_cs() is called inside the setup_flash_device() with zero values in place of configurated SPI flash mode and maximum flash speed. This code causes HALT error during startup environment relocation on some platforms - namely Armada-38x-GP board. Fix the function call by replacing zeros with the appropriate values - CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: nand: pxa3xx: Add WA for eliminating flash ready timeoutDavid Sniatkiwicz
add delay before processing the status flags in pxa3xx_nand_irq(). Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> c: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NANDKonstantin Porotchkin
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: cosmetic: add comments to the timing layout structuresKonstantin Porotchkin
Add comments with timing parameter names and some details about nand layout fileds. Remove unneeded definition. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: nand: Replace hardcoded page chunk size with calculated oneKonstantin Porotchkin
Replace the hardcoded value of page chink with value that depends on flash page size and ECC strength. This fixes nand access errors for 2K page flashes with 8-bit ECC. Move the initial flash commannd function assignment past the ECC structures initialization for eliminating usage of hardcoded page chunk size value. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: add support for Toshiba flashKonstantin Porotchkin
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: add support for 2KB 8-bit flashVictor Axelrod
Add support for 2KB page 8-bit ECC strength flash layout Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: Fix READOOB implementationBoris Brezillon
In the current driver, OOB bytes are accessed in raw mode, and when a page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the driver must read the whole spare area (64 bytes in case of a 2k page, 16 bytes for a 512 page). The driver was only reading the free OOB bytes, which was leaving some unread data in the FIFO and was somehow leading to a timeout. We could patch the driver to read ->spare_size + ->ecc_size instead of just ->spare_size when READOOB is requested, but we'd better make in-band and OOB accesses consistent. Since the driver is always accessing in-band data in non-raw mode (with the ECC engine enabled), we should also access OOB data in this mode. That's particularly useful when using the BCH engine because in this mode the free OOB bytes are also ECC protected. Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support") Cc: stable@vger.kernel.org Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: add support for partial chunksOfer Heifetz
This commit is needed to properly support the 8-bits ECC configuration with 4KB pages. When pages larger than 2 KB are used on platforms using the PXA3xx NAND controller, the reading/programming operations need to be split in chunks of 2 KBs or less because the controller FIFO is limited to about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to this requirement, the data layout on NAND is a bit strange, with ECC interleaved with data, at the end of each chunk. When a 4-bits ECC configuration is used with 4 KB pages, the physical data layout on the NAND looks like this: | 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC | So the data chunks have an equal size, 2080 bytes for each chunk, which the driver supports properly. When a 8-bits ECC configuration is used with 4KB pages, the physical data layout on the NAND looks like this: | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC | So, the spare area is stored in its own chunk, which has a different size than the other chunks. Since OOB is not used by UBIFS, the initial implementation of the driver has chosen to not support reading this additional "spare" chunk of data. Unfortunately, Marvell has chosen to store the BBT signature in the OOB area. Therefore, if the driver doesn't read this spare area, Linux has no way of finding the BBT. It thinks there is no BBT, and rewrites one, which U-Boot does not recognize, causing compatibility problems between the bootloader and the kernel in terms of NAND usage. To fix this, this commit implements the support for reading a partial last chunk. This support is currently only useful for the case of 8 bits ECC with 4 KB pages, but it will be useful in the future to enable other configurations such as 12 bits and 16 bits ECC with 4 KB pages, or 8 bits ECC with 8 KB pages, etc. All those configurations have a "last" chunk that doesn't have the same size as the other chunks. In order to implement reading of the last chunk, this commit: - Adds a number of new fields to the pxa3xx_nand_info to describe how many full chunks and how many chunks we have, the size of full chunks and partial chunks, both in terms of data area and spare area. - Fills in the step_chunk_size and step_spare_size variables to describe how much data and spare should be read/written for the current read/program step. - Reworks the state machine to accommodate doing the additional read or program step when a last partial chunk is used. This commit is taken from Linux: 'commit c2cdace755b' ("mtd: nand: pxa3xx_nand: add support for partial chunks") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Simplify pxa3xx_nand_scanOfer Heifetz
This commit simplifies the initial configuration performed by pxa3xx_nand_scan. No functionality change is intended. This commit is taken from Linux: 'commit 154f50fbde53' ("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Fix initial controller configurationOfer Heifetz
The Data Flash Control Register (NDCR) contains two types of parameters: those that are needed for device identification, and those that can only be set after device identification. Therefore, the driver can't set them all at once and instead needs to configure the first group before nand_scan_ident() and the second group later. Let's split pxa3xx_nand_config in two halves, and set the parameters that depend on the device geometry once this is known. This commit is taken from Linux: 'commit 66e8e47eae65' ("mtd: pxa3xx_nand: Fix initial controller configuration") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Increase the initial chunk sizeOfer Heifetz
The chunk size represents the size of the data chunks, which is used by the controllers that allow to split transferred data. However, the initial chunk size is used in a non-split way, during device identification. Therefore, it must be large enough for all the NAND commands issued during device identification. This includes NAND_CMD_PARAM which was recently changed to transfer up to 2048 bytes (for the redundant parameter pages). Thus, the initial chunk size should be 2048 as well. On Armada 370/XP platforms (NFCv2) booted without the keep-config devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM command: [..] pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device pxa3xx-nand f10d0000.nand: Wait time out!!! nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38 nand: Micron MT29F8G08ABABAWP nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224 This commit is taken from Linux: 'commit c7f00c29aa8' ("mtd: pxa3xx_nand: Increase the initial chunk size") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: Increase READ_ID buffer and make the size staticOfer Heifetz
The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. This commit is taken from Linux: 'commit b226eca2088' ("nand: pxa3xx: Increase READ_ID buffer and make the size static") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx-nand: fix random command timeoutsOfer Heifetz
When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase This patch is taken from Linux: 'commit 21fc0ef9652f' ("mtd: nand: pxa3xx-nand: fix random command timeouts") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: fix early spurious interruptOfer Heifetz
When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. This commit is taken from Linux: 'commit 0b14392db2e' ("mtd: nand: pxa3xx_nand: fix early spurious interrupt") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()Ofer Heifetz
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: use nand_to_mtd()Ofer Heifetz
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the one that is already part of struct nand_chip. This brings us in line with current U-boot and Linux conventions. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: Increase initial buffer sizeOfer Heifetz
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. This commit is taken from Linux: 'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19board: turris_mox: Fixup U-Boot's device tree if PCIe connectedMarek Behún
If PCIe Mox module is connected we want to have PCIe node enabled in U-Boot's device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19dts: mvebu: mcbin: drop redundant SD slot nodeBaruch Siach
Commit 61dccf73d302 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added a redundant DT node for SD card slot. Drop it. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19arch/arm/dts: Update Turris Mox device treeMarek Behún
Remove smi_pins definition since it is already in armada-37xx.dtsi. Add assigned-clocks definitions to spi0. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19board: turris_mox: Enable PCI in defconfigMarek Behún
Enable the pci-aardvark driver in defconfig for Turris Mox and also enable the pci command. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19board: turris_mox: Fix watchdog macro nameMarek Behún
The macro name CONFIG_WDT_ARMADA_3720 is called CONFIG_WDT_ARMADA_37XX instead. Fix this so that watchdog really is enabled in board_init. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19clk: armada-37xx-periph: Support changing clock parent and rateMarek Behún
Add support for changing clock rate and parent clock for Armada 37xx peripheral clocks. Only clocks which can be disabled (.can_gate is true) can have parent or rate changed. This is needed so that Turris Mox can change SPI clock in device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
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