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2017-09-23ARM: socfpga: remove unneeded NAND config optionsMasahiro Yamada
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the NAND initialization process is driven by the driver itself. CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-09-22armv8: ls1046ardb: disable PPA loading during SPL stage for SD bootYangbo Lu
PPA loading during SPL stage is not required for nornal SD boot scenario. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: ls1043ardb: disable PPA loading during SPL stage for SD bootYangbo Lu
PPA loading during SPL stage is not required for nornal SD boot scenario. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: ls1043a: disable IFC in SPL only when QSPI is usedYangbo Lu
Current u-boot disables IFC support for SD boot on all ls1043a boards. Actually IFC only conflicts with QSPI on ls1043a hardware. Only when QSPI is used, IFC should be disabled. Otherwise, the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22board/ls2080ardb: Update board env based on SoCPriyanka Jain
As per current implementation, default value of board env is based on board filename i.e ls2080ardb. With distro support changes, this env is used to decide upon kernel dtb which is different for other SoCs (ls2088a, ls2081a) combination supported with this board. Add support to modify board env at runtime based on SoC type Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22board/ls2080ardb: Add mcmemsize variable in default envPriyanka Jain
For most of ls2080ardb use-cases, mc private DRAM block is required to be of 1.75GB. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [YS: this reservation needs to be reduced if memory is not enough] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2CSriram Dash
I2C code is put under CONFIG_SYS_I2C. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFCSriram Dash
IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22pci: layerscape: Fixup iommu-map for LS208xABharat Bhushan
Commit 0aaa1a9 added support for LS208xA devices but fixing iommu-map property is missing. This patch adds support for fixing iommu-map. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512sSantan Kumar
As per updated board design, different QSPI flash is connected on boards, hence change QSPI flash type from Micron n25q512a device to spansion s25fs512s device in dts and config. Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATESantan Kumar
CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay the prints of boardinfo late in cycle during uboot boot. This feature is not required in case of QSPI_BOOT. Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl-layerscape: Put SATA code under SATA configsAshish Kumar
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv7: ls1021a: Fix marco CONFIG_LS102XAYork Sun
Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A to CONFIG_LS102XA. Signed-off-by: York Sun <york.sun@nxp.com>
2017-09-22regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1Jean-Jacques Hiblot
In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1 IO cells. Without this bias voltage these I/O cells can not function properly. The PBIAS cell is controlled by software. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: core: Add functions to get strings and the string count from a stringlistJean-Jacques Hiblot
dev_read_string_count() is used to get the number of strings in a stringlist. dev_read_string_index() is used to get a string in the stringlist based on its position in the list. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-09-22mmc: uniphier-sd: Add support for R8A7795 and R7A7796Marek Vasut
Add OF match entries and quirks for Renesas RCar Gen3 controllers into the driver. The IP this driver handles is in fact Matsushita one and in used both in Socionext and Renesas chips. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22mmc: uniphier-sd: Add support for quirksMarek Vasut
Check if the OF match has any associated data and if so, use those data as the controller quirks, otherwise fallback to the old method of reading the controller version register to figure out the quirks. This allows us to supply controller quirks on controllers which ie. do not have version register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22mmc: uniphier-sd: Add support for 64bit FIFOMarek Vasut
The Renesas RCar Gen3 contains the same controller, originally Matsushita. This patch adds support for handling of the 64bit FIFO on this controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22mmc: uniphier-sd: Add support for 64bit controllerMarek Vasut
The Renesas RCar Gen3 contains the same controller, originally Matsushita, yet the register addresses are shifted by 1 to the left. The whole controller is also 64bit, including the data FIFOs and RSP registers. This patch adds support for handling the register IO by shifting the register offset by 1 in the IO accessor functions. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22mmc: uniphier-sd: Factor out register IOMarek Vasut
This patch prepares the driver to support controller(s) with registers at locations shifted by constant. Pull out the readl()/writel() from the driver into separate functions, where the adjustment of the register offset can be easily contained. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-09-22Travis-CI: Checkout only v1.4.3 of dtcTom Rini
Our minimum DTC version is 1.4.3, so check that out. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22net/tftp: fix build if CMD_BOOTEFI is not setJörg Krause
Fixes: net/tftp.c:811: undefined reference to `efi_set_bootdev' Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22Makefile: Update minimum dtc version to 1.4.3Tom Rini
With support for overlays and calling the -@ flag to dtc we need to have at least 1.4.3 available now. Cc: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22spl: Fix compiling warning on gunzip argumentYork Sun
common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’ from incompatible pointer type [-Wincompatible-pointer-types] src, &length)) Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-09-22arm: am33xx: Make pin multiplexing functions optionalFelix Brack
This patch provides default implementations of the two functions set_uart_mux_conf and set_mux_conf_regs. Hence boards not using them do not need to provide their distinct empty definitions. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-09-22board: Add stm32h7 SoC, discovery and evaluation boards supportPatrice Chotard
This patch adds support for stm32h7 soc family, stm32h743 discovery and evaluation boards. For more information about STM32H7 series, please visit: http://www.st.com/en/microcontrollers/stm32h7-series.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: adapt stm32h7 dts files for U-bootPatrice Chotard
This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: add stm32h743i-eval filesPatrice Chotard
This file is imported from linux kernel v4.13 Add device tree support for STM32H743 evaluation board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS and FS _ I2 C compatible serial interface _ RTC with rechargeable backup battery _ SAI Audio DAC _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash _ 1-Gbit Twin Quad-SPI NOR Flash _ Potentiometer _ 4 colored user LEDs _ Reset, wakeup, tamper or key buttons _ Joystick with 4-direction control and selector _ Board connectors : Power jack 3 USB with Micro-AB RS-232 communications Ethernet RJ45 FD-CAN compliant connection Stereo headset jack including analog microphone input 2 audio jacks for external speakers microSD™ card JTAG/SWD and ETM trace _ Expansion connectors: Extension connectors and memory connectors for daughterboard or wire-wrap board _ Flexible power-supply options: ST-LINK USB VBUS or external sources _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: DTS: stm32: add stm32h743i-disco filesPatrice Chotard
All these files are imported from linux kernel v4.13 Add device tree support for STM32H743 SoC and discovery board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS _ I2 C compatible serial interface _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM _ 1-Gbit Twin Quad-SPI NOR Flash _ Reset, wakeup, or key buttons _ Joystick with 4-direction control and selector _ Board connectors : 1 USB with Micro-AB Ethernet RJ45 Stereo headset jack including analog microphone input microSD™ card RCA connector JTAG/SWD and ETM trace _ Expansion connectors: Arduino Uno compatible Connectors 2 x PIO connectors (PMOD and PMOD+) _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: misc: add stm32 rcc driverChristophe Kerello
This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: reset: add stm32 reset driverPatrice Chotard
This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22dm: clk: add clk driver support for stm32h7 SoCsPatrice Chotard
This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22serial: stm32x7: add STM32H7 supportPatrice Chotard
STM32F7 and STM32H7 shares the same UART block, add STM32H7 compatible string. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22pinctrl: stm32: add stm32h743-pinctrl compatiblePatrice Chotard
STM32H7 SoCs uses the same pinctrl block as found into STM32F7 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-09-22spl: stash bootstage info before jump to next stageKever Yang
Since we may jump to next stage like ATF/OP-TEE instead of U-Boot, we need to stash the bootstage info before it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22board: STiH410-B2260: add fastboot supportPatrice Chotard
Add usb_gadget_handle_interrupts(), board_usb_init(), board_usb_cleanup() and g_dnl_board_usb_cable_connected() callbacks needed for FASTBOOT support Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: STiH410: update ehci and ohci compatiblePatrice Chotard
Update ehci and ohci node's compatible string in order to use ehci-generic and ohci-generic drivers. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: STiH410: set DWC3 dual role mode to peripheralPatrice Chotard
On STi 96boards, configure by default the micro USB connector (managed by DWC3 hardware block) in peripheral mode. This will allow to use fastboot feature. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22usb: dwc3: Add dwc3 glue driver support for STiPatrice Chotard
This patch adds the ST glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Part of this code been extracted from kernel.org driver (drivers/usb/dwc3/dwc3-st.c) Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22STiH410-B2260: enable USB, fastboot, reset, PHY related flagsPatrice Chotard
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22STiH410-B2260: enable USB Host NetworkingPatrice Chotard
Enable USB Host Networking support by enabling Ethernet/USB adaptors support and by enabling some BOOTP flags Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22usb: phy: Add STi USB2 PHYPatrice Chotard
This is the generic phy driver for the picoPHY ports used by USB2/1.1 controllers. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22mmc: sti_sdhci: Use reset frameworkPatrice Chotard
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22ARM: dts: stih410-family: Add missing reset_names for mmc1 nodePatrice Chotard
reset-names property is needed to use the reset API for STi sdhci driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22mmc: sti_sdhci: Rework sti_mmc_core_config()Patrice Chotard
Use struct udevice* as input parameter. Previous parameters are retrieved through plat and priv data. This to prepare to use the reset framework. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-22pci: Remove unnecessary 'default n' from KconfigTuomas Tynkkynen
'default n' is the default anyway so it doesn't need to be specified explicitly, and the rest of the file doesn't specify it either anywhere. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: layerscape: Remove unused field 'hose' from struct ls_pcieTuomas Tynkkynen
This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: tegra: Remove unused field 'hose' from struct tegra_pcieTuomas Tynkkynen
This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: xilinx: Remove unused field 'hose' from struct xilinx_pcieTuomas Tynkkynen
This field has never been used as the driver has been DM-based since the beginning. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: xilinx: Fix doc comments on config space accessorsTuomas Tynkkynen
These take the 'struct udevice *' as an argument, not the 'struct xilinx_pcie *` which is a local variable. Fix the comments to match the code. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-29 01:14:16 +0000