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2016-09-06arm: dts: update DTS files for meson-gxbb and odroid-c2Beniamino Galvani
Import DTS files and dt-bindings includes from Linux 4.8-rc1. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06pinctrl: generic: scan for "pins" and "groups" properties in sub-nodesBeniamino Galvani
In cases where the pins and groups definitions are in a sub-node, as: uart_a { mux { groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; }; }; pinctrl_generic_set_state_subnode() returns an error for the top-level node and pinctrl_generic_set_state() fails. Instead, return success so that the child nodes are tried. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-06image-fit: fix fit_image_load() OS checkAndreas Bießmann
Commit 62afc601883e788f3f22291202d5b2a23c1a8b06 introduced fpga image load via bootm but broke the OS check in fit_image_load(). This commit removes following compiler warning: ---8<--- In file included from tools/common/image-fit.c:1: /Volumes/devel/u-boot/tools/../common/image-fit.c:1715:39: warning: use of logical '||' with constant operand [-Wconstant-logical-operand] os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA || ^ ~~~~~~~~~~~~ /Volumes/devel/u-boot/tools/../common/image-fit.c:1715:39: note: use '|' for a bitwise operation os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA || ^~ | 1 warning generated. --->8--- Signed-off-by: Andreas Bießmann <andreas@biessmann.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-06serial: bcm283x_mu: Detect disabled serial deviceAlexander Graf
On the raspberry pi, you can disable the serial port to gain dynamic frequency scaling which can get handy at times. However, in such a configuration the serial controller gets its rx queue filled up with zero bytes which then happily get transmitted on to whoever calls getc() today. This patch adds detection logic for that case by checking whether the RX pin is mapped to GPIO15 and disables the mini uart if it is not mapped properly. That way we can leave the driver enabled in the tree and can determine during runtime whether serial is usable or not, having a single binary that allows for uart and non-uart operation. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06bcm2835_gpio: Implement GPIOF_FUNCAlexander Graf
So far we could only tell the gpio framework that a GPIO was mapped as input or output, not as alternative function. This patch adds support for determining whether a function is mapped as alternative. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2016-09-06warp7: Print secure/non-secure mode infoFabio Estevam
warp7 has two targets: - warp7_defconfig: boots in non-secure mode - warp7_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Use PARTUUID to specify the rootfs locationFabio Estevam
warp7 can run different kernel versions, such as NXP 4.1 or mainline. Currently the rootfs location is passed via mmcblk number and the problem with this approach is that the mmcblk number for the eMMC changes depending on the kernel version. In order to avoid such issue, use UUID method to specify the rootfs location. Succesfully tested booting a NXP 4.1 and also a mainline kernel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Add a secure mode targetFabio Estevam
NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mx6ul_14x14_ev: Enable the CCGR clocks earlierFabio Estevam
To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init(). Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD"). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Tested-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6ul_14x14_evk: Adjust SPL DDR3 settingsFabio Estevam
Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6ul_14x14_evk: Pass refsel and refr fields to avoid hangFabio Estevam
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq. This hang issue does not happen on the NXP U-Boot version. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 --> Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6: ddr: Allow changing REFSEL and REFR fieldsFabio Estevam
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx7dsabresd: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mx7dsabresd: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06pico-imx6ul: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06ARM: board: cm_fx6: fix mtd partition fixupChristopher Spinrath
ft_board_setup may return early in the case that the board revision cannot be obtained. In that case it is assumed that no revision specific correction in the fdt is neccessary. But the mtd partitions will not be fixed up either altough they are not revision specific. Move the call to fdt_fixup_mtdparts in front of the revision specific part to ensure that the partitions are fixed up even if the board revision cannot be obtained. While on it, fix a spelling mistake in a comment introduced by the same commit. Fixes: 62d6bac66038 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt") Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>
2016-09-06mx6ul_14x14_evk: don't use array for SD2 card detect padEric Nelson
Only a single pad is changed to change sdhc2_dat3 from an SDIO pin to and from GPIO4:5, so remove the array and use the imx_iomux_v3_setup_pad() routine. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Modify fdt_file environment variableBreno Lima
Use imx7s-warp.dts as fdt_file because this is the name that upstream kernel will deploy. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp: Fix RAM size runtime detectionFabio Estevam
Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
2016-09-06warp7: Add PMIC supportVanessa Maegima
Add PMIC support. Tested by command "pmic PFUZE3000 dump". Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat
Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
2016-09-06mx7dsabresd: Print secure/non-secure mode infoFabio Estevam
mx7dsabresd has two targets: - mx7dsabresd_defconfig: boots in non-secure mode - mx7dsabresd_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mtd: nand: mxs: fix cache alignment for cache lines >32Stefan Agner
Currently the command buffer gets allocated with a size of 32 bytes. This causes warning messages on systems with cache lines bigger than 32 bytes: CACHE: Misaligned operation at range [9df17a00, 9df17a20] Define command buffer to be at least 32 bytes, but more if cache line is bigger. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06imx: ventana: enable splashscreen supportTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2016-09-06board: tbs2910: fix HDMI pre-console bufferSoeren Moch
HDMI output must be enabled very early to also enable the pre-console buffer Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06board: tbs2910: always enable usbkbdSoeren Moch
'usb start' is much faster now, so always enable usb keyboard Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini
2016-09-06Merge git://git.denx.de/u-boot-nand-flashTom Rini
2016-09-06ARM: dts: dra72-evm: fix broken ethernetMugunthan V N
With commit ceec08f50b6, phy is connected to slave 0, but changing the phy node was missed, fix it by populating the phy node to proper cpsw slave node. Fixes: ceec08f50b6 ("ARM: dts: dra72-evm: Add mode-gpios entry for mac node") Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Tom Rini <trini@konsulko.com>
2016-09-06sunxi: fix 64-bit compiler warning for SPL header parsingAndre Przywara
Casting "int"s to pointers is only valid for 32-bit systems. Add the appropriate pointer type cast to avoid a compiler warning when compiling for AArch64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-06sunxi: Kconfig: rename non-existent SUN50I_A64 config symbolAndre Przywara
There is no "CONFIG_MACH_SUN50I_A64" in upstream U-Boot, so fix the name to prevent the option to be enabled. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-06Revert "sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80"Andre Przywara
This commit moved the SPL stack into SRAM C, which worked when the SPL set the AHB1 clock down to 100 MHz to cope with the flaky SRAM C access from the CPU. However booting with boot0 (and thus not using SPL at all) we still run with a 200 MHz AHB1, so any access to SRAM C is prone to fail. Since this commit does _not_ only affect the SPL code, but also the U-Boot proper, we fail when booting with boot0. As the introduction of tiny-printf reduced the size of the SPL, we can afford to have the SPL stack in SRAM A1. This reverts commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34 and fixes booting the Pine64 when using boot0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Add defconfig and dts file for the Orange Pi Plus2E SBCHans de Goede
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. The dts file is identical to the one submitted to the upstream kernel, except that it has the pending patch to enable the ethernet controller squashed in, as u-boot already has sun8i-emac support. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Enable emac on H3 orangepi boardsHans de Goede
The Orange Pi 2 and Orange Pi Plus also come with ethernet, enable support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Sync h3-orangepi dts files with kernelHans de Goede
This adds an emac node to the orangepi-2 dts (not yet merged upstream, but in u-boot we already have emac support); fixes the alphetically sorting of nodes in sun8i-h3-orangepi-plus.dts and disables some usb controllers in sun8i-h3-orangepi-plus.dts which are only used on the plus2e, as upstream has decided to do a separate dts files for the plus2e. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Fix H3 EMAC syscon register addressChen-Yu Tsai
The sun8i-emac driver follows an old version of the proposed DT bindings, where the EMAC clock and EPHY control register range is listed directly, rather than through a syscon phandle. Add back the syscon register range to avoid an invalid data access. We should fix the driver once the Linux kernel bindings have been finalized. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Add support for A33-OLinuXino boardStefan Mavrodiev
A33-OLinuXino is A33 development board designed by Olimex LTD. It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector, headphone and mic jacks, connector for LiPo battery and optional 4GB NAND Flash. It has two 40-pin headers. One for LCD panel, and one for additional modules. Also there is CSI/DSI connector. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: Add iNet D978 rev2 defconfigIcenowy Zheng
The iNet D978 rev2 is a tablet board designed by iNet, which is intended to use on 10" tablets with a appearance like Apple iPad. It has A33 SoC, 1GB RAM, 8GB/16GB NAND, SDIO Wi-Fi, a MicroUSB port and a MicroSD slot. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-03sunxi: add proper device tree for iNet D978 rev2 boardsIcenowy Zheng
Add a proper dts for the iNet D978 rev2 based A33 tablets. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-01nand: Fix some more NULL name testsScott Wood
Now that nand_info[] is an array of pointers we need to test the pointer itself rather than using name as a proxy for NULLness. Fixes: b616d9b0a708eb9 ("nand: Embed mtd_info in struct nand_chip") Signed-off-by: Scott Wood <oss@buserror.net> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Tony Lindgren <tony@atomide.com>
2016-09-01nand: Fix nand info for no deviceTony Lindgren
Looks like we have few more places where we're testing for nand_info[i]->name. We can now use just test for nand_info[i] instead. This fixes a data abort on devices with no NAND when doing nand info. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-01mtd: nand: pxa3xx: use nand_set_controller_dataChris Packham
In commit 17cb4b8f327e ("mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data") the assignment of mtd->priv was removed but was not replaced. This adds the required nand_set_controller_data() call. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2016-09-01ARM: tegra: Add support for TK1-SOM board from Colorado EngineeringPeter Chubb
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-30ARM: tegra: use numeric versioning for p2771-0000Stephen Warren
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-30x86: qemu: efi: Add two boards for EFI 32-bit and 64-bit payloadBin Meng
This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: efi: Fix EFI 64-bit payload build warningsBin Meng
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: efi: payload: Make EFI payload build againBin Meng
Since commit 73c5c39 "Makefile: Drop unnecessary -dtb suffixes", EFI payload does not build anymore. This fixes the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: Add debugging when cpu_common_init() failsSimon Glass
Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30x86: ivybridge: Allow microcode to be collatedSimon Glass
Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30x86: Add debugging when a microcode update failsSimon Glass
Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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