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2015-12-03sparc: leon3: Move ambapp_bus_init() call to arch_cpu_init() functionFrancois Retief
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: leon3: Move snoop detection from startup.S to arch_cpu_init()Francois Retief
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: Initial ground work for generic board initializationFrancois Retief
Initial ground work in preperation for generic board initialization code for the SPARC architecture. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: Fix whitespace in cpu/leon2/cpu_init.cFrancois Retief
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: leon3: Updated serial driver to use CONFIG_CONS_INDEXFrancois Retief
Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX option to select which serial port the console will use. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: Serial baud rate register support multiple buses with different frequencyDaniel Hellstrom
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failureFrancois Retief
Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the panic function can use DEBUG_UART driver. drivers/serial/serial.c set this flag before calling this function, preventing DEBUG_UART code from running. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: Added function that checks if IRQ is on or offDaniel Hellstrom
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
2015-12-03sparc: Remove version_string variable from start.S fileFrancois Retief
Remove the version_string variable from start.S file. A weak variable is also set in the cmd_version.c file. No need for architecture override. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-03sparc: Move SYS_SPARC_NWINDOWS to KconfigFrancois Retief
Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
2015-12-02Revert "LCD: Add an option to skip registration as an stdio output"Anatolij Gustschin
This reverts commit 05bfe1321024e2ae0039dc16f17d2165610fb4fd. As discussed on the list, we already have the needed functionality by defining CONFIG_SYS_CONSOLE_IS_IN_ENV, CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE and adding custom overwrite_console() in the board code. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2015-12-01iocon: Disable FIT_VERBOSETom Rini
In order to fit into image constraints again, remove this feature. Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-01arm: imx6: novena: Enable extfs support in SPLMarek Vasut
Simple patch to enable support for extfs filesystem in SPL, this is useful to those who want to avoid vfat like plague. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2015-12-01arm: imx6: novena, gw_ventana: Fix use of pfuze100 bit definitionsMarek Vasut
The following patch changed the PFUZE100 swbst register bit definitions and broke PMIC configuration on multiple boards, at least on the novena and gw_ventana. This patch fixes it. commit 8fa46350a4c7dca7710362f6c871098557b934ad Author: Peng Fan <Peng.Fan@freescale.com> Date: Fri Aug 7 16:43:45 2015 +0800 power: regulator: add pfuze100 support Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
2015-12-01rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LENSjoerd Simons
Now that u-boot relocates the malloc area in SPL to SDRAM, with the malloc area sitting below the SPL_STACK_R_ADDR the SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then STACK_R_MALLOC_SIMPLE_LEN (1Mb). Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot from SD card. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons
This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro
Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: doc: show packet rk3036 uboot imagehuang lin
show how to packet rk3036 uboot image and boot from SD Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Series-to: u-boot Series-version: 8 Series-cc: Lin Huang <hl@rock-chips.com>
2015-12-01rockchip: Add support for rk's second level loaderJeffy Chen
The Rockchip boot ROM could load & run an initial spl loader, and continue to load a second level boot-loader(which stored right after the initial loader) when it returns. Modify idblock generation code to support it. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: Add max spl size & spl header configsJeffy Chen
Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
2015-12-01rockchip: Add basic support for evb-rk3036 boardhuang lin
This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
2015-12-01rockchip: rk3036: Add core Soc start-up codehuang lin
rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-12-01rockchip: add rk3036 sdram driverhuang lin
add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: add early uart driverhuang lin
add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin
rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
2015-12-01rockchip: mmc: use non-removable property to distinguish emmc and sdcard ↵huang lin
register emmc and sdcard have different register address, use non-removeable property to distinguish them. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01mmc: dw_mmc: support fifo mode in dwc mmc driverhuang lin
some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01mmc: dw_mmc: move data transfer as a separate functionhuang lin
the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add pinctrl driverhuang lin
Add a driver which support pin multiplexing setup for rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add a simple syscon driverhuang lin
Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add Soc reset driverhuang lin
We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add header files for GRFhuang lin
GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rk3036: Add clock driverhuang lin
Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: Bring in RK3036 device tree file includes and bindingshuang lin
Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: serial driver support rk3036huang lin
Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01dm: core: Add SPL Kconfig for REGMAP and SYSCONhuang lin
Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: add config decide whether to build common.chuang lin
some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: rename board-spl.c to rk3288-board-spl.chuang lin
since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin
since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: add timer driverhuang lin
some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: firefly: Save the environment on SD cardSjoerd Simons
Save the environment on the SD card for Firefly in the empty space between the SPL and the u-boot image. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01rockchip: Also load the initrd below 512MSjoerd Simons
Similar to load an fdt, when loading an initrd about the 512Mb mark things seem to break. For now force loading below 512Mb until the reason why this fails has been determined/solved. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01ARM: mxs: fix VDDD brownout settingMichael Heimpold
At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2015-12-01dm: pci: Disable PCI compatibility functions by defaultSimon Glass
We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Convert 'pci' command to driver modelSimon Glass
Adjust this command to use the correct PCI functions, instead of the compatibility layer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01pci: Move PCI header output code into its own functionSimon Glass
We want to share this code with the driver model version, so put it in a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01pci: Use a separate 'dev' variable for the PCI deviceSimon Glass
In the 'pci' command, add a separate variable to hold the PCI device. When this code is converted to driver model, this variable will be used to hold a struct udevice instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01pci: Use common functions to read/write configSimon Glass
Currently we use switch() and access PCI configuration via several functions, one for each data size. Adjust the code to use generic functions, where the data size is a parameter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01pci: Tidy up function comments in cmd_pci.cSimon Glass
The function comments use an old style and some are incorrect. Update them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01dm: pci: Reorder functions in cmd_pci.cSimon Glass
Before converting this to driver model, reorder the code to avoid forward function declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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