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2020-04-06arm64: zynqmp: Sync DP subsystemMichal Simek
Sync DP subsystem with the latest state in Xilinx U-Boot repository. This binding hasn't been approved in mainline Linux but it is much better than ancient version which this patch removes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Do not duplicate flash partition label propertyAmit Kumar Mahapatra
In kernel 5.4, support has been added for reading MTD devices via the nvmem API. For this the mtd devices are registered as read-only NVMEM providers under sysfs with the same name as the flash partition label property. So if flash partition label property of multiple flash devices are identical then the second mtd device fails to get registered as a NVMEM provider. This patch fixes the issue by having different label property for different flashes. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: dts: zynqmp: Add clk cells for sdhciAshok Reddy Soma
Add clock-cells and clock-output-names for sdhci0 and sdhci1. These are needed for linux sdhci driver from 5.4 version onwards. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Remove second copy of reset-controllerMichal Simek
Reset controller is handled via firmware that's why it should be the part of firmware node. Origin solution hasn't been removed when above change was applied by commit b07e97b4ba27 ("arm64: zynqmp: Use reset header in zynqmp.dtsi"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Add 'no-1-8-v' property for ZynqMP BoardsManish Narani
Modify dts files to add 'no-1-8-v' property for all the ZynqMP boards. User can remove this property to enable the UHS mode. This is to keep the same speed (HS) modes across all the stages of the Linux Boot. Due to power cycling limitation of some of the ZynqMP boards, some SD cards don't get power cycled and are failing in Linux. Signed-off-by: Manish Narani <manish.narani@xilinx.com>
2020-04-06arm64: zynqmp: Sync zynqmp fpga manager with mainlineNava kishore Manne
Sync zynqmp fpga manager with mainline. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Remove unused zynqmp-clk.dtsiMichal Simek
All boards have been converted to firmware based driver that's why we can remove this file now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06ARM: zynq: Fix spi name nodeMichal Simek
None name address should be aligned with address. DTC 1.5.1 is reporting issues related to that. arch/arm/boot/dts/zynq-zc770-xm010.dts:106.10-119.4: Warning (spi_bus_reg): /amba/spi@e0007000/flash@0: SPI bus unit address format error, expected "1" arch/arm/boot/dts/zynq-zc770-xm013.dts:101.19-109.4: Warning (spi_bus_reg): /amba/spi@e0006000/eeprom@0: SPI bus unit address format error, expected "2" Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Update Copyright years to 2020Michal Simek
Trivial change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Replace gpio-key,wakeup with wakeup sourceMichal Simek
The same change has been done for Zynq by commit 1241c72b6db1 ("ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property") in mainline Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source propertySudeep Holla
Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the Linux kernel commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06ARM: dts: zc702: Fix I2C bus warningsQuanyang Wang
The dtc has new checks for I2C and SPI buses. Fix the warnings in node names and unit-addresses. Warning from Linux kernel: arch/arm/boot/dts/zynq-zc702.dts:187.13-190.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@52: I2C bus unit address format error, expected "34" arch/arm/boot/dts/zynq-zc702.dts:191.13-194.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@53: I2C bus unit address format error, expected "35" arch/arm/boot/dts/zynq-zc702.dts:195.13-198.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@54: I2C bus unit address format error, expected "36" Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Enable cache command for mini mtest configurationMichal Simek
Enable cache commands by default for mtest configuration. It is good to be able to enable/disable caches when you test memory. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06configs: versal: Add CONFIG_DISTRO_DEFAULTS to versal defconfigT Karthik Reddy
Add DISTRO_DEFAULTS config to versal virt defconfig file which is suitable for booting general purpose Linux distributions. Remove other configs which are selected by default by DISTRO_DEFAULTS configuration. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Print multiboot register value in EL3Michal Simek
Multi boot register can be used for using different boot images and design better boot strategy. Let EL3 SPL or U-Boot to read it and print it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: dts: meson: add libretech-pc supportJerome Brunet
Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: update board/amlogic/q200/MAINTAINERS] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06arm64: dts: meson: import libretech-pc from linux v5.6-rc2Jerome Brunet
Sync the libretech-pc device tree from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06arm64: dts: meson: sync dt and bindings from v5.6-rc2Jerome Brunet
Sync the device tree and dt-bindings from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") The only exception to this is the mmc pinctrl pin bias of gxl SoC family. This is a fix which found its way to u-boot but not Linux yet. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06clk: meson: reset mmc clock on probeJerome Brunet
On some SoCs, depending on the boot device, the MMC clock block may be left in a weird state by the ROM code, in which no decent clock may be provided. Reset the related register to make sure a sane MMC clock is ready for the controller. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06mmc: meson-gx: enable input clocksJerome Brunet
Until now, the mmc clock was left in a good enough state by the ROM code to be used by the controller. However on some SoC, if the ROM code finds a bootloader on USB or SPI, it might leave the MMC clock in state the controller cannot work with. Enable the input clocks provided to the mmc controller. While the u-boot mmc controller driver is not doing fancy settings like the Linux, it at least needs to make these clocks are running. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06dt-bindings: leds: import common led bindings from linux v5.5Jerome Brunet
Import the common leds bindings definition from linux d5226fa6dbae ("Linux 5.5") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06clk: meson-g12a: missing breakHeinrich Schuchardt
Add missing break for CLKID_PCIE_PLL in switch statement. Reported by CppCheck. Cc: Neil Armstrong <narmstrong@baylibre.com> Fixes: 08e09c263fdf ("clk: meson-g12a: Add PCIE PLL support") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-05clk: socfpga: Read the clock parent's register base in probe functionChee Hong Ang
This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's ofdata_to_platdata() method before the parent is probed in dm core. This has caused the driver no longer able to get the correct parent clock's register base in the ofdata_to_platdata() method because the parent clocks will only be probed after the child's ofdata_to_platdata(). To resolve this, the clock parent's register base will only be retrieved by the child in probe() method instead of ofdata_to_platdata(). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-05ARM: dts: stm32: Temporarily drop cd-gpios from AV96 DTMarek Vasut
The card-detect GPIO and any other GPIO access currently doesn't work in U-Boot SPL on any STM32 platform and crashes the SPL. To work around this problem on AV96 right before release, remove the cd-gpios from DT. This patch must be reverted right after release, once the proper fix for the GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-04-04Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- net: sh_eth: Init the hardware before PHY access
2020-04-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- verdin-imx8mm board reST documentation update - Intel Edison board ACPI table I2C/USB minor updates - Fix a regression of ns16550 serial driver that breaks Intel Edison
2020-04-04serial: ns16550: Fix ordering of getting base addressBin Meng
Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-04x86: acpi: Describe USB 3 host controller found on Intel TangierAndy Shevchenko
USB 3 host controller may be described in ACPI to allow users alter the properties or other features. Describe it for Intel Tangier SoC. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-04x86: acpi: Add I²C timings to Intel Merrifield platformAndy Shevchenko
There is established way to provide I²C timings, or actually counters, to the OS via ACPI. Fill them for Intel Merrifield platform. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-04doc: board: verdin-imx8mm: use mainline TF-AIgor Opaniuk
1. Update build steps where mainline Trusted Firmware A is used. 2. Fix BL31_BASE to the proper one according to the SoC reference manual. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-04x86: acpi: Refactor XSDT handling in acpi_add_table()Andy Shevchenko
There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-04net: sh_eth: Init the hardware before PHY accessMarek Vasut
To access the PHY, the MAC registers must be initialized. Call the init function in probe() to make it so, otherwise the PHY ID readout returns all zeroes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-04-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegraTom Rini
- Add support for Jetson Nano, plus miscellaneous other fixes found during Nano bringup. - Add Igor's update_uboot wrapper patches.
2020-04-03arch: Add explicit linker script for u-boot-elfMichal Simek
Commit f4dc714aaa2d ("arm64: Turn u-boot.bin back into an ELF file after relocate-rela") introduce REMAKE_ELF option to recreate u-boot.elf from u-boot -> u-boot.bin + DT -> u-boot.elf. The best is to ilustrate it from make V=1 output cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin cp u-boot-dtb.bin u-boot.bin aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf --defsym="_start"=0x8000000 -Ttext=0x8000000 Last command has no explicit linker script passed that's why toolchain internal linker script is used. In Binutils 2.32 case it contains SIZEOF_HEADERS symbol which has changed behavior by commit https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=64029e93683a266c38d19789e780f3748bd6a188 which result in situation that program headers has changed from (xilinx_zynqmp_mini_defconfig) Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000010000 0x00000000fffc0000 0x00000000fffc0000 0x0000000000018918 0x0000000000018918 RW 0x10000 to Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000000 0x00000000fffb0000 0x00000000fffb0000 0x0000000000028918 0x0000000000028918 RW 0x10000 Xilinx tools like XSDB or Bootgen are using program headers for loading ELF to the right location and by above binutils change ELF is loaded to incorrect location. The patch is explicitly use u-boot-elf.lds (just cat now) for u-boot.elf recreation which is called when REMAKE_ELF is setup. By purpose u-boot-elf.lds doesn't contain OUTPUT_FORMAT/OUTPUT_ARCH to be able to use by all archs. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-By: Álvaro Fernández Rojas <noltari@gmail.com>
2020-04-03mach-snapdragon: Fix overwriting last digit of serial numberJan-Christoph Tebbe
When generating the MAC address based on the boards serial number the last digit was overwritten with the null termination. That way boards with serial numbers close to each other would use the same MAC address. Signed-off-by: Jan-Christoph Tebbe <Jan-Christoph.Tebbe@ithinx.io>
2020-04-03Revert "common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled"Ye Li
Commit cf8dcc5d02c3 ("common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable image. Actually when using TINY FIT, the first loadable image is thought as u-boot and already have fdt appended. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fabio Estevam <festevam@gmail.com>
2020-04-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- fix for MMIO window size (Tudor Ambarus)
2020-04-02ARM: tegra: Add NVIDIA Jetson Nano Developer Kit supportTom Warren
The Jetson Nano Developer Kit is a Tegra X1-based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. NVMe support has also been added. Env save is at the end of QSPI (4MB-8K). A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02mtd: spi: Add Macronix MX25U3235F deviceTom Warren
Add Macronix MX25U3235F flash device description. This is a 4MiB part. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02t210: Adjust ramdisk_addr_r/fdt_addr_r to allow for large kernelsTom Warren
The L4T kernel is 32MB+, and can overwrite the ramdisk/fdt loaded from extlinux.conf. Adjust the load addresses to fix this for now. Using the calculated_env addresses table from T186 U-Boot is a better fix, but it isn't working correctly on T210 U-Boot right now, so this will do until I can fix it. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02qspi: t210: Use dev_read calls to get FDT data like base, freqTom Warren
This Tegra QSPI driver hadn't been brought up to date with how DM drivers are fetching data from the FDT now, and was pulling in bogus data for base, max freq, etc. Fixed ofdata_to_platdata to work the same way it does in the tegra114 SPI driver, using dev_read_ functions. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02qspi: t210: Fix QSPI clock and tap delaysTom Warren
When claim_bus was setting the clock, it reset the QSPI controller, which wipes out any tap delays set by previous bootloaders (nvtboot, CBoot for example on Nano). Instead of doing that in claim_bus, which gets called a lot, moved clock setting to probe(), and set tap delays there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env save works reliably again. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02qspi: t210: Fix claim_bus's use of the wrong bus/deviceTom Warren
claim_bus() is passed a udevice *dev, which is the bus device's parent. In this driver, claim_bus assumed it was the bus, which caused the 'priv' info pointer to be wrong, and periph_id was incorrect. This in turn caused the periph clock call to assign the wrong clock (PLLM instead of PLLP0), which caused a kernel warning. I only saw the 'bad' periph_id when enabling DEBUG due to an assert. Not sure how QSPI was working w/this errant clock, but it was moot as QSPI wasn't active unless you probed it, and that wasn't happening until I posted a patch to enable env save to QSPI for Nano (coming soon). Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detectTom Warren
According to the HW team, for some reason the normal clock select code picks what appears to be a perfectly valid 375KHz SD card clock, based on the CAR clock source and SDMMC1 controller register settings (CAR = 408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register divisor of 16 = 375KHz). But the resulting SD card clock, as measured by the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on T210 when the requested clock is <= 400KHz. Note that as far as I can tell, the other requests for clocks in the Tegra MMC driver result in valid SD clocks. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02mmc: t210: Add autocal and tap/trim updates for SDMMC1/3Tom Warren
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and autocal values need to be set to condition the signals correctly before talking to the SD-card. This is the same as what's being done in CBoot, but it gets reset when the SDMMC1 HW is soft-reset during SD driver init, so needs to be repeated here. Also set autocal and tap/trim for SDMMC3, although no T210 boards use it for SD-card at this time. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boardsTom Warren
This allows the user to set $serverip in the environment before executing a DHCP request. If they do, U-Boot will use that IP rather than using the IP in the DHCP response. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02ARM: tegra: p2771-0000: enable PIE relocationVishruth
U-Boot is configured to build as position independent executable. Enable relocation of RELA section required to work with different load addresses. Signed-off-by: Vishruth <vishruthj@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Peter Robinson <probinson@gmail.com>
2020-04-02i2c: t210: Add VI_I2C clock source supportTom Warren
Fix VI_I2C clock source type. Will be needed by VI_I2C driver. Also added use of INTERNAL_ID macro in two places, needed to keep the id returned to 8 bits. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02t210: pinmux: Remove pinmux/GPIO init from T210 boardsTom Warren
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB tables. Remove pinmux/GPIO init tables & code from all T210-based builds below: p2371-2180 aka TX1 p2371-0000 e2220-1170 p2571 Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02t210: do not enable PLLE and UPHY PLL HW PWRSEQJC Kuo
This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
generated by cgit (git 2.34.1) at 2024-12-27 20:26:38 +0000