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2019-06-20aspeed/watchdog: Correct timeout valueJoel Stanley
The driver was using milliseconds and programming it into a register which takes ticks of the watchdog clock, which runs at 1MHz. This meant we were off by 1000 with the desired value. When 06985289d452 ("watchdog: Implement generic watchdog_reset() version") was added the aspeed board would leave the watchdog running, causing it to bite before u-boot was done. Discovered by booting in qemu: $ qemu-system-arm -M ast2500-evb -drive file=test.img,format=raw,if=mtd -nographic -no-reboot -d cpu_reset U-Boot 2019.07-rc3-00091-g2253e40caef5 (Jun 06 2019 - 16:53:23 +0930) Model: Aspeed BMC DRAM: 496 MiB WDT: Started with servicing (60s timeout) MMC: In: serial@1e784000 Out: serial@1e784000 Err: serial@1e784000 Watchdog timer expired. Fixes: 06985289d452 ("watchdog: Implement generic watchdog_reset() version") Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-06-20armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER checkMian Yousaf Kaukab
Fixes: 8163faf952 ARMv8: add optional Linux kernel image header Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Andreas Färber <afaerber@suse.de>
2019-06-20MAINTAINERS: Update git repo linksBin Meng
Update all git repo links with the new gitlab ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Wolfgang Denk <wd@denx.de>
2019-06-20sh: Add myself as SH maintainerMarek Vasut
Add myself as an SH maintainer. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com>
2019-06-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- PCIe driver change to support DM model - T2080QDS migrated to use PCIe DM model
2019-06-20Merge tag 'u-boot-stm32-20190619' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Update STM32MP entry in MAINTAINERS - Handle correctly binding for g-tx-fifo-size for USB DWC2 driver - Fix trusted STM32MP1 defconfig with correct ethernet driver
2019-06-20Merge tag 'mmc-6-19' of https://github.com/MrVan/u-bootTom Rini
- Avoid HS400 mode when accessing boot partitions
2019-06-20configs: T2080QDS: Enable PCIe driverHou Zhiqiang
Enable the DM PCIe driver in T2080QDS defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: T208xQDS: Disable legacy PCIe driver when DM_PCI is enabledHou Zhiqiang
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20dm: pci: add Freescale PowerPC PCIe driverHou Zhiqiang
Add PCIe DM driver for Freescale PowerPC PCIe controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20t2080: dts: Added PCIe DT nodesHou Zhiqiang
T2080 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: T208xQDS: Compile the legacy PCIe routines conditionallyHou Zhiqiang
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Update the condition to compile PCI routinesHou Zhiqiang
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to KconfigHou Zhiqiang
Use the Kconfig option to select the PCIe reset errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-20powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to KconfigHou Zhiqiang
Use the Kconfig option to select the PCIe ASPM errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
2019-06-19usb: dwc2: allow peripheral mode for OTG configurationPatrick Delaunay
Allow device mode in DWC2 driver when device tree select the dr_mode "peripheral" or "otg". The device mode is not allowed when dr_mode = "host" in device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-06-19ARM: dts: stm32mp1: remove override for g-tx-fifo-sizePatrick Delaunay
Remove the override for usbotg_hs on g-tx-fifo-size as the correct binding, used in the kernel device tree, is now supported in dwc2 device driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-06-19usb: dwc2: correctly handle binding for g-tx-fifo-sizePatrick Delaunay
Manage g-tx-fifo-size as a array as specify in the binding. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Marek Vasut <marex@denx.de>
2019-06-19board/freescale/common: secure_boot: Set bootdelay to -2.Udit Agarwal
Uboot prompt must not be available while running secure boot. TO ensure this bootdelay must be set to -2. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls2088ardb: Fix MC firmware loading during SD bootWasim Khan
During SD boot, MC firmware and DPC are copied from SD card to DDR. Size reserved between MC and DPC firmware on DDR is 1MB. If the size of MC firmware(load address 0x80000000) is more than 1 MB then part of MC firmware will be overwritten by DPC firmware (load address 0x80100000). Fix: Update the MC/DPL/DPC firmware's DDR address as per their respective addresses in SD card. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls2088aqds: Fix MC firmware loading during SD bootWasim Khan
During SD boot, MC firmware and DPC are copied from SD card to DDR. Size reserved between MC and DPC firmware on DDR is 1MB. If the size of MC firmware(load address 0x80000000) is more than 1 MB then part of MC firmware will be overwritten by DPC firmware (load address 0x80100000). Fix: Update the MC/DPL/DPC firmware's DDR address as per their respective addresses in SD card. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls2088aqds: Add bootcmd for TFA bootWasim Khan
Add bootcmd for IFC NOR boot and SD boot. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu
Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19configs/ls1046ardb_*: disable CONFIG_SPI_FLASH_USE_4K_SECTORSMaciej Pijanowski
With this setting enabled, the on-board QSPI cannot be properly flashed. There are no error messages, but the simple write / read / compare tests fail. This is already disabled in the qspi and tfa defconfigs for the LS1046ARDB platform. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19configs: Unset CONFIG_SPI_FLASH_BAR, move CONFIG_FSL_QSPI to defconfigAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: fix config dependency for layerscape pci codeAlex Marginean
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Change bootcmd update logicPankit Garg
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19ls1046ardb: Add CONFIG_ENV_ADDR to init env in qspi bootPankit Garg
Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Update qspi clk cfgPankit Garg
Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19ARM: dts: ls1021a: Fixed reg for sata nodePeng Ma
This patch is to fixed the reg read to "0" for armv7 architecture. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8/fsl-layerscape: Add loop to check L3 dcache statusMeenakshi Aggarwal
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable eSDHC controllersYinbo Zhu
This patch is to enable esdhc controllers for lx2160aqds Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add secure boot defconfigYuantian Tang
Add secure boot defconfig for ls1028aqds and ls1028ardb boards. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board: lx2160a: use default scan_dev_for_bootMian Yousaf Kaukab
Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board: lx2160a: fix fsl-mc status in fdt with bootefiMian Yousaf Kaukab
fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add ecc address node for sata.Peng Ma
Move the ecc addr from driver to dts Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabledYangbo Lu
u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not. config BLK bool "Support block devices" depends on DM default y if DM_MMC When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch3: add clock support for the second eSDHCYangbo Lu
Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: lx2160aqds: Enable sataPeng Ma
Change sata node status to enable sata. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add other serdes protocal supportXiaowei Bao
Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB errarum A-009007Yinbo Zhu
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB erratum A-008997Ran Wang
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19board/fsl/layerscape: Modify the aliases namesPankaj Bansal
when compiling dts file using DTC_FLAG='-@', the device tree compiler reports these warnings: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Fixed the node aliases to silence these warnings. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19mmc: Avoid HS400 mode when accessing boot partitionsMarek Vasut
U-Boot code currently only applies this restriction to HS200 mode, extend this to HS400 mode as well. Currently U-Boot code not support accessing boot partition in HS200/400 mode. This needs more check. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-18MAINTAINERS: Remove Christophe Kerello from STM32MP entryPatrice Chotard
Christophe will not have maintainer activities, so remove its name. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Christophe Kerello <christophe.kerello@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com>
generated by cgit (git 2.34.1) at 2024-12-24 12:43:54 +0000