summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-12-06x86: fdt: Create basic .dtsi file for corebootSimon Glass
This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctlyGabe Black
We will use coreboot.dtsi as our fdt include file. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Add support for CONFIG_OF_CONTROLGabe Black
Allow a device tree to be provided through the standard mechanisms. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loadingStefan Reinauer
This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loadinlg of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
2012-12-06x86: Add back cold- and warm-boot flagsGabe Black
These were removed, but actually are useful. Cold means that we started from a reset/power on. Warm means that we started from another U-Boot. We determine whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point). We plumb the result through to the global data structure. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Override calculate_relocation_address to use the e820 mapGabe Black
Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Make calculate_relocation_address an overridable functionGabe Black
Different systems may have different mechanisms for picking a suitable place to relocate U-Boot to. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Make the upper bound on relocated symbols closed instead of openGabe Black
This seems to be a bug. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Reorder x86's post relocation memory layoutGabe Black
This changes the layout in decreasing addresses from: 1. Stack 2. Sections in the image 3. Heap to 1. Sections in the image 2. Heap 3. Stack This allows the stack to grow significantly more since it isn't constrained by the other u-boot areas. More importantly, the generic memory wipe code assumes that the stack is the lowest addressed area used by the main part of u-boot. In the original layout, that means that u-boot tramples all over itself. In the new layout, it works. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Initialise SPI if enabledGabe Black
If we have SPI support, make sure that we init it. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vic Yang <victoryang@chromium.org>
2012-12-06x86: Implement arch_phys_memset so that it can wipe memory above 4GBGabe Black
Implement arch_phys_memset so that it can set memory at physical addresses above 4GB using PAE paging. Because there are only 5 page tables in PAE mode, 1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The tables must be 4K page aligned and are declared that way, and because U-Boot starts as 4K aligned and the relocation code relocates it to a 4K aligned address, the tables work as intended. While paging is turned on, all 4GB are identity mapped except for one 2MB page which is used as the window into high memory. This way, U-Boot will continue to work as expected when running code that expects to access memory freely, but the code can still get at high memory through its window. The window is put at 2MB so that it's 2MB page aligned, low in memory to be out of the way of things U-Boot is likely to care about, and above the lowest 1MB where lots of random things live. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06Introduce arch_phys_memset which works like memset but on physical memoryGabe Black
The default implementation of this function is just memset, but other implementations will be needed when physical memory isn't accessible by U-Boot using normal addressing mechanisms. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Increase the size of the phys_size_t and phys_addr_t typesGabe Black
These types should be 64 bits long to reflect the fact that physical addresses and the size of physical areas of memory are more than 32 bits long. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Fix off-by-one error in do_elf_reloc_fixups()Duncan Laurie
The use of post-increment with a do-while loop results in the loop going one step too far when handling relocation fixups. In about 1/100 cases this would cause it to hang. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Ignore memory >4GB when parsing Coreboot tablesDuncan Laurie
U-boot is unable to actually use that memory and it can cause problems with relocation if it tries to. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass
Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Fix indirect jmp warning in zimage.cSimon Glass
This fixes the following warning: zimage.c:312: Warning: indirect jmp without `*' Also fixed these warnings to keep checkpatch quiet: warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer
This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Import MSR/MTRR code from LinuxGraeme Russ
Imported from Linux 3.1 with a few modifications to suit U-Boot Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Provide a function to clean up just before booting a zimageStefan Reinauer
This function can be used by boards which want to do some clean-up before booting a zImage. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Add basic cache operationsStefan Reinauer
Add functions to enable/disable the data cache. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Fill in the dram info using the e820 map on coreboot/x86Gabe Black
This way when that dram "banks" are displayed, there's some useful information there. The number of "banks" we claim to have needs to be adjusted so that it covers the number of RAM e820 regions we expect to have/care about. This needs to be done after "RAM" initialization even though we always run from RAM. The bd pointer in the global data structure doesn't automatically point to anything, and it isn't set up until "RAM" is available since, I assume, it would take too much space in the very constrained pre-RAM environment. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Add a CBMEM timestamp generated right before the kernel startup.Vadim Bendebury
To maintain the initialization state of the timestamp facility, thesq pointer to the CBMEM section containing the timestamp table should be kept in the .data section (so that it is maintained across u-boot relocation). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable coreboot timestamp facility support in u-boot.Vadim Bendebury
This change turns on the code which allows u-boot to add timestamps to the timestamp table created by coreboot. Since u-boot does not use the tsc_t like structure to represent HW counter readings, this structure is being replaced by 64 bit integer. The timestamp_init() function is now initializing the base timer value used by u-boot to calculate the HW counter increments. Timestamp facility is initialized as soon as the timestamp table pointer is found in the coreboot table. The u-boot generated timer events' ID will start at 1000 to clearly separate u-boot events from coreboot events in the timer trace. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Add function to read time stamp counterVadim Bendebury
Put this function in the u-boot-x86.h header file. We could instead create timer.h perhaps. We support setting a base time, and reading the time relative to this base. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: gpio: Add additional GPIO banks to the ICH6 driverBill Richardson
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the same place across all versions. This change adds two more banks, for up to 96 GPIOS. BUT: - Not all chipsets have the same number of GPIOs - Not all chipsets have the same number of GPIO banks - Not all chipsets put the additional banks at the same offset from GPIOBASE - There so many chipset variants that it's pretty much impossible to support them all, or even keep track of the new ones. So, although this adds suppport for the additional banks that seem to work for the particular variants of CougarPoint Mobile chipsets that we've tried, there's no chance it will support everything Intel produces. Good luck. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable ICH6 GPIO controller for corebootSimon Glass
Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-064xx: Fix PCI memory mapping on CPCI405 boardsMatthias Fuchs
This patch fixes an issue with overlapping PCI regions on boards with more than 64MB RAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05Makefile: Add target for combined spl/u-boot.bin & u-boot.imgStefan Roese
This new make target "u-boot-img.bin" consists of the U-Boot SPL image with the real, full-blown U-Boot image directly attached to it. The full-blown U-Boot image has the mkimage header included, with its load-address and entry-point. This will be used by the upcoming a3m071 MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05Makefile: Add possibility to set entry-point for u-boot.imgStefan Roese
This patch enabled boards using the SPL framework to set an entry point in the U-Boot mkimage image "u-boot.img". Until now the entry point in the header has been set to 0. By setting CONFIG_SYS_UBOOT_START in the board header, boards can override this default location. This will be used by the upcoming a3m071 MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05mpc5200: Add a3m071 board supportStefan Roese
This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05mpc5200: Add SPL supportStefan Roese
This patch adds SPL booting support (NOR flash) for the MPC5200 platforms. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05env: Enable getenv_f() for SPL_BUILDStefan Roese
With this patch, getenv_f() can be included easily into the SPL binary. With this, SPL boards can now use getenv_f() to read environment variables (e.g. to detect if the OS or U-Boot shall be executed). In the approach this is done for env stored in NOR flash, as this will be used by an upcoming MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05SPL: Port SPL framework to powerpcStefan Roese
This patch enables the SPL framework to be used on powerpc platforms and not only ARM. timer_init() does not exist on PPC systems. The timer (decrementer) is initialized and enabled in interrupt_init() here. And currently interrupt_init() is called after relocation to SDRAM. Since the only powerpc SPL implementation (a3m071) doesn't need a timer, let's remove this timer_init() call for PPC systems. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese
By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-03Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini
2012-11-30x86: Don't spam POST80 codes with slow IO functionsStefan Reinauer
This patch prevents u-boot from "spamming" random progress codes on a port 80 "post card". The previous version of this patch just removed the delays in the "slow" IO functions, as they do not need to be slow, however, this patch is less intrusive. It uses another unused port that is often used by BIOSes (and the Linux Kernel) for small delay timing purposes. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass
This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Fix typo in pcat_timer.cStefan Reinauer
Fix a small comment typo. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Include types.h explicitly in the i386 version of io.hGabe Black
The i386 version of io.h depends on the phys_addr_t type which is defined in types.h. It wasn't including that explicitly, and was working presumably because the other files including it had already included types.h themselves directly or indirectly. This change fixes that. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a dummy implementation for timer_get_usGabe Black
The microsecond timer is not currently implemented, but add a dummy implementation for now. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a default implementation for cleanup_before_linux()Gabe Black
This function provides an opportunity for some last minute cleanup and reconfiguration before control is handed over to Linux. It's possible this may need to do something in the future, but for now it's left empty. It's set up as a weak symbol so it can be overridden if necessary on a case by case basis. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a minimal device tree for alex x86Gabe Black
The device tree now includes the necessary console configuration information. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add an fdt pointer to the global data structureGabe Black
This change adds a pointer to the global data structure in x86 to point to the device tree. This mirrors an identical pointer in ARM. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: video: Add coreboot framebuffer supportStefan Reinauer
Add a basic driver for the coreboot framebuffer. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Remove coreboot start16 codeSimon Glass
This file is no longer needed for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Allow compiling out realmode/bios codeGabe Black
We don't want this for coreboot, so provide a way of compiling it out. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Select stdio devices for corebootSimon Glass
We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add console command to display CBMEM console bufferVadim Bendebury
This command is useful to allow to observe messages generated by coreboot and u-boot until present. In particular it is handy when u-boot is instrumented to fall through into console mode on startup errors. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-01 09:37:57 +0000