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2020-03-31Merge branch 'next' of git://git.denx.de/u-boot-usb into nextTom Rini
2020-03-30usb: Migrate to support live DT for some driverKever Yang
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT. This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use ofnode as parameter instead of fdt offset. And all the drivers who use these APIs update to use live dt APIs at the same time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-30usb: ehci-msm: Use dev interface to get device addressKever Yang
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support live DT. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-03-30usb: dwc3-of-simple: Drop redundant inclding header fileKever Yang
The fdtdec.h is no use in this file, remove the include code. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-27Merge branch '2020-03-27-master-imports'Tom Rini
- Update a few MAINTAINERS entries - cache alignment fix in ext4 code - Two small test fixes
2020-03-27test: typo decompressionHeinrich Schuchardt
%s/decopmression/decompression/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-27MAINTAINERS: add myself as maintainer of fs/btrfsMarek Behún
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2020-03-27fs: ext4: Fix alignment of cache buffersJan Kiszka
We need to align the cache buffer to ARCH_DMA_MINALIGN in order to avoid access errors like CACHE: Misaligned operation at range [be0231e0, be0235e0] seen on the MCIMX7SABRE. Fixes: d5aee659f217 ("fs: ext4: cache extent data") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-03-27MAINTAINERS: Add usb.h entry to usbMarek Vasut
Add usb.h file into the USB list. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
2020-03-27test/py: mmc: Fix 'mmc info' testcaseHarald Seiler
Commit 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") fixed the layout of `mmc info` output. Reflect this change in the respective testcase. Also fix a typo in the documentation. Fixes: 41e30dcf8796 ("cmd: mmc: Make Mode: printout consistent") Signed-off-by: Harald Seiler <hws@denx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-27Revert "vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader."Tom Rini
Currently this causes failures of the platform when running the EFI loader tests, so disable it for now. This reverts commit af827140e5965e5bb2bcad1c53ca8419b428ff6d. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-03-26Merge tag 'u-boot-rockchip-20200327' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fixed for rv1108 and elgin-rv1108 board - Fix the keyboard from USB instead of CrOS EC
2020-03-26Merge tag 'u-boot-stm32-20200324' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm into next - stm32mp: fix command stboard - stm32mp: update kernel device tree according the part number - stm32mp: add 800 MHz profile support = stm32mp15xd and stm32mp15xf - stm32mp: set cp15 frequency in psci cpu on - stm32mp: DT alignment with Linux 5.6-rc1 - stm32mp: clk: add SPI5 support and correct CKSELR masks - stm32mp: ram: fixes on LPDDR2/LPDDR3 support and on tuning - stm32: i2c: allows for any bus frequency - sti: timer: livetree and clk API conversion
2020-03-26rockchip: mkimage: Use an existing macro instead of a decimal valueMiquel Raynal
Depending on the SoC, a header of four characters is prepended to the image. There is already a macro defining the number of characters: RK_SPL_HDR_SIZE, so use it instead of hardcoding "4". Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26rv1108: Fix boot regressionOtavio Salvador
Since commit 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") the following boot regression is seen: U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300) Model: Elgin RV1108 R1 board DRAM: 128 MiB initcall sequence 67fd12a0 failed at call 6000b927 (err=-22) This happens because the above commit missed to include the "rockchip-u-boot.dtsi" for rv1108, so include this file like it done for other Rockchip SoC dtsi's. Fixes: 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26elgin-rv1108: Avoid adc_channel_single_shot errorOtavio Salvador
Currently the following error message is seen during boot: U-Boot 2020.01-08751-g55759ae141 (Mar 09 2020 - 14:44:52 -0300) Model: Elgin RV1108 R1 board DRAM: 128 MiB APLL: 600000000 DPLL:1200000000 GPLL:1188000000 ACLK_BUS: 148500000 ACLK_PERI:148500000 HCLK_PERI:148500000 PCLK_PERI:74250000 MMC: dwmmc@30110000: 0 Loading Environment from MMC... OK In: serial@10210000 Out: serial@10210000 Err: serial@10210000 Model: Elgin RV1108 R1 board rockchip_dnl_key_pressed: adc_channel_single_shot fail! .... Since the elgin-rv1108 does not use ADC to read the download key status, select CONFIG_ROCKCHIP_BOOT_MODE_REG=0 to avoid such error. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26elgin-rv1108: Use rk_board_late_init() for GPIO settingsOtavio Salvador
Since commit 8e9a8d0d0c8c ("rockchip: elgin-rv1108: use board_early_init_f for per-boar init") the function that configure the board GPIOs is no longer called since CONFIG_BOARD_EARLY_INIT_F=y is not selected. These GPIOs do not need to be configured in such early stagem, so change it to rk_board_late_init() and also select CONFIG_BOARD_LATE_INIT=y to fix the regression. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1Otavio Salvador
In order to make the console pins more robust to noise, activate the pullups and increase its drive strength. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26rockchip: Change keyboard input from CrOS EC keyboard to a USB keyboardPeter Robinson
These boards aren't ChromeOS devices so won't have a cros-ec-keyb input as it's the keyboard available via the ChromeOS Embedded Controller. Update them to use a USB keyboard which would actually be available. Also enable the usb keyboard option for those devices that don't have it enabled already. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26rockchip: evb-rv1108: Use syscon API to get grf baseKever Yang
Use syscon API to get grf base instead of get from dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-26rockchip: elgin-rv1108: Use syscon API to get grf baseKever Yang
Use syscon API to get grf base instead of get from dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2020-03-24timer: sti: use clk API to get timer clock rateNicolas Heemeryck
Retrieve clock rate through device tree. This mimics the behavior of arm_global_timer in Linux. Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24timer: sti: convert to livetreeNicolas Heemeryck
Update STI timer to support a live tree Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24i2c: stm32f7_i2c: allows for any bus frequencyAlain Volmat
Do not limit to 3 (100KHz, 400KHz, 1MHz) bus frequencies, but instead allow for any frequency. Depending on the requested frequency (via the clock-frequency DT entry), use the spec data from either Standard, Fast or Fast Plus mode. In order to do so, the driver do not use anymore spec identifier by directly handle the requested frequency and from it retrieve the corresponding spec data to be used for the computation of the timing register. Signed-off-by: Alain Volmat <alain.volmat@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay
This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: reduce delay after BIST reset for tuningPatrick Delaunay
Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding datasheet. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1_ddr: fix self refresh disable during DQS trainingPatrick Delaunay
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not to enter in self refresh mode during the execution of this phase. Depending on settings, it can be set after the DQS training. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: update BIST config for tuningPatrick Delaunay
Update the BIST config to compute the real use mask for the real bank, row and col of the used DDR. The values are get from addrmap register value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: deactivate derating during BIST testPatrick Delaunay
The derating (timing parameter derating using MR4 read value) can't be activated during BIST test, as the MR4 read answer will be not understood by BIST (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). This patch only impacts the tuning on LPDDR2/LPDDR3, if derateen.derate_enable = 1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: add timeout for polling BISTGSR.BDDONEPatrick Delaunay
Avoid to block the tuning procedure on BIST error (not finished BIST procedure) by adding a 1000us timeout on the polling of BISTGSR.BDDONE executed to detect the end of BIST. The normal duration of the BIST test is around 5us. This patch also cleanup comments. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: don't display the prompt two timesPatrick Delaunay
Remove one "DDR>" display on command - next - step - go Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: display result for software read DQS gatingPatrick Delaunay
Display result information for software read DQS gating, the tuning 0 which be used by CubeMX DDR tuning tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDRPatrick Delaunay
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1Patrick Delaunay
This commit manages diversity for STM32M15x SOCs with: - dedicated files to support all STM32MP15 SOCs family. The differences between those SOCs are: -STM32MP151 [1]: common file. -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU. -STM32MP157 [3]: STM32MP153 + DSI + GPU. - new files to manage security diversity on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot. -Y = C means cryp IP + secure boot. - stm32mp157 pinctrl files to better manage package diversity. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24clk: stm32mp1: add SPI5_K supportPatrick Delaunay
Add clock support for SPI5, as this instance is available on extension connector of ST board. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24clk: stm32mp1: correct CKSELR masksPatrick Delaunay
Correct three masks used to access on the RCC register RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24stm32mp: psci: set cntfrq register of cpu onLudovic Barre
This path allows to set the cntfrq register of targeted cpu. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24stm32mp1: add 800 MHz profile supportPatrick Delaunay
The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A : Cortex-A7 @ 650 MHz - C : Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D : Cortex-A7 @ 800 MHz - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz This patch adds the support of STM32MP15xD and STM32MP15xF in U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: fdt: update kernel device tree according the part numberPatrick Delaunay
Update the kernel device tree for STM32MP15x product lines according the used soc and its part number, when CONFIG_OF_SYSTEM_SETUP is activated: - STM32MP15XA hasn't Crypto (cryp1/2) - STM32M151 and STM32M153 hasn't 3D GPU and DSI host - STM32M151 hasn't CAN FD and has single A7 For example: FDT: cpu 1 node remove for STM32MP151AAA Rev.B FDT: can@4400e000 node disabled for STM32MP151AAA Rev.B FDT: gpu@59000000 node disabled for STM32MP151AAA Rev.B FDT: dsi@5a000000 node disabled for STM32MP151AAA Rev.B Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: add function get_soc_namePatrick Delaunay
Add a function get_soc_name to get a string with the full name of the SOC "STM32MP15xxx Rev.x" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24board: stm32mp1: display reference only for STMicroelectronics boardPatrick Delaunay
Display the reference MBxxxx found in OTP49 only for STMicroelectronics boards when CONFIG_CMD_STBOARD is activated. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> # Conflicts: # board/st/stm32mp1/stm32mp1.c
2020-03-24board: stm32mp1: add finished good in board identifier OTPPatrick Delaunay
Update the command stboard to support the updated coding of OTP 59 with finished good. The ST product codification have several element - "Commercial Product Name" (CPN): type of product board (DKX, EVX) associated to the board ID "MBxxxx" - "Finished Good" or "Finish Good" (FG): effective content of the product without chip STM32MP1 (LCD, Wifi, …) - BOM: cost variant for same FG (for example, several provider of the same component) For example - commercial product = STM32MP157C-EV1 - Finished Good = EVA32MP157A1$AU1 Booth information are written on board and these information is also saved in OTP59: bit [31:16] (hex) => Board id, MBxxxx bit [15:12] (dec) => Variant CPN (1....15) bit [11:8] (dec) => Revision board (index with A = 1, Z = 26) bit [7:4] (dec) => Variant FG : finished good (NEW) bit [3:0] (dec) => BOM (01, .... 255) The updated command is: stboard [-y] <Board> <VarCPN> <Revision> <VarFG> <BOM> And the displayed STMicroelectronics board identification is: Board: MB<Board> Var<VarCPN>.<VarFG> Rev.<Revision>-<BOM> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: improve the error message for smcPatrick Delaunay
Add the SMC code and operation for trace on errors. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24board: stm32mp1: stboard: lock the OTP after programmingPatrick Delaunay
Lock the OTP used for board identification for the ST boards after programming. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: bsec: add permanent lock support in bsec driverPatrick Delaunay
Add BSEC lock access (read / write) at 0xC0000000 offset of misc driver. The write access only available for Trusted boot mode, based on new SMC STM32_SMC_WRLOCK_OTP. With the fuse command, the permanent lock status is accessed with 0x10000000 offset (0xC0000000 - 0x8000000 for OTP sense/program divided by u32 size), for example: Read lock status of fuse 57 (0x39) STM32MP> fuse sense 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 Set permanent lock of fuse 57 (0x39) STM32MP> fuse prog 0 0x10000039 1 Sensing bank 0: Word 0x10000039: 00000000 WARNING: the OTP lock is updated only after reboot WARING: Programming lock or fuses is an irreversible operation! This may brick your system. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24arm: stm32mp: bsec: remove unneeded testPatrick Delaunay
Remove the test offs < 0 , as offs is unsigned. This patch solves the warnings when compiling with W=1 on stm32mp1 board: In function ‘stm32mp_bsec_read’: arch/arm/mach-stm32mp/bsec.c:368:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 368 | if (offs < 0 || (offs % 4) || (size % 4)) | ^ In function ‘stm32mp_bsec_write’: arch/arm/mach-stm32mp/bsec.c:405:11: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 405 | if (offs < 0 || (offs % 4) || (size % 4)) | ^ Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24board: stm32mp1: read OTP in command stboardPatrick Delaunay
Read the value directly from the OTP and no more of the shadows to avoid the need of reboot after stboard command to have correct value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24board: stm32mp1: update command stboard on misc_write resultPatrick Delaunay
Update management of misc_write, which now return length of data after the commit 8729b1ae2cbd ("misc: Update read() and write() methods to return bytes xfered") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-23vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader.Kristian Amlie
EFI was disabled in f95b8a4b5f64f because of the missing DTB file, and indeed, the DTB file is required to load recent versions of GRUB (2.04) correctly. Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
2020-03-23Merge tag 'efi-2020-04-rc4-5' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc4 (5) This series contains bug fixes for the UEFI sub-system: * report correct variable length in GetNextVariable() * correct copying direction if freestanding memmove() * remove const for parameter of GetNextVariableName() * correct function descriptions Unit tests are added and adjusted.