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2020-07-06Prepare v2020.07Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-06configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-05Merge branch '2020-07-05-gpio-regression-fix'Tom Rini
- Merge a fix to the gpio uclass and a test for it.
2020-07-05sandbox, test: add test for GPIO_HOG functionHeiko Schocher
currently gpio hog function is not tested with "ut dm gpio" so add some basic tests for gpio hog functionality. For this enable GPIO_HOG in sandbox_defconfig, add in DTS some gpio hog entries, and add testcase in "ut dm gpio" command. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-05gpio-uclass.c: save the GPIOD flags also in the gpio descriptorHeiko Schocher
save the GPIOD_ flags also in the gpio descriptor. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Fixes: 788ea834124b ("gpio: add function _dm_gpio_set_dir_flags") Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Walter Lozano <walter.lozano@collabora.com>
2020-07-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- sbi: Add newline to error message - fu540: dts: Correct reg size of otp and dmc nodes - Enhance reserved memory fixup about PMP information passed from OpenSBI - sifive: fu540: Add gpio-restart support - qemu-riscv: Update QEMU run command - Assorted fixes related to reserved memory - fu540: enable all cache ways from U-Boot proper - use log functions in fdt_fixup
2020-07-03riscv: use log functions in fdt_fixupHeinrich Schuchardt
Replace printf() and debug() by log_err() and log_debug(). "No reserved memory region found in source FDT\n" is not an error but a debug information. %s/can not/cannot/ - use the more common spelling. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03riscv: Use optimized version of fdtdec_get_addr_size_no_parentAtish Patra
fdtdec_get_addr_size_no_parent is not an optimized version if parent node is already available with the caller. Use fdtdec_get_addr_size_auto_parent to read the "reg" property Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03riscv: Do not return error if reserved node already existsAtish Patra
Not all errors are fatal. If a reserved memory node already exists in the destination device tree, we can continue to boot without failing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03doc: qemu-riscv: Update QEMU run commandBin Meng
Explicitly pass the "-bios" option to QEMU to run U-Boot, instead of the "-kernel" option, as we know that "-bios" behavior will be changed since QEMU 5.1.0. This also updates validated QEMU version to 5.0.0. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03riscv: sifive: fu540: Add gpio-restart supportBin Meng
The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. This adds gpio reboot support. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-03riscv: Do not build reset.c if SYSRESET is onBin Meng
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Expand the DT size before copy reserved memory nodeBin Meng
The FDT blob might not have sufficient space to hold a copy of reserved memory node. Expand it before the copy. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Avoid the reserved memory fixup if src and dst point to the same placeBin Meng
The copy of reserved memory node from source dtb to destination dtb can be avoided if they point to the same place. This is useful when OF_PRIOR_STAGE is used. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-02riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: sbi: Add newline to error messageSean Anderson
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-30Merge tag 'efi-2020-07-rc6-2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc6 (2) Fix an incorrect update of the GD register in efi_get_variable_common(). Fix an incorrect check for an FDT reg property. Fix a device tree used for Python testing.
2020-06-30test/py: test_efi_fit: Update #size-cells to 1Bin Meng
test_efi_fit tests fail on RISC-V currently. This is due to the RISC-V arch_fixup_fdt() checks the #size-cells of the root node in order to correctly fix up the reserved memory node. Per the DT binding, the /reserved-memory node requires both <#address-cells> and <#size-cells> and they should use the same values as the root node. For the root node, it's not very useful if <#size-cells> is zero. Update #size-cells to 1 so tests can pass. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-06-30efi_loader: incorrect check against FDT_ADDR_T_NONEHeinrich Schuchardt
With commit 0d7c2913fdf7 ("cmd: bootefi: Honor the address & size cells properties correctly") addr was replaced by fdt_addr. But not in the check against FDT_ADDR_T_NONE. Fixes: 0d7c2913fdf7 ("cmd: bootefi: Honor the address & size cells properties correctly") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-29Merge tag 'rockchip-fix' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix "Synchronous Abort" when using rk3399 4K HDMI
2020-06-29video: rockchip: fix HDMI 4K resolutionAnatolij Gustschin
3480 is not valid XRES, use 3840 as default. Fixes: 05c65a82c3c1 ("video: rockchip: Support 4K resolution for rk3399, HDMI") Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
2020-06-29efi_loader: fix incorrect use of EFI_EXIT()Heinrich Schuchardt
efi_get_variable_common() does not use EFI_ENTRY(). So we should not use EFI_EXIT() either. Fixes: 767f6eeb01d3 ("efi_loader: variable: support variable authentication") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-28Merge tag 'fixes-for-v2020.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix logo on mx6ul_14x14_evk with DM_VIDEO enabled - fix banner string overwriting the logo on small displays - fix splash warning when building for ARM64 - fix STM32 DSI driver to probe only on supported hardware - fix memory corruption with DSI panel drivers
2020-06-28Merge tag 'u-boot-rockchip-20200628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;
2020-06-28rockchip: correctly set vop0 or vop1Patrick Wildt
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or vop1, but so far we have set it in both conditions, which is not correct. Can someone verify this is the correct way round? vop1 -> set, vop0 -> clear? Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-28video: orisetech_otm8009a: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: raydium_rm68200: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: stm32: stm32_dsi: copy DSI fieldsYannick Fertre
Copy the DSI data link characteristics from panel platform data to mipi DSI device. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: mipi update panel platform dataYannick Fertre
Add new fields "lanes, format & mode_flags" to structure mipi_dsi_panel_plat. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: check hardware version of DSIYannick Fertre
Check the hardware version of DSI. Versions 1.30 & 1.31 are only supported. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
2020-06-28splash: Fix build warning on 64 bits CPUYe Li
Get below warning on ARM64 platform, because the bmp_load_addr is defined to u32. common/splash.c: In function ‘splash_video_logo_load’: common/splash.c:74:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 74 | memcpy((void *)bmp_load_addr, bmp_logo_bitmap, Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-28video: vidconsole: avoid multiple lines overwrite logoYe Li
Fix the bug that multiple lines wraps to overwrite logo bmp display. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-28video: bmp: support 8bits BMP drawing on 24/32 bpp framebufferYe Li
Update video bmp code so that we can display 8 bits logo on 24 or 32 bpp framebuffer. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-27rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27rockchip: rk3188: Fix back to BROM bootAlexander Kochetkov
Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27rk3399: Add BOOTENV_SF commandJagan Teki
Add missing BOOTENV_SF command in rk3399 config. Fix it. Fixes: f263b860acf8 ("rk3399: Enable SF distro bootcmd") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reported-by: Suniel Mahesh <sunil@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-26Merge branch 'for-tom' of https://github.com/lftan/u-bootTom Rini
- arm: socfpga: misc_s10: Fix EMAC register address calculation
2020-06-26arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan
Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-25Merge tag 'efi-2020-07-rc6' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc6 Corrections for variable definitions are provided: * Correct size of secure boot related UEFI variables. * Do not use int for storing an enum. * Replace fdt_addr by fdt_size where needed.
2020-06-25ARM: dts: imx6q-tbs2910: Fix Ethernet regressionFabio Estevam
Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael@walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Soeren Moch <smoch@web.de>
2020-06-24efi_loader: size of secure boot variablesHeinrich Schuchardt
The variables SetupMode, AuditMode, DeployedMode are explicitly defined as UINT8 in the UEFI specification. The type of SecureBoot is UINT8 in EDK2. Use variable name secure_boot instead of sec_boot for the value of the UEFI variable SecureBoot. Avoid abbreviations in function descriptions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24efi_loader: type of efi_secure_modeHeinrich Schuchardt
Variable efi_secure_mode is meant to hold a value of enum efi_secure_mode. So it should not be defined as int but as enum efi_secure_mode. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24cmd: bootefi: Fix fdt_size variable type in efi_carve_out_dt_rsv()Bin Meng
Variable fdt_size should be of type 'fdt_size_t', not 'fdt_addr_t'. Fixes 0d7c2913fdf7: ("cmd: bootefi: Honor the address & size cells properties correctly") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24Merge tag 'mmc-2020-6-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Fix fsl_esdhc_imx tunning mask - Disable CMD CRC for normal tuning for fsl_esdhc_imx - Retry CM1 until emmc ready - Fix sdhci HISPD handling - Cache-aligned extcsd reading
2020-06-24mmc: sdhci: Fix HISPD bit handlingJagan Teki
SDHCI HISPD bits need to be configured based on desired mmc timings mode and some HISPD quirks. So, handle the HISPD bit based on the mmc computed selected mode(timing parameter) rather than fixed mmc card clock frequency. Linux handle the HISPD similar like this in below commit but no SDHCI_QUIRK_BROKEN_HISPD_MODE, commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") This eventually fixed the mmc write issue observed in rk3399 sdhci controller. Bug log for refernece, => gpt write mmc 0 $partitions Writing GPT: mmc write failed ** Can't write to device 0 ** ** Can't write to device 0 ** error! Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Peng Fan <peng.fan@nxp.com> Peng Fan: added back "ctrl &= ~SDHCI_CTRL_HISPD;" per Jaehoon's suggestion Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> # roc-rk3399-pc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-24mmc: retry CMD1 in mmc_send_op_cond() until the eMMC is readyHaibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue CMD1 repeatedly in the idle state until the eMMC is ready even if mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC devices seems to enter the inactive mode after mmc_complete_op_cond() issued CMD0 when the eMMC device is busy. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-06-24mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuningHaibo Chen
In current code, we add 1ms dealy after each tuning command for standard tuning method. Adding this 1ms dealy is because USDHC default check the CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning IC logic do not wait for the tuning data sending out by the card, trigger the buffer read ready interrupt immediately, and step to next cycle. So when next time the new tuning command send out by USDHC, card may still not send out the tuning data of the upper command，then some eMMC cards may stuck, can't response to any command, block the whole tuning procedure. If do not check the CMD CRC for tuning, then do not has this issue. USDHC will wait for the tuning data of each tuning command and check them. If the tuning data pass the check, it also means the CMD line also okay for tuning. So this patch disable the CMD CRC check for tuning, save some time for the whole tuning procedure. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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