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2019-04-17ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan
Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan
Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17arm: socfpga: implement proper peripheral resetSimon Goldschmidt
This commit removes ad-hoc reset handling for peripheral resets from SPL for socfpga gen5. This is done because as U-Boot drivers support reset handling by now. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17spi: cadence_qspi: add reset handlingSimon Goldschmidt
This adds reset handling to the cadence qspi driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17mtd: rawnand: denali: add reset handlingSimon Goldschmidt
This adds reset handling to the devicetree-enabled Denali NAND driver. For backwards compatibility, only a warning is printed when failing to get reset handles. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt
To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17reset: socfpga: add reset handling for old kernelsSimon Goldschmidt
This adds code to take peripherals out of reset based on an environment variable. This is in preparation for removing the code that does this from SPL. However, some drivers even in current Linux cannot handle peripheral reset, so until this works, we need a compatibility workaround. This workaround is implemented in the 'assert' and 'remove' callbacks of this reset driver: the 'assert' callback does not disable peripherals that were already taken out of reset, while the 'remove' callback, which is called on OS_PREPARE, deasserts all peripheral resets if the environment variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5 SPL did up to now. This is in preparation to clean up the SPL and implementing proper reset handling for U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17arm: socfpga: gen5: deassert peripheral reset by defaultSimon Goldschmidt
To keep the current behaviour of taking all peripherals out of reset before booting the OS before removing that code from socfpga gen5 SPL, this enables the new behaviour by default for all gen5 boards by adding the environment variable "socfpga_legacy_reset_compat=1" to the default environment. This can be overridden in board config files or by saving an environment without this variable enabled. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17reset: socfpga: rename membase ptr to modrst_baseSimon Goldschmidt
The only member of this driver's priv struct is a pointer, which is called 'membase'. However, since this driver handles multiple sub- architectures, this is not the base address from dts but the base address of some common registers of those sub-arches. Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17arm: socfpga: gen5: add reset & sdr node to SPL devicetreesSimon Goldschmidt
The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts. In preparation to move the DDR driver to DM, the sdr node is required in SPL, too. This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. It centralizes these settings into a common file since in contrast to boot-type specific nodes, "soc", "rst" and "sdr" are always needed. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17arm: socfpga: gen5: sync devicetrees to LinuxSimon Goldschmidt
This is again a sync to linux-next + pending patches in Dinh's tree at commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset properties")' It adds missing peripheral reset properties to socfpga.dtsi and removes U-Boot specific leftovers from socfpga_cyclone5_socrates.dts. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- drop non-DM code from ti_qspi - support spi-mem for ti_qspi
2019-04-17arm: am57xx: cl-som-am57x: remove board supportUri Mashiach
U-Boot support for the CL-SOM-AM57x module is no longer required. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
2019-04-17Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- Convert DM_MMC and DM_SCSI - A20, R40, H6 Linux dts(i) sync - CLK, RESET support for sunxi, sun8_emac net drivers
2019-04-17Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx/FPGA changes for v2019.07 fpga: - Add support for external data in FIT - Extend testing for external data case - Inform user about a need to run post config on Zynq arm: - Tune zynq command functions - Fix internal variable setting arm64: - Add support for zc39dr decoding - Disable WDT for zcu100 - Small changes in reset_reason() - Some DT changes (spi) - Tune qspi-mini configuration - Remove useless eeprom setting - Fix two sdhci boot case spi: - Fix tap delay programming clk: - Enable i2c in SPL net: - Fix gem phydev handling - Remove phy detection code from gem driver general: - Correct EXT_DTB usage for MULTI_DTB_FIT configuration
2019-04-17Merge tag 'uniphier-v2019.07' of git://git.denx.de/u-boot-uniphierTom Rini
UniPhier SoC updates for v2019.07 - Sync DT with Linux 5.1-rc4 - Enable CONFIG_SUPPORT_EMMC_RPMB for uniphier_v8_defconfig
2019-04-17spi: ti_qspi: Convert to spi-mem opsVignesh Raghavendra
Convert driver to use spi-mem ops in order to support accelerated MMIO flash interface in generic way and for better performance. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17spi: ti_qspi: Drop non DM codeVignesh Raghavendra
Now that all boards using TI QSPI have moved to DM and DT, drop non DM code completely. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [jagan: update MIGRATION.txt, rebase config_whitelist.txt] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17sunxi: update SATA driver to always use DM_SCSIAndre Przywara
It seems like the Allwinner SATA driver is already quite capable of using the driver model, so we can force this on all boards and can remove support for a non-DM_SCSI build. This removes the warning about boards with SATA ports not being DM_SCSI compliant. It also takes the opportunity to move the driver out of the board/sunxi directory to join its siblings in drivers/ata, and to make it a proper Kconfig citizen. The board defconfigs stay untouched. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: select DM_SCSI separately] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17arm: sunxi: Enable DM_MMC and DM_SCSIJagan Teki
- Enable DM_MMC if MMC defined - Enable DM_SCSI if SCSI defined globally through Allwinner platform, the effected SoC families and boards will make use of MMC and SCSI subsystems in driver-model. Tested DM_MMC in one board from A64, H6, H5, H3, R40, A83T, A20, A10 SoCs. Tested-by: Pablo Sebastián Greco <pgreco@centosproject.org> # BPI-M2-Ultra Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17ARM: dts: sun8i-r40-bananapi-m2-berry: Enable AHCIJagan Teki
Enable ahci node for BPI-M2-Berry, this would require since we have DM_SCSI enabled on the respective SoC. Unable to sync the same node from Linux, since the similar change is still in Linux ML. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17ARM: dts: a20-wits-pro-a20-dkt: Enable AHCIJagan Teki
Enable ahci node for a20-wits-pro-a20-dkt, this would require since we have DM_SCSI enabled on the respective SoC. Right now, ahci enabled in -u-boot.dtsi and will remove once same supported by Linux. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17ARM: dts: a20-m5: Enable AHCIJagan Teki
Enable ahci node for sun7i-a20-m5.dts, this would require since we have DM_SCSI enabled on the respective SoC. No need to send patch to Linux for this change, since this dts is U-Boot specific. Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17board: sunxi: Add R40 sata compatibleJagan Teki
Add sata compatible for R40. Cc: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17arm: allwinner: dts: a20: Sync A20 dts(i) files from Linux 5.1-rc2Jagan Teki
Sync sun7i-a20 dts(i) files from Linux 5.1-rc2 Linux commit details about the sun7i-a20* sync: "ARM: dts: sun7i: bananapi: Add GPIO banks regulators" (sha1: 09c6572290f018d73ec2e812e28bada34d41815f) Here are U-Boot specific dts changes. - s/uart0_pins_a/uart0_pb_pins for sun7i-a20-ainol-aw1.dts sun7i-a20-m5.dts sun7i-a20-primo73.dts sun7i-a20-yones-toptech-bd1078.dts sunxi-itead-core-common.dtsi - s/gmac_pins_mii_a/gmac_rgmii_pins for sun7i-a20-m5.dts - drop i2c0, i2c1 pins from sunxi-itead-core-common.dtsi - drop mmc0 pins from sun7i-a20-primo73.dts Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17arm: allwinner: r40: Sync R40 dts(i) files from Linux 5.1-rc2Jagan Teki
Sync sun8i-r40 dts(i) files from Linux 5.1-rc2 Linux commit details about the sun8i-r40* sync: "ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node" (sha1: 1e5f1db4ccd8348a21da55bff82f4263000879ef) Linux commit details about the sun8i-v40* sync: "ARM: dts: sunxi: Fix I2C bus warnings" (sha1: 0729b4af5753b65aa031f58c435da53dbbf56d19) Cc: Pablo Sebastián Greco <pgreco@centosproject.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17ARM: uniphier_v8: enable CONFIG_SUPPORT_EMMC_RPMBMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-04-17ARM: dts: uniphier: sync with Linux 5.1-rc4Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-04-16board: sunxi: gmac: Remove Ethernet clock and resetJagan Teki
Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16net: sun8i_emac: Add CLK and RESET supportJagan Teki
Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-16net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandleJagan Teki
Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi. So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16net: sunxi_emac: Add CLK supportJagan Teki
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-16clk: sunxi: r40: Fix GMAC reset reg offsetJagan Teki
GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c9698f109c1f001f80d282138a5c67cabef) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16arm64: zynqmp: fix preprocessor check for SPL_ZYNQMP_TWO_SDHCILuca Ceresoli
A missing CONFIG_ prefix while checking for this Kconfig variable makes the check always fail. Fix it. While there also switch from the '#if defined' form to the '#ifdef' form as the other checks in this function. Fixes: 35e2b92344b1 ("arm64: zynqmp: Fix logic around CONFIG_ZYNQ_SDHCI") Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Remove eeprom settingMichal Simek
By moving to DM_I2C there is no need to specify any eeprom configuration because it is read from DT. Reported-by: Sreeja Vadakattu <sreeja.vadakattu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16net: gem: Remove phy autodetection codeMichal Simek
There is no reason to detect phy when core is doing it for us. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu
The phydev supported features were reset in phy_set_supported() so, move the setting of driver supported features after this so that it wont lost in phy_set_supported(). Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16Makefile: Prioritize external dtb if definedMichal Simek
Prioritize external dtb if its passed via EXT_DTB than the dtb that was built in the tree. With this patch it appends the specified external dtb to the u-boot image. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-16arm: zynq: Add an info message about post configSiva Durga Prasad Paladugu
Post configuration cant be run at u-boot as u-boot didn't has any info about the design.So,this patch adds an info message that post config was not run and needs to be run manually if needed. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Add idcode for new RFSoC silicon ZU39DRSiva Durga Prasad Paladugu
This patch adds "zu39dr" to the list of zynqmp devices The zu39DR is the new RFSoC silicon with id value of 0x66. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16ARM: zynq: fix environment command syntaxMelin Tomas
Update EXTRA_ENV_SETTINGS and related commands to use 'setenv' instead of short name 'set' in commands. E.g. in case command setexpr is enabled the short form does not work properly as the name becomes ambigous. Fixes error messages like: U-Boot> set Unknown command 'set' - try 'help' Signed-off-by: Tomas Melin <tomas.melin@vaisala.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16ARM: zynq: Add missing i2c get_rate for fixing i2c SPLHannes Schmelzer
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C support because requesting the clock for the I2C ip-block isn't supported during SPL. To fixup this we add support requesting clocks for: - i2c0 - i2c1 Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: xilinx: zynqmp: Remove unneeded configsSiva Durga Prasad Paladugu
Remove unneeded configs from mini qspi configuration so that it saves space for this mini configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Define label for flash nodeSiva Durga Prasad Paladugu
Define a label for flash node so that it can be referenced easily as required. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Add spi-flash compatible string to flash nodeSiva Durga Prasad Paladugu
spi-flash compatible string is needed for reading tx and rx bus widths, hence add this compatible string to flash node. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Add debug message about clearing BSSMichal Simek
Just have better view on system. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16ARM: zynq: Check zynq aes & rsa command parameters countT Karthik Reddy
This patch checks for zynq aes & rsa commands max parameters count. Also checks minimum number of parameters count for aes command. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Use zynqmp_mmio_read/write functionsT Karthik Reddy
Changed the return type of reset_reason() to int from u32, because zynqmp_mmio_read/write() returns signed value on error. Replaced readl and writel functions with zynqmp_mmio_read & zynqmp_mmio_write functions to access RESET_REASON(CRL_APB) registers. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16spi: zynqmp_gqspi: Fix tap delay values at 100MHz and 150MHzSiva Durga Prasad Paladugu
This patch fixes the tap delay values to be set at 100MHz and 150MHz as per TRM by fixing the if condition to use <= instead of <. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16arm64: zynqmp: Disable WDT for zcu100Michal Simek
Do not enable WDT by default on this target because distributions are not enabling watchdog driver to service it. Feature has been enabled by: "arm64: zynqmp: Enable cadence WDT for zcu100" (sha1: 767afebbcda59f3ccb04f6c94de8cab2fb7905b6) And WDT is still enabled in rebranded Avnet Ultra 96 board support. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-12-27 05:03:27 +0000