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2020-07-08lib: rsa: take spl/non-spl into account when building rsa_verify_with_pkey()Heiko Stuebner
Right now in multiple places there are only checks for the full CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants. This breaks when the rsa functions get enabled for SPL, for example to verify u-boot proper from spl. So fix this by using the existing helpers to distinguis between build-steps. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-08lib: rsa: distinguish between tpl and spl for CONFIG_RSA_VERIFYHeiko Stuebner
While the SPL may want to do signature checking this won't be the case for TPL in all cases, as TPL is mostly used when the amount of initial memory is not enough for a full SPL. So on a system where SPL uses DM but TPL does not we currently end up with a TPL compile error of: lib/rsa/rsa-verify.c:48:25: error: dereferencing pointer to incomplete type ‘struct checksum_algo’ To prevent that change the $(SPL_) to $(SPL_TPL_) to distinguish between both. If someone really needs FIT signature checking in TPL as well, a new TPL_RSA_VERIFY config symbol needs to be added. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-08cmd: add a panic commandHeiko Stuebner
Even in boot scripts it may be needed to "panic" when all options are exhausted and the device specification specifies hanging instead of resetting the board. So add a new panic command that just wraps around the core panic call in U-Boot and can take an optional message. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-08debug_uart: Add CR before and after announce stringStefan Roese
Add linefeeds before and after the announce string. This makes the output easier to read, especially if some text follows the announce message without a specific additional CR. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-08tpm: add #ifndef to fix redeclaration build errorsJohannes Holland
tpm_tis_spi.c directly includes tpm_tis.h and tpm-v2.h which both define the same enums (see e.g. TPM_ACCESS_VALID). Add an #ifndef to prevent redeclaration errors. Signed-off-by: Johannes Holland <johannes.holland@infineon.com>
2020-07-08tpm: add TPM2_GetRandom command supportDhananjay Phadke
Add support for TPM2 GetRandom command Signed-off-by: Dhananjay Phadke <dphadke@linux.microsoft.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-08tpm2: tis_spi: add linux compatible fallback stringBruno Thomsen
This solves a compatibility issue with Linux device trees that contain TPMv2.x hardware. So it's easier to import DTS from upstream kernel when migrating board init from C code to DTS. The issue is that fallback binding is different between Linux and u-Boot. Linux: "tcg,tpm_tis-spi" U-Boot: "tis,tpm2-spi" As there are currently no in-tree users of the U-Boot binding, it makes sense to use Linux fallback binding. Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-08Merge tag 'u-boot-amlogic-20200708' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Add proper Odroid-N2 board support code - Add support for Odroid-C4 single board computer
2020-07-08gpio: fix test.py for gpio label lookupHeiko Schocher
commit 2bd261dd1712 ("gpio: search for gpio label if gpio is not found through bank name") disabled DM_GPIO_LOOKUP_LABEL which is needed in sandbox defconfigs, as we have tests for this functionality. Signed-off-by: Heiko Schocher <hs@denx.de>
2020-07-08ARM: dts: meson-sm1-odroid-c4: add ethernet PHY resetNeil Armstrong
The PHY needs a reset in order to be functionnal for U-Boot, add the old PHY reset bindings for dwmac until we support the new bindings in the PHY node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08boards: amlogic: add Odroid C4 supportChristian Hewitt
Odroid C4 is an Amlogic SM1 device, the board config and board documentation are adapted from the Odroid-N2 support from the same vendor. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> [narmstrong: fix odroid-c4.rst typos and structure] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08ARM: dts: sync amlogic G12A/G12B/SM1 DT from Linux 5.8-rc1Christian Hewitt
This imports the changes and the new Odroid-C4 board from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08board: amlogic: Add Odroid-N2 board supportPascal Vizeli
Add a proper Odroid-N2 board support to handle the Ethernet MAC address stored in the in-SoC eFuses. Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-07Merge tag 'u-boot-rockchip-20200708' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts sync from kernel for rk3399 boards; - Add Radxa Rock Pi N8, N10; - Some feature update for Pinebook Pro;
2020-07-07Merge branch '2020-07-07-misc-new-features'Tom Rini
- Improve s700 SoC support - Fix building with clang on ARM. - Juno platform updates - fs/dm cmd improvements - Other assorted improvements / fixes
2020-07-07arm: juno: Enable SATA controllerAndre Przywara
The ARM Juno boards (-r1 and -r2) feature a Silicon Image 3132 PCIe SATA controller soldered on the board, providing two SATA ports. Enable the driver and the sata command in the defconfig, to be able to load images from SATA disks. Tested by loading kernels and Grub/EFI from an SSD and successfully booting a Linux system (with and without using UEFI). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07arm: juno: Enable PCIAndre Przywara
The ARM Juno boards in their -r1 and -r2 variants sport a PCIe controller, which we configure already in board specific code to be ECAM compliant. Hence we can just enable the generic ECAM driver to let U-Boot use PCIe devices. Add the respective options to the Juno defconfig to enable the PCI framework and the generic ECAM driver, and initialise the driver upon loading U-Boot. Make some functions in the Juno PCIe init code static on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07sata_sil: Enable DM_PCI operationAndre Przywara
Even though the sata_sil driver was converted over to the driver model, it still assumed that the PCI controller is using the legacy interface. Allow the "devno" member to be a struct udevice pointer and use DM_PCI_COMPAT to covert the rest of the interface. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07arm: juno: Enable DM_ETHAndre Przywara
The smc911X driver is now DM enabled, so we can switch the Juno board over to use DM_ETH for the on-board Fast Ethernet device. Works out of the box by using the DT. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07net: smc911x: Properly handle EEPROM MAC addressAndre Przywara
When compiled as a DM_ETH driver, the scm911x driver was reading the MAC address from the optional EEPROM storage, but failed to copy this to the platdata struct. Since it was also missing a definition of the read_rom_hwaddr() function, the generic Ethernet code was dismissing this MAC address, falling back to a random address or denying to start at all. Add an implementation of .read_rom_hwaddr, and refactor the function reading the ROM address to be called by all interested parties. This fixes MAC address issues when using the driver in DM_ETH "mode". Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07net: dm: Remove warning about EEPROM provided MAC addressAndre Przywara
Similar to patch 821fec0ceb3e ("net: remove scary warning about EEPROM provided MAC address") this removes the somewhat awkward "warning" on boards using DM_ETH: In many parts of the computing world having a unique MAC address sitting in some on-NIC storage is considered the normal case. If there is a properly provided MAC address (either from ROM or from DT), remove the warning to not scare the user unnecessarily. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07arm: vexpress64: Fix counter frequencyAndre Przywara
The arch timer on 64-bit Arm Ltd. platforms is driven by a 24 MHz crystal oscillator, so the frequency is not 25165824 MHz, as the current code suggests. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07arm: use correct argument size of special registersHeinrich Schuchardt
Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-07arm: remove outdated comment concerning -ffixed-x18Heinrich Schuchardt
Clang 9 supports -ffixed-x18. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07trace: clang compatible handling of gd registerHeinrich Schuchardt
On ARM systems gd is stored in register r9 or x18. When compiling with clang gd is defined as a macro calling function gd_ptr(). So we can not make assignments to gd. Use function set_gd() for setting the register on ARM. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07fs: fat_write: fix short name creation.Heinrich Schuchardt
Truncate file names if the buffer size is exceeded to avoid a buffer overflow. Use Sphinx style function description. Add a TODO comment. Reported-by: CID 303779 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07test_sleep.py: make sleep time and margin configurableHeiko Schocher
make the sleep time and the margin configurable. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-07-07gpio: search for gpio label if gpio is not found through bank nameHeiko Schocher
dm_gpio_lookup_name() searches for a gpio through the bank name. But we have also gpio labels, and it makes sense to search for a gpio also in the labels we have defined, if no gpio is found through the bank name definition. This is useful for example if you have a wp pin on different gpios on different board versions. If dm_gpio_lookup_name() searches also for the gpio labels, you can give the gpio an unique label name and search for this label, and do not need to differ between board revisions. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Don't enable by default] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-07configs: Enable mac and phy configsAmit Singh Tomar
This patch adds MAC and PHY related configs (needed for proper ethernet operations) for Action Semi S700 SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07owl: Kconfig: Enable DM eth for OWL platformAmit Singh Tomar
This patch selects CONFIG_DM_ETH (ethernet driver is base on DM model) for Action semi owl SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07arm: dts: s700: add node for ethernet controllerAmit Singh Tomar
This patch adds node for ethernet controller found on Action Semi OWL S700 SoC. Since, there is no upstream Linux binding exist for S700 ethernet controller, Changes are put in u-boot specific dtsi file. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07net: designware: s700: Add glue code for S700 macAmit Singh Tomar
This patchs adds glue logic to enable designware mac present on Action Semi based S700 SoC, Configures SoC specific bits. Undocumented bit that programs the PHY interface select register comes from vendor source. It has been tested on Cubieboard7-lite based on S700 SoC. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07net: phy: realtek: Introduce PHY_RTL8201F_S700_RMII_TIMINGS to adjust rx/tx ↵Amit Singh Tomar
timings RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have specific Rx/Tx interface timings requirement for proper PHY operations. These timing values are not documented anywhere and picked from vendor code. This commits lets proper packets to be transmitted over the network. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07net: phy: realtek: Add support for RTL8201F PHY module.Amit Singh Tomar
This patch adds support for Realtek PHY RTL8201F 10/100Mbs (with variants: RTL8201FN and RTL8201FL) PHYceiver. It is present on Actions Semi Cubieboard7 board. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07clk: actions: Add Ethernet clocksAmit Singh Tomar
This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07arm: actions: remove "CONFIG_SYS_SDRAM_SIZE" for Actions Owl Semi SoCsAmit Singh Tomar
Now that, we calculate SDRAM size by reading DDR registers, "CONFIG_SYS_SDRAM_SIZE" is no more needed. This commit removes "CONFIG_SYS_SDRAM_SIZE" from common configuration file. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-07-07Actions: OWL: Calculate SDRAM sizeAmit Singh Tomar
Calculate the SDRAM size from DDR capacity register registers instead of using hard-coded value. This is quite useful to get correct size on differnt boards based on Actions OWL family of SoCs (S700 and S900). There is no documentation available that talks about DDR registers, and this is very much taken from vendor source. This commit lets Linux boot on Cubieboard7-lite(based on S700). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-07-07image: Add support for ZSTD decompressionRobert Marko
This patch adds support for ZSTD decompression of FIT images. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-07-07cmd: blkls: Add blkls commandNiel Fourie
Add a command to print a list of available block device drivers, and for each, the list of known block devices. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-07cmd: dm: Fixed/Added DM driver listing subcommandsNiel Fourie
Renamed dm "drivers" subcommand to "compat" (as it listed compatibility strings) and prevent it from segfaulting when drivers have no of_match populated. Added a new "drivers" subcommand to dump a list of all known DM drivers and for each, their uclass id, uclass driver and names of attached devices. Added a new "static" subcommand to dump a list of DM drivers with statically defined platform data. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07cmd: fs: Add command to list supported fs typesNiel Fourie
Added command "fstypes" to list supported/included filesystems. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Limit to sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-07cmd: part: Add subcommand to list supported partition tablesNiel Fourie
Add a subcommand "types" to the part command, which lists the supported partition table types. Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07Merge tag 'u-boot-stm32-20200707' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - arch and board update for stm32mp15: - use OPP information in device tree for 800MHz/650MHz support - ram: inprovments of test command - solve boot on closed chip when access to DBGMCU_IDC is protected - stm32prog command: Add "device anme" during USB enumeration - update configs: activate WATCHDOG and 'env erase' command, increase teed partition, support SD card after NOR boot by default and use env info in env_check - some sboard cleanups: gpio hog in dh board, specific driver for type-c stusb1600 controller code in a driver move part of code in spl.c and in common directory - fix STM32 compatible for dwc_eth_qos driver - support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx drivers - vrefbuf: fix a possible overshoot when re-enabling
2020-07-07Merge tag 'u-boot-atmel-2020.10-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.10 cycle
2020-07-07arm64: issue ISB after updating system registersVolodymyr Babchuk
ARM Architecture reference manual clearly states that PE pipeline should be flushed after changes to some system registers. Refer to paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI 0487B.a). Failing to issue instruction synchronization barrier can lead to spurious errors, like synchronous exception when accessing FPU registers. This is very prominent on CPUs with long instruction pipeline, like ARM Cortex A72. This change fixes the following U-Boot panic: "Synchronous Abort" handler, esr 0x1fe00000 elr: 00000000800948cc lr : 0000000080091e04 x0 : 00000000801ffdc8 x1 : 00000000000000c8 x2 : 00000000800979d4 x3 : 00000000801ffc60 x4 : 00000000801ffd40 x5 : ffffff80ffffffd8 x6 : 00000000801ffd70 x7 : 00000000801ffd70 x8 : 000000000000000a x9 : 0000000000000000 x10: 0000000000000044 x11: 0000000000000000 x12: 0000000000000000 x13: 0000000000000000 x14: 0000000000000000 x15: 0000000000000000 x16: 000000008008b2e0 x17: 0000000000000000 x18: 00000000801ffec0 x19: 00000000800957b0 x20: 00000000000000c8 x21: 00000000801ffdc8 x22: 000000008009909e x23: 0000000000000000 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000801ffc50 Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0) While executing instruction str q0, [sp, #112] in vsnprintf() prologue. This panic was observed only on Cortex A72 so far. This patch places ISBs on other strategic places as well. Also, this probably is the right fix for the issue workarounded in the commit 45f41c134baf ("ARM: uniphier: add weird workaround code for LD20") Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Suggested-by: Julien Grall <julien.grall.oss@gmail.com> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> CC: Tom Rini <trini@konsulko.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Julien Grall <julien@xen.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07ram: stm32mp1: add size and addr parameter to test allPatrick Delaunay
Add size and addr parameter to test "All" to override the default value (4kB and STM32_DDR_BASE) used in tests with these optional parameters: [size] or [addr]. When other optional parameters are present before [addr], they are replaced by default value: - [loop] = "1" - [pattern] = "-" (new: force default pattern) Example to use: DDR>test 0 1 0x20000 DDR>test 0 1 0x1000000 0xD0000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: use the DDR size by default in the test addressBusPatrick Delaunay
The test 4 = "AddressBus [size] [addr]" without parameter detects alias for any address bit only when: - size = real size of DDR - addr = start of DDR = 0xC0000000 These value must be the default value when parameters are absent. This patch sets bufsize to STM32_DDR_SIZE and get_bufsize() selects the correct value for bufsize when this parameter is absent = full size of the DDDR On EV1 board : DDR> test 4 running at 0xC0000000 length 0x40000000 On DK2 board DDR> test 4 running at 0xC0000000 length 0x20000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: add parameter addr in test FrequencySelectivePatternPatrick Delaunay
Add a parameter addr in test FrequencySelectivePattern to select the base address used to execute the tests. Default value (when the parameter is absent) is STM32_DDR_BASE, selected in get_addr() function. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: protect minimum value in get_bufsizePatrick Delaunay
Add protection on minimum value for result of get_bufsize and check the alignment of buffer size: only multiple min_size is allowed; only 4 bytes alignment was checked previously (value & 0x3). For example the "Random" test raises an issue when size is not 8 bytes aligned because address for buffer = address + size / 2 is not word aligned. This patch avoid test error for unsupported size value. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07stm32mp1: use the command env info in env_checkPatrick Delaunay
Activate CMD_NVEDIT_INFO and use the new command "env info -d -p -q" to automatically save the environment on first boot. This patch allows to remove the env_default variable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>