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The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This function can probably be used on all x86 boards, so move it into the
common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Enable GPIO support and provide the required GPIO setup information to
the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.
In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Set up the flex ratio (controls speed versus heat output) and a few other
very early things.
Signed-off-by: Simon Glass <sjg@chromium.org>
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It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These are available on other architectures. Make them available on x86 also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add support for using PCI before SDRAM is available, using early malloc()
and global_data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
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On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
Create a u-boot.rom output file for this purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Allow an empty ROM to be created, without needing to provide a descriptor.
The descriptor is not needed on some x86 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.
For this CPU we know the frequency, so add another special case for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
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This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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These are no-longer needed so drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Newer Intel chips require a Management Engine which requires a particular
format for the SPI flash that contains the boot loader. Add a tool that
supports creating and modifying these ROM images.
This tool is from Chrome OS but has been cleaned up to use U-Boot style
and to add comments. A few features have been added also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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For board IDs a common approach is to set aside several GPIOs for use in
determining the board ID. This can provide information about board features
and the revision.
Add a function that turns a list of GPIOs into an integer by assigning
each GPIO to a single bit.
Signed-off-by: Simon Glass <sjg@chromium.org>
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In general we can't store things in the data section until we have inited
SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move
the pointer to global_data so that it will work on all platforms.
Without this fix the serial port will not work prior to relocation with
driver model on some platforms.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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For some CPUs, having malloc() available very early is useful. There is no
reason to delay this since early malloc is allocated before board_init_f()
is called.
Move early malloc() init nearer to the start of the init sequence.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This warning appears even though it seems that the compiler could work it
out. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Return the saved TSC frequency in get_tbclk_mhz().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Some functions are missing prototypes. Fix those that are specific to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This was missed when the real mode support was dropped. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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When an MPC5200 based board is used with SPL support, the main
U-Boot needs to clear the GD (global data) struct again.
Otherwise the generic board init code in board_init_f (when
CONFIG_SYS_GENERIC_BOARD is defined) will not initialize all
GD variables correctly. Resulting in a hangup on the a4m2k
board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
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