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2019-01-25mmc: hi6220_dw_mmc: add compatible for Poplar supportShawn Guo
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC Hi3798CV200 to probe this mmc driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25poplar: sync up device tree with kernel 4.20Shawn Guo
It adds missing pinctrl headers, updates clock header and sync up Poplar device tree with kernel 4.20 release. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-01-25dts: 820c: Add pinctrl node and uart muxRamon Fried
* Add pinctrl node for TLMM and add mux request for uart node. * Rename uart to the actual board uart port. * Fix indentendation of sdhc2 node. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: pinctrl: clarify gpio disable bitRamon Fried
The TLMM_GPIO_ENABLE bit is actually use to disable the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25configs: dragonboard820c: Enable pinctrl/mux configRamon Fried
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: add pinctrl driver for db820cRamon Fried
Add pinctrl driver for Dragonboard820c, currently with only one mux func to initialize pins for serial console. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25arm: mach-snapdragon: db820c: Actually init PLL for serialRamon Fried
The PLL for the UART was not set, and relied on previous initializtion made by LK. add the appropriate initialization. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2019-01-25cmd: ximg: Invert check for fit image compressionStefan Theil
The imgextract command runs a number of checks of the specified fit. Where it checks for a load address for compressed images the logic in the expression is inverted as fit_image_check_comp returns 1 on success and not 0.
2019-01-25arm: stm32mp1: deploy spl in root folderSean Nyekjær
Deploy u-boot-spl.stm32 binary in u-boot root folder like the rest of the boards. This makes it more streamlined when building in Yocto, Buildroot etc.. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
2019-01-25configs: Migrate CONFIG_DFU_MMC againTom Rini
A few platforms recently added in CONFIG_DFU_MMC under include/configs rather than via the defconfig, update them. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-25Merge tag 'arc-fixes-for-2019.04-rc1' of git://git.denx.de/u-boot-arcTom Rini
A couple of trivial fixes and improvements for ARC Most notable are: * Move of ENV_SIZE/ENV_OFFSET to Kconfig * Fix with private structure allocation for arc_uart * Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
2019-01-25ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGNAlexey Brodkin
Even though we don't use CONFIG_SYS_CACHELINE_SIZE in ARC-specific code it is used a lot in different drivers for alignment purposes. So we define it and make much more drivers at least compilable for ARC. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25ARC: Fix iteration in arc_xx_version()Alexey Brodkin
"i" gets incremented before we're entering loop body and effectively we iterate from 1 to 8 instead of 0 to 7. This way we: a) Skip the first line of struct hs_versions b) Go over it and access memory beyond the structure Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25serial_arc: Allocate buffer for private dataAlexey Brodkin
Apparently we never allocated buffer for arc_serial_platdata which for some reason never caused problems when executed in nSIM. But in Qemu this causes expected problems. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25ARC: Move ENV_SIZE and ENV_OFFSET to KconfigAlexey Brodkin
Join the party of some ARM boards and drop more items from include/configs/xxx.h. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-25serial: Get rid of CONFIG_DW_SERIALAlexey Brodkin
CONFIG_DW_SERIAL is no longer used anywhere so let's forget about it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@konsulko.com> Cc: Adam Ford <aford173@gmail.com> Cc: Mario Six <mario.six@gdsys.cc> Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: "Jorg Krause" <joerg.krause@embedded.rocks> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2019-01-24Merge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xxTom Rini
mpc85xx config.mk: Add support for -msingle-pic-base
2019-01-24net: phy: aquantia: Print information on configValentin-catalin Neacsu
Print information about Aquantia system interface and firmware loaded on the phy. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: aquantia: Enable autoneg when on USXGMIIValentin-catalin Neacsu
If System Interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: remove CONFIG_MCAST_TFTPChris Packham
No mainline board enables CONFIG_MCAST_TFTP and there have been compilation issues with the code for some time. Additionally, it has a potential buffer underrun issue (reported as a side note in CVE-2018-18439). Remove the multicast TFTP code but keep the driver API for the future addition of IPv6. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: move ether_crc to tsec driverChris Packham
ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: realtek: Add functions to read PHY's extended registersCarlo Caione
According to the datasheet to access the extended registers we have to: 1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers) Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: macb: fix mapping of registersRamon Fried
Some architectures (MIPS) needs mapping to access IOMEM. Fix that. Fixes: f1dcc19b213d ("net: macb: Convert to driver model") Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvneta: Add GPIO configuration supportAditya Prayoga
This patch add GPIO configuration support in mvneta driver. Driver will handle PHY reset. GPIO pins should be set in device tree. Ported from mvpp2x [https://patchwork.ozlabs.org/patch/799654/] Initial discussion to port the changes into mvneta [https://patchwork.ozlabs.org/patch/1005765/] Signed-off-by: Aditya Prayoga <aditya@kobol.io> Tested-by: Dennis Gilmore <dgilmore@redhat.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvgbe: fallback phy-mode to GMIIChris Packham
Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: micrel: fix KSZ9031 clock skew for values greater 0psAndreas Pretzsch
For KSZ9021, all skew register fields are 4-bit wide. For KSZ9031, the clock skew register fields are 5-bit wide. The common code in ksz90x1_of_config_group calculating the combined register value checks if the requested value is above the maximum and uses this maximum if so. The calculation of this maximum uses the register width, but the check itself does not. It uses a hardcoded value of 0xf, which is too low in case of the 5-bit clock (0x1f). This detail was probably lost during driver unification. Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps), this silently results in 1860 (== +960ps) instead of the requested one. Fix the check by using the bit width instead of hardcoded value(s). Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: fix env flags for eth10addr and aboveSimon Goldschmidt
With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10 interfaces (0..9) as the number can only have one digit. On boards with more than 10 interfaces, this leads to the protection and format checks being absent for eth10addr and above. Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow more than one digit. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: remove duplicate definition of ETHADDR_WILDCARDSimon Goldschmidt
ETHADDR_WILDCARD is defined as the same value in both env_flags.h and env_callback.h As env_callback.h includes env_flags.h, remove the duplicate definition from env_callback.h Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: explicitly assign errno to return code in case of network failureThomas RIENOESSL
When dealing with two ethernet ports and having "netretry" set to "once", it could occur that the connection (e.g. an ARP request) failed, hence the status of the netloop was "NETLOOP_FAIL". Due to the setting of "netretry", the network logic would then switch to the other network interface, assigning "ret" with the return value of "net_start_again()". If this call succeeded we would return 0 (i.e. success) to the caller when in reality the network action failed. Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: mdio device per portBaruch Siach
Current code forces all ports on a given Ethernet device to use the same mdio device. In practice different ports might be wired to separate mdio devices. Move the mdio device from the container struct mvpp2 to the per port struct mvpp2_port. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: fix lookup of mdio registers base addressBaruch Siach
Current mdio base lookup code relies on a 'reg' property at the upper CP node. There is no 'reg' property there in current DT files of Armada CP110. Use ofnode_get_addr() instead since it provides proper DT address translation. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: clear padding bytesSimon Goldschmidt
Short frames are padded to the minimum allowed size of 60 bytes. However, the designware driver sends old data in these padding bytes. It is common practice to zero out these padding bytes ro prevent leaking memory contents to other hosts. Fix the padding code to zero out the padded bytes at the end. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: fix tx packet lengthSimon Goldschmidt
The designware driver has a bug in setting the tx length into the dma descriptor: it always or's the length into the descriptor without zeroing out the length mask before. This results in occasional packets being transmitted with a length greater than they should be (trailer). Due to the nature of Ethernet allowing such a trailer, most packets seem to be parsed fine by remote hosts, which is probably why this hasn't been noticed. Fix this by correctly clearing the size mask before setting the new length. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24net: phy: Add clause 45 identifier to phy_devicePankaj Bansal
The phy devices can be accessed via clause 22 or via clause 45. This information can be deduced when we read phy id. if the phy id is read without giving any MDIO Manageable Device Address (MMD), then it conforms to clause 22. otherwise it conforms to clause 45. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2019.04 tools: - Fix zynqmpimage generation zynq: - Some configs/Kconfig/DT updates - Enable REMAKE_ELF and OF_SEPARATE - Topic boards update - i2c cleanups and conversion to DM_I2C zynqmp: - Some configs/Kconfig/DT updates - Board config cleanup - Move arch folder to mach-zynqmp versal: - Enable DM_I2C, CMD_DM zynq-gem: - Fix driver cache handling i2c: - Live tree simple update phy: - Fixed phy cleanup travis: - Wire Versal SoC
2019-01-24ARM: zynq: Convert Topic Miami to DM_I2CMichal Simek
Both boards have only controllers enabled that's why move to DM_I2C is easy. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Disable i2c for Zybo/Zybo Z7Michal Simek
There is no i2c connected in base DT that's why disable I2C commands. Also remove zynq_zybo which is not needed now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24zynq: Kconfig: extend the bootstrap malloc() poolAnton Gerasimov
Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Measuring only the memory consumed in device_bind_common, I've got the following results (in decimal): root_driver: 108 mod_exp_sw: 108 amba: 120 serial@e0000000 aka uart0: 112 serial@e0001000 aka uart1: 88 spi@e000d000 aka qspi: 120 sdhci@e0100000 aka mmc0: 455 sdhci@e0100000.blk: 208 slcr@f8000000: 96 clkc@100: 72 (total) 1487 = 0x5cf of 0x600 Signed-off-by: Anton Gerasimov <tossel@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24board: topic-miamiplus: Run IO PLL at 1000 MHzMike Looijmans
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so change it to run at 1000 and adjust the divisors accordingly. Also set the GEM0 clock source to MIO instead of EMIO. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24topic-miamiplus: Run CPU at 800MHz for speedgrade-2Mike Looijmans
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz. Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24i2c: cdns: Convert to livetree functionMichal Simek
Update cadence i2c driver to support livetree Similar changes were done by: "net: zynq_gem: convert to use livetree" (sha1: 26026e695afa794ac018a09e79a48120d322b60d) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Enable dm commandMichal Simek
It is useful to have this command enable to see which devices are bind/probed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Enable i2c cadence controller and i2c commandMichal Simek
Enable communication over i2c. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek
Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Convert all boards to OF_SEPARATEMichal Simek
Build warning was added by: "fdt: Add warning about CONFIG_OF_EMBED" (sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41) Zynq mini configurations are not moved yet and it is questionable if make sense to move them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm: zynq: Enable CONFIG_REMAKE_ELFSiva Durga Prasad Paladugu
This patch enables CONFIG_REMAKE_ELF for Zynq platform so that it generates u-boot.elf from binary which works for all Zynq boards with OF_SEPARATE option enabled. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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