Age | Commit message (Collapse) | Author |
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Add dm eth config options for all involved ColdFire-based boards.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
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Add ethernet controller overrides for all involved boards.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
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Add basic ethernet controller devicetree nodes for all ColdFire
families.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
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- A small PR with MC8309 fixes from Rasmus.
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dm: Increased separation of ofdata_to_platdata() and probe methods
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- DFU updates
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https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
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https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.04
- add pinmux nodes for I2C ch5, ch6
- enable SPI driver and command
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
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Add i.MX8MP SoC and EVK board
Update README for i.MX8MN EVK and fix mmc env
Add pca9450 driver
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Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
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- DT overlay support in FIT images in SPL
- remoteproc update
- Assorted SATA fixes
- Other assorted fixes
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Compile drivers/spi/uniphier_spi.c and cmd/spi.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The next generation SoC can connect on-board slave devices via
I2C ch5 and ch6.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
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In the initialization of sata driver, we want to initialize all port
probes, Therefore, any detection failure between of them should continue
initialization by skipping the current port instead of exit.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
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As previous CONFIG_SYS_UBOOT_START is now set by default to
CONFIG_SYS_TEXT_BASE when not defined, CONFIG_SYS_UBOOT_START
can be removed from include/configs board files.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
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This patches restores boot on boards which rely on
CONFIG_SYS_UBOOT_START equal to CONFIG_SYS_TEXT_BASE when using SPL
Fixes: d3e97b53c1f2 ("spl: fix entry_point equal to load_addr")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Per Enea OSE documentation, it supports some classes of ARM, PowerPC and
X86. Limit the option to those platforms.
Signed-off-by: Tom Rini <trini@konsulko.com>
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enable CONFIG_CMD_ERASEENV to make it easy to erase env.
Use savedefconfig to generate new defconfig.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add board_mmc_get_env_dev, otherwise,
Loading Environment from MMC...
MMC Device 0 not found
*** Warning - No MMC card found, using default environment
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add a README for users to build a workable image.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add basic i.MX8MP EVK board support
U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
power_pca9450b_init
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Failed to find clock node. Check device tree
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz
Reset cause: POR
Model: NXP i.MX8MPlus EVK board
DRAM: 6 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
u-boot=> mmc list
FSL_SDHC: 1 (SD)
FSL_SDHC: 2
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add imximage-8mp-lpddr4.cfg for imximage usage, almost same
as i.MX8MN ddr4 cfg, but with different ddr firmware
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8MP clk driver for i.MX8MP CLK driver model usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add imx_clk_mux2_flags which will be used by i.MX8MP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The drivers/clk/imx/*.c are used for CLK dm case, the
clock_imx8mm.c is used for non CLK dm case, let's split
it. Sometimes it is hard to enable CLK dm in SPL stage,
considering code size, malloc size requirement, the splittion
will make it easy to use non CLK dm in SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP ROM support ROMAPI as i.MX8MN, so make
SPL_IMX_ROMAPI_LOADADDR visible to i.MX8MP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add pin header file for i.MX8MP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The i.MX8M Plus Media Applications Processor is part of the growing
mScale family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in Samsung 14LPP to achieve both
high performance and low power consumption and relies on a powerful
fully coherent core complex based on a quad core ARM Cortex-A53 cluster
and Cortex-M7 low-power coprocessor, audio digital signal processor,
machine learning and graphics accelerators.
Add the basic dtsi support for i.MX8MP.
Patch from Anson Huang for Kernel
https://patchwork.kernel.org/patch/11310915/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8MP compatible to let the pinctrl driver could support
i.MX8MP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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4000MTS DDR needs 1GHz fracpll, so add the entry
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8MP pinfunc header for dts usage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8MP clock header
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP follows i.MX8MN, so just let it use spl_board_boot_device
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add Kconfig entry for i.MX8MP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest
bit, so enlarge bit mask to 0x1FF to make it could detect
cpu type correctly
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Support get i.MX8MP cpu id and cpu type
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK +
dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK
as root clk and cause sd card could not be detected in U-Boot proper,
as below:
"Loading Environment from MMC... unable to select a mode"
Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Fabio Estevam <festevam@gmail.com>
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After the conversion to DM_PMIC the following output is seen:
PMIC: PMIC: PFUZE100 ID=0x10
Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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Commit ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
PMIC: pmic_get() ret -19
...
and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:
WARNING: Could not determine dtb to use
and the kernel does not boot at all.
Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.
Fixes: ec837c82d709 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:
When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().
The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:
- The power-on-reset value of SCCR[PCICM] is 0, so
mpc83xx_clk_enable() would probably need to be tought to enable the
clock.
- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
depending on the CFG_CLKIN_DIV configuration input, but that can't
be read from software, so to properly fill out
->speed[MPC83XX_CLK_PCI] I think one would need guidance from
Kconfig or dtb.
Partially fixes: 07d538d281 clk: Add MPC83xx clock driver
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
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The MPC8309 has two gpio controllers (which is already correctly
reflected in its struct immap definition).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
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Allow drivers/spi/mpc8xxx_spi.c to be built for an mpc8309 target.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
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