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2017-07-27sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size ↵Andy Yan
before relocation SPL and normal u-boot stage use different malloc pool size configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit different boot stage. Signed-off-by: Andy Yan <andyshrk@gmail.com> Changes in v3: - use CONFIG_VAL(), which suggested by Simon Changes in v2: None arch/sandbox/cpu/start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full ↵Andy Yan
U-Boot Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LENAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Add "usb start" to auto-start USB deviceLeo Wen
Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't need to input "usb start" in command line of u-boot console,it can auto-start the USB device,after that usb keyboard can work. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Set the environment variable 'usbkbd' to the stdinLeo Wen
Add the 'usbkbd' environment variable to the 'stdin', the contents of the keyboard input can be auto-displayed on the serial terminal,so you don't need to manually set the environment variable 'stdin'. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Add some macros to enable the usb keyboardLeo Wen
Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the firefly-rk3288_defconfig,can support usb keyboard device when these four macros are enabled. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via ↵Philipp Tomsich
Kconfig SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously enabled through rk3399_common.h. This change implies these options through Kconfig. These need to always be active for the RK3399, as follows: - SPL_SERIAL_SUPPORT is needed to pass the SPL build - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Add support for drive-strength in PINCTRLRomain Perier
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically. This commit adds support for handling drive-strength of 12ma, when it's defined in the DT. Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: use UUID for root partitionsKever Yang
We use to use /dev/mmcbl0p7 as root partition, and pass it to kernel by cmdline, but the mmc number in kernel in not fixed, we need to change the bootargs to adapt it from time to time. We can use the UUID to fix it, the ID is from: https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/ ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3 ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: rk3399-puma: put EFI partition entries at 2MBPhilipp Tomsich
When creating a EFI/GUID partition map for the RK3399-Q7 through U-Boot, the partition entries should be places at a 1MB offset from the start of the device to give us space for the environment (at 16KB on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the image payload (at 256KB on SD/MMC devices). This change sets this up through the u-boot,efi-partition-entries-offset /config property in the RK3399-Q7 DTSI. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) ↵Philipp Tomsich
before SPL As our SPL stage can grow quite large (80KB+ are not unusual) on the RK3399-Q7, the default setting for the environment location (in include/configs/rockchip-common.h) can overlap our SPL. This change finally makes use of the 'u-boot,mmc-env-offset' DTS property to override the environment location and put it at 16KB into the device, which is right before the SPL (located at 32KB). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: clk: rk3399: remove unused fields from priv-structuresPhilipp Tomsich
This removes the unused 'rate' field from both rk3399_pmuclk_priv and rk3399_clk_priv. I didn't bother to check where this came from (i.e. what the historical context of these was), but only verified that these are indeed unused across all code-paths. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27rockchip: clk: rk3368: remove unused fields from rk3368_clk_privPhilipp Tomsich
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This removes them as there's no need for either (i.e. has_bwadj is always true for the RK3368, according to its TRM). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for ↵Philipp Tomsich
auto-alloc The clk driver for the RK3368 picked the wrong data structure's size for its auto-alloc size: the size was calculated on the structure representing the CRU hardware block instead of the priv structure. As the CRU's register file is much larger than the driver's priv, this did not cause any pain (except wasting memory). Fix this by using the correct data structure's size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27rockchip: spl: make boot0 hook TPL safePhilipp Tomsich
When building for a TPL/SPL setup (e.g. on the RK3368), we need the TPL stage to have the extra space for for the 'Rockchip SPL name' (i.e. 'RK33' word). Yet, the SPL will start execution at its first word (i.e. the first word in the SPL binary needs to be a valid instruction). To make things a bit more involved, CONFIG_SPL_BUILD is defined both for the SPL and the TPL stage. To avoid having to explicitly test for the first stage (TPL, if and only if TPL and SPL are built, SPL otherwise), this commit modifies the sequence to repeat the 'b reset' (instead of reserving 4 bytes of undefined space) at the start of the boot0 hook: if overwritten (and execution starts at the second word), the first instruction is still a 'b reset'... if not overwritten, we start on a 'b reset' as well. This solution wouldn't even require the check whether we are in the SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for documentation purposes. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-27rockchip: pwm: add mask for config settingKever Yang
Use mask to clear old setting before direct set the new config, or else there it will mess up the config when it's not the same with default value. Fixes: 3851059 rockchip: Setup default PWM flags Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27power: pwm_regulator: remove redundant codeKever Yang
The regulator_enable() should be called from upper layer like regulators_enable_boot_on(), remove it from pwm regulator driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up typo in commit message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27power: pwm_regulator: fix the pwm_set_config parameter orderKever Yang
The rkpwm reg order has fixed by below patch: e3ef41d rockchip: pwm: fix the register layout for the PWM controller We need to correct the parameter order for pwm_set_config() to make the pwm regulator works correctly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: correct vdd_log setting for firefly-rk3399Kever Yang
Add regulator-init-microvolt for driver to init the regulator, and the min output value is not 800000mV for the PWM2 io domain has changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to correct it with the value measured when PWM2 output HIGH. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: firefly using ddr3 1600Kever Yang
According to my test, some of firefly-rk3399 hang after dram init when using ddr3-1333 config, while using ddr3-1600 config works for all the board I have test. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: phycore: Add ID page of M24C32-D EEPROMWadim Egorov
The Identification Page (32 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. phyCORE-RK3288 SoMs are using this page to describe the module variant. This page also contains a MAC. Our boards can be equipped with a different amount of EEPROMs. To make this more transparent let's add an alias for the eeprom which stores the module variant. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMACRomain Perier
This reverts TXCLK toggling that was accidently dropped while reworking commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac ethernet interface"). So the TX clock is enabled and we can use GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled (!PINTRL_FULL). Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Remove phy reset GPIO pull upRomain Perier
We should not handle this pin explicitly from pinctrl. GMAC driver takes care of it by using a "reset-gpio" in the DT. This commit removes pull up for GPIO4B0. Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: efuse: dm: change to use dev_read_addrPhilipp Tomsich
This changes the rockchip-efuse driver to use dev_read_addr instead of devfdt_get_addr. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: timer: make register sizes explicitPhilipp Tomsich
We are about to reuse the rockchip timer (header file) for 64bit ARMv8 chips, so it seems a good time to make the register sizes explicit by changing from 'unsigned int' to 'u32'. Reorders the header-includes in rk_timer.c to ensure that 'u32' is definded before it is used by 'asm/arch/timer.h'. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: rk3229: add dwc2 node for fastbootMeng Dongyang
Add dwc2 node for fastboot to init dwc2 controller. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-26Merge git://git.denx.de/u-boot-uniphierTom Rini
2017-07-26Merge git://git.denx.de/u-boot-mipsTom Rini
2017-07-26MAINTAINERS: Update maintainer for x86Bin Meng
This adds myself as one of the x86 maintainers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-26FIT: List kernel_noload in the list of typesTom Rini
In the source_file_format.txt file we talk about how to construct a valid FIT image. While it already says to look at the source for the full list, add kernel_noload to the explicit list of types. This is arguably the most important type to use as most often we are including a kernel that will run from wherever it is loaded into memory and execute. This for example, allows you to create a single FIT image for Linux that can be used on both OMAP and i.MX devices as the kernel will not need to be moved in memory. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-07-26ram: stm32: add stm32h7 supportPatrice Chotard
STM32F7 and H7 shared the same SDRAM control block. On STM32H7 few control bits has been added. The current driver need some minor adaptation as FMC block enable/disable for H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26ARM: DTS: stm32: remove useless mr-nbanks propertyPatrice Chotard
FMC driver is now able to discover the bank number by parsing bank subnodes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26ram: stm32: add second SDRAM bank managementPatrice Chotard
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26ram: stm32: replace fdtdec_get by ofnode callsPatrice Chotard
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26ram: stm32: get base address from DTPatrice Chotard
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC For STM32F7, FMC block base address is 0xA0000000, but SDRAM registers are located at offset 0x140 inside FMC block. Update the stm32_fmc_regs fields with all FMC registers to map SDRAM registers at the right address. These additionals registers will be used later. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-26ram: stm32: migrate fmc defines in driver filePatrice Chotard
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h to drivers/ram/stm32_sdram.c This will avoid to add an additionnal arch-stm32xx/fmc.h file when a new stm32 family soc will be introduced. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-26clk: stm32f7: remove clock_get()Patrice Chotard
All drivers which was using clock_get() are now using clk_get_rate() from clock framework, now it's safe to remove clock_get(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26spi: stm32_qspi: add clk_get_rate() supportPatrice Chotard
Replace proprietary clock_get() by clk_get_rate() The stm32_qspi is now "generic" and can be used by other STM32 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26serial: stm32x7: add clk_get_rate() supportPatrice Chotard
Replace proprietary clock_get() by clk_get_rate() The stm32x7 serial driver is now "generic" and can be used by other STM32 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26serial: stm32x7: migrate serial struct to driverPatrice Chotard
This allow to remove include/dm/platform_data/serial_stm32x7.h which was included in the past by stm32x7 driver and by stm32f746-disco.c board file. Since patch 42bf5e7c27 "serial: stm32f7: add device tree support" this file is no more needed in board file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: cleanup clocks unused definitionsPatrice Chotard
clean the code by removing unused enums, structs and defines related to clocks Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: add clock .get_rate() callbackPatrice Chotard
Add clock framework .get_rate callback. This step will allow to convert all drivers which was using proprietary clock_get() to use clock framework .get_rate(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: get RCC base address from DTPatrice Chotard
Retrieve RCC base address from DT, this will prepare the ground for future STM32 SoCs support. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26clk: stm32f7: add static for configure_clocks()Patrice Chotard
Also remove its declaration from stm32.h which is no more needed. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26ARM: DTS: stm32: align DT clock declaration with kernelPatrice Chotard
Use the same clocks macro than the one used by kernel DT. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26arm: mach-keystone: Fixes issue with return values in inline assemblySrinivas, Madan
The inline assembly functions in mon.c assume that the caller will check for the return value in r0 according to regular ARM calling conventions. However, this assumption breaks down if the compiler inlines the functions. The caller is then under no obligation to use r0 for the result. To fix this disconnect, we must explicitly move the return value from the smc/bl call to the variable that the function returns. Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26configs: ti: armv7: Fixes bug in fit_loadaddr for ramfs bootMadan Srinivas
The load address of ramdisk, rdaddr is 0x88080000 and fit_loadaddr is defined as 0x88000000. This leaves only 512Kbytes for the fit image. When the FIT images are larger than this, it will overwite the ramdisk and cause the boot to fail. For eg, The K2 HS fit images are a few MB and end up overwriting the ramdsk. This patch moves the fit_loadaddr to 0x87000000, leaving a 16MB window for the fit image. This memory can be reclaimed once the kernel starts running. Signed-off-by: Madan Srinivas <madans@ti.com>
2017-07-26arm: mach-keystone: Updates mon_install for K2G HSMadan Srinivas
On early K2 devices (eg. K2HK) the secure ROM code does not support loading secure code to firewall protected memory, before decrypting, authenticating and executing it. To load the boot monitor on these devices, it is necessary to first authenticate and run a copy loop from non-secure memory that copies the boot monitor behind firewall protected memory, before decrypting and executing it. On K2G, the secure ROM does not allow secure code executing from unprotected memory. Further, ROM first copies the signed and encrypted image into firewall protected memory, then decrypts, authenticates and executes it. As a result of this, we cannot use the copy loop for K2G. The mon_install has to be modified to pass the address the signed and encrypted secure boot monitor image to the authentication API. For backward compatibility with other K2 devices and K2G GP, the mon_install API still supports a single argument. In this case the second argument is set to 0 by u-boot and is ignored by ROM Signed-off-by: Thanh Tran <thanh-tran@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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