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2013-06-13spi: tegra114_spi: Convert to use spi_alloc_slave()Axel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-13spi: armada100_spi: Remove unnecessary NULL test for dout and dinAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-06-12Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2013-06-12arm: pxa: config option for PXA270 turbo modeSergey Yanovich
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process. Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
2013-06-12arm: pxa: Add support for ICP DAS LP-8x4xSergey Yanovich
LP-8x4x is a programmable automation controller by ICP DAS. It is shipped with outdated U-Boot v1.3.0 This patch adds enough supports to boot the board: - 128M of 128M SDRAM - 32M of 48M NOR Flash memory - 1 of 4 Serial consoles (PXA FFUART) - 2 of 2 Ethernet controllers (DM9000) Signed-off-by: Sergey Yanovich <ynvich@gmail.com> Series-to: u-boot Series-cc: marex
2013-06-12usb, composite: after unregister gadget driver set composite to NULLHeiko Schocher
Without this, second usb_composite_register() call fails always with -EINVAL. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Vasut <marex@denx.de>
2013-06-12usb: ehci: add missing cache managmentStephen Warren
Commit 8f62ca6 "usb: ehci: Support interrupt transfers via periodic list" didn't include any cache management in the new interrupt transfer path. It also added an extra write to or_asynclistaddr in usb_lowlevel_init(), without having flushed out the data there. Add the missing cache management calls, so that the code works again. This allows the USB keyboard on Tegra's Seaboard/Springbank boards to work. Cc: Patrick Georgi <patrick@georgi-clan.de> Cc: Vincent Palatin <vpalatin@chromium.org> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-06-12usb: gadget: add Faraday FOTG210 USB gadget supportKuo-Jung Su
The Faraday FOTG210 is an OTG chip which could operate as either an EHCI Host or a USB Device at a time. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
2013-06-12usb: ehci: add Faraday USB 2.0 EHCI supportKuo-Jung Su
This patch adds support to both Faraday FUSBH200 and FOTG210, the differences between Faraday EHCI and standard EHCI are listed bellow: 1. The PORTSC starts at 0x30 instead of 0x44. 2. The CONFIGFLAG(0x40) is not only un-implemented, and also has its address space removed. 3. Faraday EHCI is a TDI design, but it doesn't compatible with the general TDI implementation found at both U-Boot and Linux. 4. The ISOC descriptors differ from standard EHCI in several ways. But since U-boot doesn't support ISOC, we don't have to worry about that. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
2013-06-12usb: hub: make minimum power-on delay configurableKuo-Jung Su
This patch makes the minimum power-on delay for USB HUB become configurable. The original design waits at least 100 msec here, but some EHCI controlers(e.g. Faraday EHCI) are known to require much longer delay interval. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
2013-06-12usb: ehci: add weak-aliased function for PORTSCKuo-Jung Su
There is at least one non-EHCI compliant controller (i.e. Faraday EHCI) not only leave RESERVED and CONFIGFLAG registers un-implemented but also has their address spaces removed. As an result, the PORTSC register of Faraday EHCI always starts from 0x30 instead of 0x44 in standard EHCI. So that we'll need a weak-aliased function for abstraction. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
2013-06-12usb: ehci: prevent bad PORTSC register accessKuo-Jung Su
1. The 'index' of ehci_submit_root() is not always > 0. e.g. While it gets invoked from usb_get_descriptor(), the 'index' is always a '0'. (See ch.9 of USB2.0) 2. The PORTSC register is not always required, and thus it should only report a port error when necessary. It would cause a port scan failure if the ehci_submit_root() always gets terminated by a port error. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
2013-06-12usb: gadget: Use unaligned access for wMaxPacketSizeVivek Gautam
Use get_unaligned() while fetching wMaxPacketSize to avoid voilating any alignment rules. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Dalek <luk0104@gmail.com> Cc: Marek Vasut <marex@denx.de>
2013-06-12usb: Use get_unaligned() in usb_endpoint_maxp() for wMaxPacketSizeVivek Gautam
Use unaligned access to fetch wMaxPacketSize in usb_endpoint_maxp() api. In its absence we see following data abort message: ============================================================== data abort MAYBE you should read doc/README.arm-unaligned-accesses pc : [<bf794e24>] lr : [<bf794e1c>] sp : bf37c7b0 ip : 0000002f fp : 00000000 r10: 00000000 r9 : 00000002 r8 : bf37fecc r7 : 00000001 r6 : bf7d8931 r5 : bf7d891c r4 : bf7d8800 r3 : bf7d65b0 r2 : 00000002 r1 : bf7d65b4 r0 : 00000027 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... ============================================================== Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Marek Vasut <marex@denx.de>
2013-06-12usb: asix: Move software resets to basic_initJulius Werner
The ASIX driver calls a basic_init() function during get_info(), so that not all initialization tasks need to be redone on every init(). Unfortunately, the most important one is still triggered too often: the driver does a full port and MII reset on every asix_init(), requiring up to several seconds to reestablish the link. This patch confines that software reset into the asix_basic_init() function so that it will only be executed once. This saves about a second of boot time on systems using BOOTP. Note: this patch was previously submitted many moons ago as: usb: usbeth: asix: Do a fast init if link already established That patch seens to have been lost or forgotten, so this is a rebased version. It is tested on snow with a Asix USB dongle (Cisco). Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2013-06-12usb: Correct CLEAR_FEATURE code in ehci-hcdSimon Glass
This commit broke USB2 on link (Chromebook Pixel): 020bbcb usb: hub: Power-cycle on root-hub ports However the root cause seems to be a missing mask and missing 'break' in ehci-hcd.c. This patch fixes both. On link, 'usb start' with a USB keyboard and memory stick inserted now finds both. The keyboard works as expected. Also ext2ls shows a directory listing from the memory stick. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-12usb: workaround non-working keyboards.Vincent Palatin
If the USB keyboard is not answering properly the first request on its interrupt endpoint, just skip it and try the next one. This workarounds an issue with a wireless mouse dongle which presents itself both as a keyboard and a mouse but has a non-functional keyboard interface. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 012bbf0ce0301be2482857e3f03b481dd15c2340) Rebased to upstream/master: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
2013-06-12usb: properly re-initialize the USB keyboard.Vincent Palatin
Allow to reconfigure properly the USB keyboard driver when we enumerate several times the USB devices and its position in the device tree has changes. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
2013-06-11Merge branch 'master' of git://git.denx.de/u-boot-74xx-7xxTom Rini
2013-06-11ppc: ppmc7xx: Fix possible out-of-bound accessMarek Vasut
The flash_info_t->start[] field is limited in size by CONFIG_SYS_MAX_FLASH_SECT macro, which is set to 19 for this board in the board config file. If we inspect the board/ppmc7xx/flash.c closely, especially the flash_get_size() function, we can notice the "switch ((long)flashtest)" at around line 80 having a few results which will set flash_info_t->sector_count to value higher than 19, for example "case AMD_ID_LV640U" will set it to 128. Notice that right underneath, iteration over flash_info_t->start[] happens and the upper bound for the interation is flash_info_t->sector_count. Now if the sector_count is 128 as it is for the AMD_ID_LV640U case, but the CONFIG_SYS_MAX_FLASH_SECT limiting the start[] is only 19, an access past the start[] array much happen. Moreover, during this iteration, the field is written to, so memory corruption is inevitable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Richard Danter <richard.danter@windriver.com>
2013-06-11powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7Scott Wood
C99's strict aliasing rules are insane to use in low-level code such as a bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the past, add a union so that 16-bit accesses can be performed. Compile-tested only. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2013-06-10cosmetic: arm: fix comments in arch/arm/lib/crt0.SMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-06-10Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-06-10arm/km: make local functions staticHolger Brunck
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
2013-06-10arm: da830: moved pinmux configurations to the arch treeVishwanathrao Badarkhe, Manish
Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
2013-06-10ARM: DRA7: Add MaintainerLokesh Vutla
Adding Maintainer for DRA7xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10OMAP5: Enable access to auxclk registersLubomir Popov
auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-06-10ARM: OMAP: I2C: New read, write and probe functionsLubomir Popov
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older OMAPs and derivatives as well. The only anticipated exception would be the OMAP2420, which shall require driver modification. - Rewritten i2c_read to operate correctly with all types of chips (old function could not read consistent data from some I2C slaves). - Optimised i2c_write. - New i2c_probe, performs write access vs read. The old probe could hang the system under certain conditions (e.g. unconfigured pads). - The read/write/probe functions try to identify unconfigured bus. - Status functions now read irqstatus_raw as per TRM guidelines (except for OMAP243X and OMAP34XX). - Driver now supports up to I2C5 (OMAP5). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Heiko Schocher <hs@denx.de>
2013-06-10arm: Remove OMAP2420H4 and all omap24xx supportTom Rini
The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
2013-06-10da830: add MMC supportVishwanathrao Badarkhe, Manish
Add MMC support for da830 boards in order to perform mmc operations(read,write and erase). Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
2013-06-10ARM: OMAP5: Power: Add more functionality to Palmas driverLubomir Popov
Add some useful functions, and the corresponding definitions. Add support for powering on the dra7xx_evm SD/MMC LDO (courtesy Lokesh Vutla <lokeshvutla@ti.com>). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-06-10ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R
DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-06-10ARM: DRA7xx: Update pinmux dataLokesh Vutla
Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
2013-06-10mmc: omap_hsmmc: Update pbias programmingBalaji T K
Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: Correct SRAM END addressSricharan R
NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: Change the Debug UART to UART1Sricharan R
Serial UART is connected to UART1. So add the change for the same. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-06-10ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla
Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon
DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: clocks: Fixing i2c_init for PMICLokesh Vutla
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla
TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: DRA7xx: Add control id code for DRA7xxLokesh Vutla
The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla
Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla
To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: OMAP5: clocks: Do not enable sgx clocksSricharan R
SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10ARM: OMAP4+: Cleanup header filesLokesh Vutla
After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10OMAP5: Fix bug in omap5_es1_prcm structLubomir Popov
The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Tom Rini <trini@ti.com>
2013-06-10OMAP5: add ABB setup for MPU voltage domainAndrii Tseglytskyi
Patch adds a call of abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
2013-06-10OMAP3+: introduce generic ABB supportAndrii Tseglytskyi
Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
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