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2013-07-26am335x_evm: Add basic READMETom Rini
Add a README for the family of boards the am335x_evm covers, and include instructions on preparing and using falcon mode, for various media. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2013-07-26am335x_evm: Correct CONFIG_CMD_SPL_WRITE_SIZETom Rini
We use CONFIG_CMD_SPL_WRITE_SIZE when reading/writing the args portion of falcon mode to NAND. Previously it was half the size of the eraseblock which is too small, increase to eraseblock size. Signed-off-by: Tom Rini <trini@ti.com>
2013-07-26am335x_evm: Update eMMC falcon mode locationsTom Rini
The previous location used for the "args" portion of falcon mode was too small to allow for a device tree to be saved there, so move the location slightly and increase the size. In addition, our previous kernel location was part of the area we set aside for U-Boot itself, so move it up a bit higher. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-07-26am335x_evm: Correct DFU ALT settings for falcon modeTom Rini
Now that we have falcon mode enabled, the partiton numbers for NAND have changed, and we need to list entries for updating these parts of the system. While adding falcon mode entires for eMMC (raw), we round up the limit on U-Boot for ease of math later. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-07-26README.falcon: Note how we determine if we can boot the OS or notTom Rini
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
2013-07-26omap3/sys_info: fix printout of OMAP36XX L3 freqencyAndreas Bießmann
The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-07-26spl_mmc.c: Detect missing kernel image in RAW MMCTom Rini
Currently, we assume that if we can read from MMC correctly, we have found a valid image. This is not the case as an empty area will read just fine. Add a check for a valid IH_MAGIC. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-07-26da850evm: Use clrbits function with correct endianessChristian Riesch
The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
2013-07-26arm: omap3: spl: Fix problem with 8bit NAND devicesStefan Roese
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
2013-07-25Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD
2013-07-25Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini
2013-07-25qemu-malta: Update for SPDX license identifiersTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
Conflict over SPDX changes means that one change was effectively dropped as it was fixing typos in a removed hunk of text. Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25drivers/i2c: Update fti2c010.[ch], i2c_core.c to use SPDX identifiersTom Rini
Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25socfpga: Move board/socfpga_cyclone5 to board/socfpgaDinh Nguyen
Because the SOCFPGA platform will include support for Cyclone V and Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to be more generic. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> v2: - Add Reviewed-by: Pavel Machek - Cc: Tom Rini
2013-07-25nds32: Enable FPU if the version of CPU supportedken kuo
Some version of Andes core support FPU coprocessor, if this is the case, and toolchain support FPU instruction set, we should enable it at low level initialization time. Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-25nds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiersTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-25nds32: Convert Makefiles to use COBJS-y styleken kuo
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
2013-07-25highbank: enable keyed autoboot stopRob Herring
Restrict autoboot interruption to "s" or "d" keys. This will prevent some unwanted stopping and also allow disabling the reset on command timeout. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: compile misc_init_r only if CONFIG_MISC_INIT_RRob Herring
Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: setup peripherals based on power domain statusRob Herring
Accessing powered down peripherals will hang the bus, so check power domain status before initializing SATA and fixup the FDT to disable unused peripherals. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: enable reset on command timeoutRob Herring
Enable resetting on command timeout. The timeout is set with environment setting bootretry. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: avoid bss write in timer_initRob Herring
The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: set timer prescaler to 256Rob Herring
The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: fix get_tbclk value to timer rateRob Herring
get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: highbank: update config optionsRob Herring
Various changes to highbank config: Enable EFI partitions Enable ext4 and FAT filesystems Enable bootz command and raw initrd Increase cmd and print buffer size to 1K Change serial baudrate to 115200 Enable hush shell Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25net: calxedaxgmac: enable rx cut-thruRob Herring
There is no reason to wait for the entire frame to start DMA on receive, so enable rx cut-thru for better performance. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25ARM: move interrupt_init to before relocationRob Herring
interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-24MIPS: mips32/cache.S: use v1 register for indirect function callsGabor Juhos
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/cache.S: store cache line size in t8 registerGabor Juhos
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/cache.S: save return address in t9 registerGabor Juhos
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: xburst/start.S: rework relocation info checkGabor Juhos
Make it similar to the code in mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: xburst/start.S: use t8 register for dynamic relocationGabor Juhos
Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: xburst/start.S: save gd in s0 registerGabor Juhos
Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: xburst/start.S: save relocation offset in s1 registerGabor Juhos
Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: xburst/start.S: save relocation address in s2 registerGabor Juhos
Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/start.S: rework relocation info checkGabor Juhos
Make it similar to the code in mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/start.S: use t8 register for dynamic relocationGabor Juhos
Synchronize the code with mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/cache.S: remove superfluous register assignmentGabor Juhos
The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-07-24MIPS: remove obsolete TODO itemsGabor Juhos
The MIPS code uses centralized u-boot.lds script already, and dynamic relocation is supported as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips64/interrupt.c: remove superfluous includeGabor Juhos
Nothing is used from asm/mipsregs.h. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: mips32/time.c: fix checkpatch errors/warningsGabor Juhos
Checking mips32/time.c with checkpatch.pl shows this: arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked Fix the code to make checkpatch.pl happy. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: bring up ethernetGabor Juhos
Qemu emulates a PCNET PCI card for the Malta CoreLV board. Enable the pcnet driver and add board specific ethernet initialization function to bring it up. Also enable the CONFIG_CMD_NET and CONFIG_CMD_PING options. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: add PCI supportGabor Juhos
Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: setup GT64120 registers as done by YAMONGabor Juhos
Move the GT64120 register base to 0x1be00000 and setup PCI BAR registers as done by the original YAMON bootloader. This is needed for running Linux kernel. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: enable flash supportGabor Juhos
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: add reset supportGabor Juhos
The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset. Use this feature to implement reset support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: qemu-malta: add support for emulated MIPS Malta boardGabor Juhos
Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: start.S: emulate REVISION register for qemu-maltaGabor Juhos
On the origial Malta boards the REVISION register is accessible at the 0x1fc00010 address. The contents of this register gives information about the revision of the Malta and Core Boards. This register is used by the Linux kernel to identify the actual board it is running on. However the register is not emulated properly by Qemu, so put a hardcoded value into the flash to make Linux work. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24MIPS: import gt64120.h header from LinuxGabor Juhos
The Linux specific register access macros, the extern function declarations and the UL suffixes has been removed. The header file will be used for the qemu-malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
generated by cgit (git 2.34.1) at 2025-01-15 15:37:46 +0000