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2015-01-14videomodes: Add (vesa) standard timingsHans de Goede
The timings for the modes defined in videomodes.c differ (significantly) from vesa standard timings for these modes. This commit adds a version with the proper std timings for these modes, since I do not want to cause regressions, boards which want to use the standard timings need to define CONFIG_VIDEO_STD_TIMINGS to get the new correct timings. Since there is no std timing for 960x720 this commit uses the timing used by the nvidia video drivers for 960x720, which uses a standard pixelclock of 74.25 MHz rather then the weird 76.335... clock used by the old modes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14videomodes: Add pixelclock_khz and refresh fields to ctfb_res_modesHans de Goede
Add pixelclock_khz and refresh fields to ctfb_res_modes: 1) pixelclocks are usually referred to in hz, not picoseconds, and e.g pll-s are also typically programmed in hz, not ps. Converting between the 2 leads to rounding differences, add a pixelclock_khz field to directly store the *exact* pixelclock for a mode, so that drivers do not need to resort to rounding tricks to try and guess the exact pixelclock; 2) The video-mode environment variable, as parsed by video_get_video_mode also contains the vertical refresh rate, add a refresh field, so that the refresh-rate can be matched when parsing the video-mode environment variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14sun7i: Add new Bananapro board / defconfigHans de Goede
Add support for the new Bananapro A20 development board from lemaker.org. This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver, 3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Fix PLL1 running at half speed on sun8iHans de Goede
PLL1 on sun6i / sun8i also has a p factor which divides the clock by 2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is used and we were setting it to 1, resulting in the CPU running at 504 MHz instead of 1008 MHz, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Fix buggy sun6i/sun8i DRAM size detection logicSiarhei Siamashka
After reboot, reset or even short power off, DRAM typically retains the old stale data for some period of time (for this type of memory, the bits of data are stored in slowly discharging capacitors). The current sun6i/sun8i DRAM size detection logic, which is inherited from the Allwinner code, relies on using a large magic signature with the hope that it is unique enough and unlikely to ever accidentally match this leftover garbage data in RAM. But this approach is inherently unsafe, as can be demonstrated using the following test program: /***** A testcase for reproducing the problem ******/ void main(int argc, char *argv[]) { size_t size, i; uint32_t *buf; /* Allocate the buffer */ if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) || !(buf = malloc(size))) { printf("Need buffer size in MiB as a cmdline argument\n"); exit(1); } /* Fill it with the Allwinner DRAM "magic" values */ for (i = 0; i < size / 4; i++) buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64; /* Try to reboot */ system("reboot"); /* And wait */ for (;;) {} } /***************************************************/ If this test program is run on the device (giving it a large chunk of memory), then the DRAM size detection logic in u-boot gets confused after reboot and fails to initialize DRAM properly. A better approach is not to rely on luck and abstain from making any assumptions about the properties of the leftover garbage data in RAM. Instead just use a more reliable code for testing whether two different addresses refer to the same memory location. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14sun7i: Add defconfig for MSI Primo73 tabletSiarhei Siamashka
This patch uses the same DRAM settings as in the pre-installed Android firmware. The LCD display is supported too. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14sun6i: Add defconfig for MSI Primo81 tabletSiarhei Siamashka
This patch uses the same ZQ and DRAM clock settings as in the pre-installed Android firmware. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14sunxi: Fix CONFIG_UART0_PORT_F build and add it to menuconfigSiarhei Siamashka
The CONFIG_UART0_PORT_F option has been supported since http://git.denx.de/?p=u-boot.git;a=commit;h=ff2b47f6a9cc1025 This option is primarily useful only for low level u-boot debugging on tablets, where normal UART0 is difficult to access and requires device disassembly and/or soldering. This patch now allows it to be selected from menuconfig. A dependency on SPL_FEL is added because u-boot does not support booting from NAND yet and also booting from SD card is impossible when a MicroSD breakout board is plugged into the SD slot. Additionally a compilation problem is fixed: common/spl/built-in.o: In function `spl_mmc_load_image': /tmp/u-boot-sunxi/common/spl/spl_mmc.c:94: undefined reference to `mmc_initialize' /tmp/u-boot-sunxi/common/spl/spl_mmc.c:96: undefined reference to `find_mmc_device' /tmp/u-boot-sunxi/common/spl/spl_mmc.c:104: undefined reference to `mmc_init' scripts/Makefile.spl:206: recipe for target 'spl/u-boot-spl' failed Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14sun8i: Add defconfig for Ippo_q8h v1.2Hans de Goede
We need separate defconfigs for the v5 and v1.2 versions of this board, as they use different DRAM parameters. Note they also use different dtb files, as the wifi is different too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun8i: Ippo_q8h_v5_defconfig: Enable SPL supportHans de Goede
Now that we've sun8i dram-init support we can enable the SPL for sun8i boards. While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE, the former is for u-boot's own fdt usage, which we do not use (yet), the later specifies the fdt to pass to the kernel, which is the one we want. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun8i: Add dram initialization supportHans de Goede
Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Use memcmp for mctl_mem_matchesHans de Goede
Use memcmp for mctl_mem_matches instead of DIY. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Fill memory before comparing it when doing dram init on sun6iHans de Goede
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing it at different offsets to do columns, etc. detection. The sun6i boot0 code does not do it, instead relying on the memory contents being random enough to begin with for the memcmp to properly detect the wrap-around address, iow it is working purely by chance. Since our sun6i dram code was modelled after the boot0 code it contained the same issue. This commit fixes this by filling the memory with a unique, distinct pattern. The new mctl_mem_fill function this introduces is added as an inline helper in dram.h, so that it can be shared with the sun8i dram code. While at it move mctl_mem_matches to dram.h for re-use in sun8i too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Move await_completion dram helper to dram.hHans de Goede
The await_completion helper is already copy pasted between the sun4i and sun6i dram code, and we need it for sun8i too, so lets make it an inline helper in dram.h, rather then adding yet another copy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: clock_set_pll5: Calculate k and m rather then hardcoding themHans de Goede
Our old hardcoded k and m values are based on PLL5 being configured in steps of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i) the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps. This commit adjusts clock_set_pll5 to automatically select the best k and m depending on the requested clk rate. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()Hans de Goede
The sun8i dram code sometimes wants to enable sigma delta mode, add a parameter to allow this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: axp221: Disable dcdc4 on sun8i (A23)Hans de Goede
dcdc4 is not used on sun8i, disable it. While at it also add comments to the other fixed voltages to document what they are used for. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: axp221: Explicitly turn off unused voltagesHans de Goede
Explicitly turn off unused voltages, rather then leaving them as is. Likewise explictly enabled the dcdc convertors, rather then assuming they are already enabled at boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: axp221: Make dcdc1 voltage configurableHans de Goede
The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to safe battery, but not on all, make it configurable so that we can use the same settings as the original firmware on all boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usageHans de Goede
Some of the ldo-s of the axp221 are used in the same way on most boards, add comments to the Kconfig help text to reflect this, and give them defaults matching their typical usage. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: axp221: Add axp223 supportHans de Goede
The axp223 appears to be the same as the axp221, except that it uses the rsb to communicate rather then the p2wi. At least all the registers we use are 100% the same. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Add support for the rsb (Reduced Serial Bus)Hans de Goede
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/Hans de Goede
The p2wi interface is only available on sun6i, adjust the gpio pinmux and base address defines for it to reflect this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14mmc: sunxi: Fix misuse of gpio_direction_input()Axel Lin
It does not make sense to make gpio_direction_input() return the gpio input status. The return value of gpio_direction_input() is inconsistent if CONFIG_DM_GPIO is defined. And we don't need to call gpio_direction_input() int sunxi_mmc_getcd(). Just init the gpio once in mmc_resource_init() is enough. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: Align PSCI stack calculation to commentJan Kiszka
0x400 is true 1K. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Add new board Merrii Hummingbird A31Chen-Yu Tsai
The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14sunxi: Add sunxi_get_sid helper functionHans de Goede
On sun6i the SID is stored in the pmic, rather then in the SoC itself, add a helper function to abstract this away. This makes our MAC address generation code also work on sun6i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: axp221: Add axp221_get_sid functionHans de Goede
For sun6i the SID is stored in the pmic, rather then in the SoC itself, add a function to retreive the sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sunxi: mmc: Properly setup mod-clk and clock sampling phasesHans de Goede
The sunxi mmc controller has both an internal clock divider, as well as the divider in the mod0-clk for the mmc controller. The internal divider cannot be used, as it conflicts with the setting of clock sampling phases which is done in the mod0-clk, so it must be set to 0 (divide by 1). For some reason while the kernel has had this correct from day one, the u-boot sunxi mmc code has been using a fixed mod0-clk and setting its internal divider depending on the desired speed. This is something which we've inherited from the original Allwinner u-boot sources, but while this has been fixed in Allwinner's own u-boot code at least for the A23 and later upstream u-boot was still doing this wrong. This commit fixes this, thereby also fixing mmc support not working reliable on the A23 (which seems more sensitive to this) and possible also fixes some other sunxi mmc issues. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Update Colombus defconfig settingsHans de Goede
The Colombus defconfig settings are missing a number of settings for recently added features, because we did not know exactly how things were hooked up. Maxime Ripard has run various tests to get us the necessary details, this commit updates the defconfig with this info. This commit also updates the dram clk and zq values with values verified by Maxime to be the ones used by the original firmware for this board. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Add new CSQ_CS908 boardHans de Goede
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND, rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG controller), ethernet, 3.5 mm jack with a/v out and hdmi out: http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html Note it has no sdcard slot and therefore can only be fel booted. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: dram: Do not try to initialize a second dram chan on A31sHans de Goede
The A31s only has one dram channel, so do not bother with trying to initialize a second channel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Add sunxi_get_ss_bonding_id() functionHans de Goede
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between the A31s and the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14sun6i: Make dram clk and zq value Kconfig optionsHans de Goede
It turns out that there is a too large spread between boards to handle this with a default value, turn this into Kconfig options, and set the values the factory images are using for the Colombus and Mele_M9 boards. Note this changes the ZQ default when not overriden through defconfig from 120 to 123, as that is what most boards seem to actually use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-13omap5: Add netargs and netboot optionCooper Jr., Franklin
* Add netargs and netboot option. * This enables tftp and nfs booting * This puts omap5 devices inline with other devices such as am335x and am437x Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
2015-01-13arm: omap3: devkit8000: inherit from ti_omap3_common.hAnthoine Bourgeois
Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
2015-01-13arm: omap3: devkit8000: inherit from ti_armv7_common.hAnthoine Bourgeois
2015-01-13pcm051: Add boot script support to pcm051matwey.kornilov@gmail.com
This patch adds boot script support to pcm051 Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2015-01-13board: ti: am43xx: add support for AM43xx Industrial Development KitFelipe Balbi
AM43xx Industrial Development Kit is a new board based on AM437x line of SoCs. Targetted at Industrial Automation applications, it comes with EtherCAT, motor control and other goodies. Thanks to James Doublesin for all the help. Cc: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13pmic: add tps62362 simple wrapper codeFelipe Balbi
This regulator is used with AM437x IDK to feed VDD_MPU, without means to scale VDD_MPU we can't support higher frequencies. Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13Merge git://git.denx.de/u-boot-x86Tom Rini
2015-01-13board: ti: am43xx: take care of all OPPsFelipe Balbi
Make sure that all OPPs are checked on scale_vcores(). While at that also fix 600MHz VDD_MPU voltage according to AM437x Data Manual available at [1]. Table 5-3 on that document, lists all valid voltages per frequency. [1] http://www.ti.com/lit/ds/symlink/am4379.pdf Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13power: tps65218: define all valid VDD_MPU voltagesFelipe Balbi
DCDC1 is used as VDD_MPU in all known boards, let's define all other valid voltages for that rail so it can be used by our boards. Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13board: ti: am43xx: replace if else if else with a switchFelipe Balbi
A switch statement fits better in this case, specially considering we have a few extra frequencies to use. Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13arm: am437x: Correct PLL frequency for 25MHzJames Doublesin
The frequencies for 25MHz in dpll_per were out of spec for 25MHz, correct. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13arm: am437x: Enable hardware leveling for EMIFJames Doublesin
Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length. Tested-by: Felipe Balbi <balbi@ti.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2015-01-13arm: am437x: PLL values for all input frequenciesJames Doublesin
Need to provide PLL values for all possible input frequencies (19.2, 24, 25, 26MHz). Values provide are also optimized for jitter (needed especially for PER PLL and DDR PLL). Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-01-13mtd: OMAP: Enable GPMC prefetch modeDaniel Mack
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read access a lot by pre-fetching contents in the background and reading them through the FIFO address. The current implementation has two limitations: a) it only works in 8-bit mode b) it only supports read access Both is easily fixable by someone who has hardware to implement it. Note that U-Boot code uses non word-aligned buffers to read data into, and request read lengths that are not multiples of 4, so both partial buffers (head and tail) have to be addressed. Tested on AM335x hardware. Tested-by: Guido Martínez <guido@vanguardiasur.com.ar> Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar> Signed-off-by: Daniel Mack <zonque@gmail.com> [trini: Make apply again, use 'cs' fix pointed out by Guido] Signed-off-by: Tom Rini <trini@ti.com>
2015-01-13x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.hBin Meng
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove it to avoid duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Update README.x86 for coreboot supportBin Meng
Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>