summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-07-13README: davinci: Clarify when SPL is used and the target devices.Adam Ford
The documentation states that SPL is enabled in all config options for the da850. This incorrect, because devices booting from NOR do not need the SPL to do the low level initializion because when booting from NOR, the board is able to execute in place (XIP) This also clarifies that SPL isn't only used for booting from SPI, because it is also used for booting from MMC and NAND for those devices supporting those boot options. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-13arm: dts: k3-am65: Sync CPSW DT node from kernelVignesh Raghavendra
Sync CPSW DT node from kernel and move it out of -u-boot.dtsi file. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13arm: dts: k3-j721e: Sync CPSW DT node from kernelVignesh Raghavendra
Sync CPSW DT node from Kernel and move it out of -u-boot.dtsi file. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Update driver to use kernel DTVignesh Raghavendra
Kernel DT has CPSW ports under ethernet-ports subnode. Update the driver to look for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Set ALE default thread enableVignesh Raghavendra
Force default thread to be used for RX as ALE is anyways set to Bypass mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Remove dead codeVignesh Raghavendra
MDIO node is not referenced further, therefore drop the dead code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Switch to k3_ringacc_request_rings_pairVignesh Raghavendra
We only request ring pairs via K3 DMA driver, switch to use the new k3_ringacc_request_rings_pair() to simplify the code. As a good side effect, all boot stages now use exposed RING mode which avoid maintaining proxy mode for 32 bit R5 core. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Move RX descriptor ring entries to rflow structVignesh Raghavendra
In K3 UDMA architecture, RX rings are associated with RX flows rather than RX channels, therefore move the ring pointers to udma_rflow struct Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Introduce udma_chan_config structVignesh Raghavendra
Encapsulate channel configuration in a separate struct so as to ease resetting of these fields with memset() and also to increase readability of the code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Separate soc specific initializationVignesh Raghavendra
In preparation of adding more K3 SoCs, separate soc specific initialization add a SoC specific initialization hook. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Add an API to request pair of ringsVignesh Raghavendra
Add new API k3_ringacc_request_rings_pair() to request pair of rings at once, as in the most case Rings are used with DMA channels which required to request pair of rings - one to feed DMA with descriptors (TX/RX FDQ) and one to receive completions (RX/TX CQ). This will allow to simplify Ringacc API users. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Move state tracking variables under a structVignesh Raghavendra
Move the free, occ, windex and rinfex under a struct. We can use memset to zero them and it will allow a cleaner way to extend the variables for duplex rings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DTVignesh Raghavendra
Sync DT bindings from kernel DT and move them to out of -u-boot.dtsi files. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-13dma: ti: k3-udma: Update driver to use static endpoint DataVignesh Raghavendra
Update driver to use static PSIL endpoint Data instead of DT. This will allow DT bindings to be in sync with kernel's DT. Note that this patch breaks networking and OSPI boot as driver changes are not backward compatible with existing DT. Subsequent commit will update the DT to make it compatible with updated driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-13dma: ti: Add static PSIL endpoint informationVignesh Raghavendra
Much of PSIL endpoint configuration for a given SoC can be known at compile time, therefore pass them for platform specific data instead of DT. Add per SoC's specific PSIL endpoint data. This is to bring driver in sync with upstream DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-11Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- Enable DM_SPI on siemens omap boards (Jagan) - Dropped some non-dm supported omap3 boards (Jagan) - Dropped non-dm code in omap3 spi driver (Jagan) - Dropped non-dm code in kirkwood spi driver (Bhargav)
2020-07-11Merge tag 'uniphier-v2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.10 - remove workaround for Cortex-A72 - increase U-Boot proper size to 2MB - sync DT with Linux - add system bus controller driver - improve serial driver - add reset assertion to Denali NAND driver
2020-07-11ARM: uniphier: remove NAND reset codeMasahiro Yamada
Now that commit 3e57f879eee6 ("mtd: nand: raw: denali: Assert reset before deassert") added the reset assertion, this code in the board file is unneeded. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11mtd: nand: raw: denali: Wait for reset completion statusLey Foon Tan
Fixed delay 200us is not working in certain platforms. Change to poll for reset completion status to have more reliable reset process. Controller will set the rst_comp bit in intr_status register after controller has completed its reset and initialization process. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11mtd: nand: raw: denali: Assert reset before deassertLey Foon Tan
Always put the controller in reset, then take it out of reset. This is to make sure controller always in reset state in both SPL and proper Uboot. This is preparation for the next patch to poll for reset completion (rst_comp) bit after reset. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: enable FIFOMasahiro Yamada
This UART controller is integrated with a FIFO. Enable it. You can put the next character into the FIFO while the transmitter is sending out the current character. This works slightly faster. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: flush transmitter before changing hardware settingsMasahiro Yamada
Ensure the transmitter is empty when chaining the baudrate or any hardware settings. If a character is remaining in the transmitter, the console will be garbled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: use register macros instead of structureMasahiro Yamada
After all, I am not a big fan of using a structure to represent the hardware register map. You do not need to know the entire register map. Add only necessary register macros. Use FIELD_PREP() instead of maintaining a pair of shift and mask. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove sbc/ directoryMasahiro Yamada
Now that this directory contains only uniphier_sbc_boot_is_swapped(), move it to boot-device.c and delete the sbc/ directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: move hardware init from board filesMasahiro Yamada
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: add UniPhier System Bus driverMasahiro Yamada
Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based drivers/net/smc911x.c is compiled, but it is never probed because the parent node lacks the DM-based driver. I need a skeleton driver to populate child devices (but the next commit will move more hardware settings to the this driver). I put this to drivers/bus/uniphier-system-bus.c because this is the same path as the driver in Linux kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove support for NOR Flash on support cardMasahiro Yamada
I actually do not see this used these days because eMMC or NAND is used for non-volatile devices. Dump the burden to maintain this crappy code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: remove unused uniphier_sbc_init_admulti()Masahiro Yamada
This was used by the old sLD3 SoC, the support of which was removed by commit 00aa453ebf56 ("ARM: uniphier: remove sLD3 SoC support"). There is no more user of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: fix build error when CONFIG_MICRO_SUPPORT_CARD=nMasahiro Yamada
If CONFIG_MICRO_SUPPORT_CARD is unset, the build fails due to function redefinition. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: sync with Linux 5.8-rc4Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: consolidate SoC select menuMasahiro Yamada
Currently, the supports for the following two ARMv7 SoC groups are exclusive, because the boot ROM loads the SPL to a different address: - LD4, sLD8 (SPL is loaded at 0x00040000) - Pro4, Pro5, PXs2, LD6b (SPL is loaded at 0x00100000) This limitation exists only when CONFIG_SPL=y. Instead of using crappy CONFIG options, checking SPL and SPL_TEXT_BASE is cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN to 2MBMasahiro Yamada
I increased the maximum U-Boot proper size from time to time, but configs/uniphier_v7_defconfig hit the current limit 832KB. Some historical info: In the initial support, the max size was 512MB. Commit 58d702274c09 ("ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN") increased it to 576KB, and commit 3ce5b1a8d86d ("ARM: uniphier: move SPL stack address") moved the SPL stack location to avoid the memory map conflict. It was the solution to increase the size without changing the NOR boot image map. commit 1a4bd3a095b2 ("ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN again") ended up with increasing the max size again, breaking the NOR boot image map. The limit was set to 832KB, otherwise the SPL stack would overwrite the U-Boot proper image: CONFIG_SPL_STACK - CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header) = 0xd0000 To increase CONFIG_SYS_MONITOR_LEN even more, the SPL stack must be moved somewhere. I put it back to the original location prior to commit 3ce5b1a8d86d. With this change, there is no more practical size limit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11Revert "ARM: uniphier: add weird workaround code for LD20"Masahiro Yamada
This reverts commit 45f41c134baf5ff1bbf59d33027f6c79884fa4d9. This weird workaround was the best I came up with at that time to boot U-Boot from TF-A. I noticed U-Boot successfully boots on LD20 (i.e. CA72 CPU) by using the latest TF-A. Specifically, since the following TF-A commit, U-Boot runs at EL2 instead of EL1, and this issue went away as a side-effect. |commit f998a052fd94ea082833109f25b94ed5bfa24e8b |Author: Masahiro Yamada <yamada.masahiro@socionext.com> |Date: Thu Jul 25 10:57:38 2019 +0900 | | uniphier: run BL33 at EL2 | | All the SoCs in 64-bit UniPhier SoC family support EL2. | | Just hard-code MODE_EL2 instead of using el_implemented() helper. | | Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> However, if I reverted that, this problem would come back, presumably because some EL1 code in U-Boot triggers this issue. Now that commit f8ddd8cbb513 ("arm64: issue ISB after updating system registers") fixed this issue properly, this weird workaround is no longer needed irrespective of the exception level at which U-Boot runs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-10Merge tag 'dm-pull-10jul20' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata: better phandle and compatible-string support patman support for Python3 on Ubuntu 14.04 new checkpatch check to avoid #ifdefs
2020-07-10CI: show skipped Python testsHeinrich Schuchardt
Call pytest3 with argument -ra to display the reason why Python tests are skipped. The -r flag displays a test summary info for each test. -ra eliminates this info for passed tests. Pros an cons were discussed in: https://lists.denx.de/pipermail/u-boot/2020-June/417090.html Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-10Merge tag 'rpi-next-2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10Merge branch '2020-08-10-arbitrary-virt-phys-mappings'Tom Rini
- Bring in Marek Szyprowski's series to allow for arbitrary virtual-physical address mappings.
2020-07-10config: Enable support for the XHCI controller on RPI4 boardMarek Szyprowski
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)Marek Szyprowski
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10mmc: bcm283x: fix int to pointer castSeung-Woo Kim
On build with 32 bit, there is a warning for int-to-pointer-cast. Fix the int to pointer cast by using uintptr_t. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10arm: provide a function for boards init code to modify MMU virtual-physical mapMarek Szyprowski
Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10arm: update comments to the common styleMarek Szyprowski
Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10powerpc: move ADDR_MAP to KconfigMarek Szyprowski
Move ADDR_MAP related config options from include/configs/*.h to the proper place in lib/Kconfig. This has been done using ./tools/moveconfig.py and manual inspection of the generated changes. This is a preparation to use ADDR_MAP helper on ARM 32bit Raspberry Pi4 board for mapping the PCIe XHCI MMIO, which is above the 4GiB identity mapping limit. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10config: Enable USB Keyboard support on RPi4Nicolas Saenz Julienne
Supporting USB keyboards out of the box is both handy for development and production. Notably if u-boot is used to boot into GRUB. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [mb: drop rpi_4_32b_defconfig hunk] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10usb: xhci: Add reset controller supportNicolas Saenz Julienne
Some atypical users of xhci might need to manually reset their xHCI controller before starting the HCD setup. Check if a reset controller device is available to the PCI bus and trigger a reset. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> [mb: squash fix to only build xhci_reset_hw() if CONFIG_DM_BUS] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10configs: Enable support for reset controllers on RPi4Nicolas Saenz Julienne
This is required in order to access the reset controller used to initialize the board's xHCI chip. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10reset: Add Raspberry Pi 4 firmware reset controllerNicolas Saenz Julienne
Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10arm: rpi: Add function to trigger VL805's firmware loadNicolas Saenz Julienne
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware may either be loaded directly from an EEPROM or, if not present, by the SoC's VideCore (the SoC's co-processor). Introduce the function that informs VideCore that VL805 may need its firmware loaded. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)Marek Szyprowski
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI and USB commands. To get it working one has to call the following commands: "pci enum; usb start;", thus such commands have been added to the default "preboot" environment variable. One has to update their environment if it is already configured to get this feature working out of the box. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10pci: Add driver for Broadcom BCM2711 SoC PCIe controllerSylwester Nawrocki
This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
generated by cgit (git 2.34.1) at 2024-12-24 00:45:38 +0000