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2020-01-14imx: Add basic support for the NXP IMXRT10xx SoC familyGiulio Benetti
Add i.IMXRT family basic support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhcGiulio Benetti
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms with CONFIG_DM_MMC=y. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statementGiulio Benetti
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK instead. So building could result in failure due to missing mxc_get_clock(). Make if(CONFIG_IS_ENABLED(CLK)) an #if statement. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti
Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14serial_lpuart: add support for i.MXRTGiulio Benetti
Add i.MXRT compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 as done for i.MX8. It needs also to set baudrate the same way as i.MX8 does. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14serial_lpuart: add clock enable if CONFIG_CLK is definedGiulio Benetti
This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined. If clock is not found, because DM is not used, let's emit a warning and proceed, because serial clock could also be already enabled by non DM code. If clock is found but cna't be enabled then return with error. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14ARM: dts: imxrt1050: add dtsi fileGiulio Benetti
Add dtsi file for i.MXRT1050. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14gpio: mxc_gpio: add support for i.MXRT1050Giulio Benetti
Add i.MXRT1050 support, there are 5 GPIO banks. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14pinctrl: add i.MXRT driverGiulio Benetti
Add i.MXRT pinctrl driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: add i.IMXRT1050 clk driverGiulio Benetti
Add i.MXRT1050 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pfd: add set_rate()Giulio Benetti
Implement set_rate() for pfd. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti
Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add set_rate() supportGiulio Benetti
Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add disable() supportGiulio Benetti
Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: add enable() supportGiulio Benetti
Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti
div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti
Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibilityGiulio Benetti
Since some driver requires this function add it as an empty stub when DCACHE is OFF. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14spl: fix entry_point equal to load_addrGiulio Benetti
At the moment entry_point is set to image_get_load(header) that sets it to "load address" instead of "entry point", assuming entry_point is equal to load_addr, but it's not true. Then load_addr is set to "entry_point - header_size", but this is wrong too since load_addr is not an entry point. So use image_get_ep() for entry_point assignment and image_get_load() for load_addr assignment. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14imx: dts: imx8dx: add I2C IPG clock for bus 0 and 2Anatolij Gustschin
IPG clock description is missing for I2C0 and I2C2 busses, add it. Otherwise we see -ENODATA error when trying to get I2C clock for these busses. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2020-01-14clk: imx8qxp: extend to support getting I2C IPG clockAnatolij Gustschin
Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks doesn't work. Add I2C IPG clock IDs to related switch statements to fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-14ARM: dts: imx6ul-14x14-evk: Pass the "broken-cd" propertyFabio Estevam
imx6ul-14x14-evk does not have a GPIO dedicated for reading the card detect pin on the eSDHC2 port. In such cases the "broken-cd" property must be passed, otherwise the card cannot be detected. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14mmc: fsl_esdhc_imx: Handle the "broken-cd" propertyFabio Estevam
When no GPIO is used to read the card detect status the following error is seen: MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... MMC: no card present *** Warning - No block device, using default environment Fix it by handling the "broken-cd" property in the same way that drivers/mmc/sdhci.c does, which considers that the SD card is present when the "broken-cd" property is passed. Tested on a imx6ul-evk board. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14pico-imx7d: Convert to DM_ETHJoris Offouga
Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14pico-imx7d: Disable USB_ETHER support for bl33 defconfigJoris Offouga
For DM_ETH support , it's require to disable this config. When this config is enable, This generate a error with spl in linker script Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14mx6ul_14x14_evk: Fix SPL boot hangFabio Estevam
Currently the following SPL hang is observed: U-Boot SPL 2020.01-rc5-00079-g797eee36a1 (Jan 06 2020 - 11:24:09 -0300) Trying to boot from MMC1 Card did not respond to voltage select! spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Fix it by moving the eSDHC2 initialization to SPL. While at it, since this board uses DM_MMC all the esdhc board code can be removed to make the code simpler. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-01-14imx: imx8qxp_mek: update READMEPeng Fan
Update README to use 4.19.35_1.1.0 released firmware images. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-14wandboard: Do not print error message when PMIC is absentFabio Estevam
Only the wandboard revD1 boards have PMIC, so when running on a wandboard of different revision the following error is always shown on every boot: pmic_get() ret -19 Instead of printing this error message, move it to debug level instead. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-01-14imx8qxp_mek: Select CONFIG_NET_RANDOM_ETHADDRFabio Estevam
Some i.MX8QXP MEK boards do not have MAC address stored and hang during eth driver probe: Error: ethernet@5b040000 address not set. (Board hangs) To fix this problem select CONFIG_NET_RANDOM_ETHADDR so that a valid MAC address can be used in such case. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-01-14imx: add imx8x based deneb boardAnatolij Gustschin
Add support for Capricorn Deneb SoM variant. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-01-14imx: add imx8x capricorn giedi boardAnatolij Gustschin
Add support for i.MX8X based Capricorn Giedi SoM. Supported interfaces: GPIO, ENET, eMMC, I2C, UART. Console output: U-Boot SPL 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) Trying to boot from MMC1 Load image from MMC/SD 0x3e400 U-Boot 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) ##v01.07 CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C Model: Siemens Giedi Board: Capricorn Boot: MMC0 DRAM: 1022 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@5a080000 Out: serial@5a080000 Err: serial@5a080000 Net: eth1: ethernet@5b050000 [PRIME] Autobooting in 1 seconds, press "<Esc><Esc>" to stop Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-01-14tegra: fdt: Add tegra186-u-boot.dtsiStephen Warren
All Tegra chips except Tegra186 have a tegraNNN-u-boot.dtsi. Duplicate Tegra210's copy of this file for Tegra186. This ensures that a /binman node exists in U-Boot's control DT. Subsequent to 3c10dc95bdd0 ("binman: Add a library to access binman entries") this appears to be required. I haven't really investigated why all this is necessary or how it works, but simply observed the boot failure listed below, bisected it, noticed the inconsistency in DT files, and found that fixing it resolved the boot issue. U-Boot 2020.01-rc4-00256-g3c10dc95bdd0 (Jan 07 2020 - 10:25:00 -0700) SoC: tegra186 Model: NVIDIA P2771-0000-500 Board: NVIDIA P2771-0000 DRAM: 7.8 GiB initcall sequence 00000000fffb7858 failed at call 00000000800955a8 (err=-22) ### ERROR ### Please RESET the board ### Fixes: 3c10dc95bdd0 ("binman: Add a library to access binman entries") Fixes: f2faffecb016 ("binman: tegra: Convert to use binman") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-14arm64: versal: Enable board_late_init callingMichal Simek
Qemu v4.2.0 maps bootmode registers to address space which was the reason why board_late_init() was disabled and accesses were failing. With new Qemu board_late_init() can be called without any issue. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14ARM: dts: zynq: enablement of coresight topologyZumeng Chen
This patch is to build the coresight topology structure of zynq-7000 series according to the docs of coresight and userguide of zynq-7000. Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Sync gem clock nodes with mainline LinuxMichal Simek
Just fixing indentation and update year in Copyright. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Sync gpio-controller name locationMichal Simek
Sync location with mainline kernel. Added by Linux kernel commit 75926f07baae ("arm64: dts: zynqmp: Add missing gpio-controller to ps gpio"). Fixes: 0b33e0b15600 ("arm64: zynqmp: Add missing gpio property to dtsi") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: dts: zynqmp: replace gpio-key,wakeup with wakeup-source propertySudeep Holla
Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. This patch replaces the legacy properties with the unified "wakeup-source" property introduced by: "Input: gpio_keys - switch to using generic device properties" (sha1: 700a38b27eefc582099fdf69effacfad0ad738a4) Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: dts: zcu100-revC: Give wifi some time after power-onJan Kiszka
Somewhere along recent changes to power control of the wl1831, power-on became very unreliable on the Ultra96, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, Ultra96 is already happy with 10 ms. Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: dts: zynqmp: Fix node names which contain "_"Michal Simek
s/_/-/ for node names. It fixes warnings like this: ... Warning (node_name_chars_strict): /cpu_opp_table: Character '_' not recommended in node name ... Issues reported by make dtbs W=12 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-01-14arm64: zynqmp: Remove incorrect phy from DT for zcu102-revB upMichal Simek
zcu102-revB/up are not removing phy from revA properly because of incorrect name. Fixes: 2975a42b42c5 ("arm64: zynqmp: Use ethernet-phy as node name for ethernet phys") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Add support for zcu1285 revA boardMichal Simek
zcu1285 is the same as zcu1275 but it is using Avnet FMC http://www.ultrazed.org/product/network-fmc-module Unfortunately not everything is connected now that's why this is only describing system which Xilinx is using. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek
Record note about reducing number of BDs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Switch zcu100 revC to use firmware clock driverMichal Simek
There is no issue with using firmware based driver instead of fixed clock one. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14zynqmp: dts: Cleanup no-1-8-v property from sdhci dt nodesT Karthik Reddy
Removed no-1-8-v property from zynqmp sdhci devicetree nodes to allow UHS-I capable SD cards to work in SD3.0 UHS modes. Boards that does not have level shifter for SD, does not support 1.8v. so no-1-8-v property to sdhci dt nodes should be present in zcu102 Rev-A,B, zcu104 Rev-A,C, zcu100, zcu1275 Rev-B boards. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Add support for zcu208Michal Simek
The board is very similar to zcu216 with zu49dr device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14ARM: zynq: Add missing nand/smcc nodesMichal Simek
Add missing nand/smcc description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14firmware: Remove probe which is causing extra bindAshok Reddy Soma
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver. It is just binding its subnode zynqmp-clk. As a result one extra node is showing up in dm tree. This is not required, it is anyway bound from it's own zynqmp-clk driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Correct the type of eeprom for zcu216 boardsRaviteja Narayanam
Corrected the type of eeprom in device tree for zcu216 boards according to schematic. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2025-01-13 23:25:39 +0000