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2018-01-26dm: ram: bmips: add BCM6318 supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-26dm: cpu: bmips: add BCM6318 supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-26MIPS: add BMIPS Comtrend WAP-5813n boardÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-26MIPS: add support for Broadcom MIPS BCM6368 SoC familyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-26dm: cpu: bmips: add BCM6368 supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-26DW SPI: Get clock value from Device TreeEugeniy Paltsev
Add option to set spi controller clock frequency via device tree using standard clock bindings. Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API and implement dw_spi_get_clk their own way in their clock manager. Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead) Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-26SOCFPGA: clock manager: implement dw_spi_get_clk functionEugeniy Paltsev
Implement dw_spi_get_clk function to override its weak implementation in designware_spi.c driver. We need this change to get rid of cm_get_spi_controller_clk_hz function and clock_manager.h include in designware_spi.c driver. Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-25usb: ehci: mxs: fix swapped argument in ehci_writel()Daniel Schwierzeck
ehci_writel() swaps the arguments for address and value. One call in ehci-mxs ignores that. This fixes the warning: drivers/usb/host/ehci-mxs.c: In function ?ehci_hcd_stop?: drivers/usb/host/ehci-mxs.c:159:19: error: initialization makes integer from pointer without a cast [-Werror=int-conversion] ehci_writel(tmp, &hcor->or_usbcmd); ^ arch/arm/include/asm/io.h:117:34: note: in definition of macro ?writel? #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/usb/host/ehci-mxs.c:159:2: note: in expansion of macro ?ehci_writel? ^~~~~~~~~~~ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-25usb: xhci: Fix bool initialization in xhci_bulk_txGustavo A. R. Silva
Bool initializations should use true and false. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de>
2018-01-25mips: bmips: increment SYS_MALLOC_F_LENÁlvaro Fernández Rojas
This prevents the following ENOMEM: Error binding driver 'bmips_cpu': -12 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-25boston: Pad binary in .mcs to a multiple of 16 bytesPaul Burton
When flashing U-Boot on a Boston board using Xilinx Vivado tools, the final 0x00 byte which ends the .relocs section seems to be skipped & left in flash as 0xff unless the data contained in the .mcs is padded out to a 16 byte boundary. Without our final zero byte relocation will fail with an error about a spurious reloc: Avoid this problem by padding out the data in the .mcs file to a 16 byte boundary using srec_cat's -range-pad functionality. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-01-25ddr: altera: silence PHY calibration unless in debug modeGoldschmidt Simon
This driver has been using printf() including filename since it was added. Convert to using debug() instead. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-01-25arm: socfpga: allow configs without network supportSimon Goldschmidt
Currently, socfpga_common.h does not allow configurations without network support. This is because CONFIG_CMD_PXE is defined in this file and distro mode has DHCP hard-coded as available. Fix this by moving CONFIG_CMD_PXE and CONFIG_MENU to the defconfigs and by making DHCP optional in BOOT_TARGET_DEVICES(func). Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-01-24Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini
2018-01-24pinctrl: rmobile: Import R8A7794 E2 PFC tablesMarek Vasut
Import PFC tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24pinctrl: rmobile: Import R8A7792 V2H PFC tablesMarek Vasut
Import PFC tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24pinctrl: rmobile: Import R8A7791/R8A7793 M2 PFC tablesMarek Vasut
Import PFC tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24pinctrl: rmobile: Import R8A7790 H2 PFC tablesMarek Vasut
Import PFC tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7794 E2 clock tablesMarek Vasut
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7792 V2H clock tablesMarek Vasut
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7791/R8A7793 M2 clock tablesMarek Vasut
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Import R8A7790 H2 clock tablesMarek Vasut
Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Add Gen2 clock coreMarek Vasut
Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Add DIV6P1 clock typeMarek Vasut
Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split out code shared between Gen2 and Gen3Marek Vasut
Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make clock tables Kconfig configurableMarek Vasut
Add Kconfig entries for each SoC clock table, so they can be compiled in or out at build time. This can reduce the size of the binary if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split SMSTPCR and RMSTPCR tablesMarek Vasut
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Pull Gen3 specific bits into separate headerMarek Vasut
Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make PLL configurations per-SoCMarek Vasut
Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Make clk_ids per-driverMarek Vasut
Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24clk: renesas: Split RCar Gen3 driverMarek Vasut
Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24serial: sh: Add support for R7S72100 (RZ/A1)Chris Brandt
Add support for RZ/A1 series SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2018-01-24serial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2Marek Vasut
Use the common RCAR_GEN2 config option instead of enumerating each SoC and having a lengthy ifdef clause. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24serial: sh: Replace fdtdec_get_addr() with devfdt_get_addr()Marek Vasut
Replace fdtdec_get_addr() with devfdt_get_addr() as the later one is the current recommended practice. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24ARM: rmobile: Convert CONFIG_R8A77xx to KconfigMarek Vasut
Convert these configuration options to Kconfig, update board defconfigs and drop them from whitelist. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24ARM: dts: rmobile: Factor out U-Boot extrasMarek Vasut
Pull out u-boot extras into dtsi files to make synchronization of DTS from Linux kernel as easy as a simple copy. All the U-Boot extras are now in *-u-boot.dts* files instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24ARM: dts: rmobile: Update DTS to match Linux 4.14Marek Vasut
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.14, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . This includes both M3 and H3 ULCB and Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24Merge git://git.denx.de/u-boot-mmcTom Rini
2018-01-24mmc: Poll for broken card detection caseJun Nie
Poll for broken card detection case instead of return no card detected. Signed-off-by: Jun Nie <jun.nie@linaro.org>
2018-01-24mmc: fix to assign to correct clock value when clock is enablingJaehoon Chung
When clock is enabling, it's assigned to 0 as mmc->clock. Then it can't initialize any card. Fix to assign to correct clock value as mmc->cfg->f_min or f_max. Fixes: 9546eb92cb6 ("mmc: fix the wrong disabling clock") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Guillaume GARDET <guillaume.gardet@free.fr> Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
2018-01-24configs: odroid-xu3: enable the configs relevant to regulatorJaehoon Chung
Enable the CONFIG_CMD_REGULATOR and CONFIG_DM_REGULATOR_S2MPS11. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-24power: pmic: s2mps11: probe the regulator driverJaehoon Chung
Add the probe function to support the s2mps11 regulator driver. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-24power: regulator: s2mps11: add a regulator driver for s2mps11Jaehoon Chung
exynos5422 has the s2mps11 PMIC. s2mps11 pmic has the 10-BUCK and 38-LDO regulators. Each IP and devices in exynos5422 can be controlled by each regulators. This patch is support for s2mps11 regulator driver. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-24spi: cadence_qspi_apb: Make flash writes 32 bit alignedVignesh R
Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 bit aligned buffers. This is required because as per TI K2G TRM[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer. Otherwise indirect writes is known to fail sometimes. [1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when ↵Vignesh R
possible" This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. Using bounce_buf.c to handle non-DMA alignment problems is bad as bounce_buf.c does cache manipulations which is not required. Therefore revert this patch in favour of local bounce buffer solution in the next patch. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when ↵Goldschmidt Simon
possible" This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates the data cache after reading. This is meant for dma transfers only and breaks the cadence_qspi driver which copies via cpu only: data that is copied by the cpu is in cache only and the cache invalidation at the end throws away this data. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dts: cadence_spi: Update documentation for DT bindingsJason Rush
Update documentation to reflect adopting the Linux DT bindings. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24config: cadence_spi: Remove defines read from DTJason Rush
Cleanup unused #define values that are read from the DT. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24dts: cadence_spi: Sync DT bindings with LinuxJason Rush
Adopt the Linux DT bindings and clean-up duplicate and unused values. Fix indentation of the QSPI node in the keystone k2g device tree. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24spi: cadence_spi: Sync DT bindings with LinuxJason Rush
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
generated by cgit (git 2.34.1) at 2025-01-01 20:37:55 +0000