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2016-10-29ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada
Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada
Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada
Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada
The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3Masahiro Yamada
The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabledMasahiro Yamada
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada
The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada
This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada
- Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: remove unused board attribute macrosMasahiro Yamada
After SoC evaluation, they turned out unnecessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: enable SSC for more PLLs for LD20 SoCMasahiro Yamada
For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: remove unneeded mdelay() in PLL setting functionMasahiro Yamada
This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: adjust fdt_file environment handling to latest LinuxMasahiro Yamada
The environment fdt_file is useful to remember the appropriate DTB file name. Adjust it to the recent renaming in the upstream kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-28Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini
2016-10-28dm: at91: Add driver model support for the spi driverWenyou Yang
Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28board: sama5d2_xplained: Enable an early debug UARTWenyou Yang
Enable an early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-10-28board: sama5d2_xplained: Set 'ethaddr' got from AT24MACWenyou Yang
If 'ethaddr' is not set, we will get the ethernet address from AT24MAC, and set it to 'ethaddr' variable. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Songjun Wu <songjun.wu@microchip.com> Reviewed-by: Andreas Bießmann <biessmann@corscience.de>
2016-10-28board: sama5d2_xplained: Clean up codeWenyou Yang
Since the introduction of pinctrl and clk driver, and the dts file, remove unneeded the pin configurations and the clock enabling code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-10-28board: sama5d2_xplained: Move config options to defconfigsWenyou Yang
Move the config options from the include/configs/sama5d2_xplained.h to configs/sama5d2_xplained_*_defconfig. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-10-28serial: atmel_usart: Support enable an early debug UARTWenyou Yang
Add support to enable an early debug UART for debugging. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28serial: Kconfig: Add ATMEL_USART optionWenyou Yang
Add ATMEL_USART option to support to enable the Atmel usart driver from Kconfig. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28mmc: atmel_sdhci: Remove unnecessary clock callingWenyou Yang
Due to the peripheral and generated clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28usb: ehci-atmel: Remove unnecessary clock callingWenyou Yang
Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28i2c: at91_i2c: Change error return -ENODEV to -EINVALWenyou Yang
Change the error return value -ENODEV from to -EINVAL for more reasonable. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-10-28i2c: at91_i2c: Remove unnecessary clock callingWenyou Yang
Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-10-28gpio: atmel_pio4: Remove unnecessary clock callingWenyou Yang
Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: at91: Improve the clock implementationWenyou Yang
For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency. The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops. So do the generated clock and system clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: clk-uclass: Assign clk->dev before call .of_xlateWenyou Yang
In order to make clk->dev available in ops->of_xlate() to get the clock ID from the 'reg' property of the clock node, assign the clk->dev before calling ops->of_xlate(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-10-28ARM: at91/dt: sama5d2: Fix the warning from dtcWenyou Yang
Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: at91: Fix at91-pmc and at91-sckc's class IDWenyou Yang
The at91-pmc and at91-sckc aren't the clock providers, change their class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't need to bind the child nodes explicitly, the .post_bind callback of simple_bus uclass will do it for them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28AT91: Correct misspelling of "redundent" in partition namesRobert P. J. Day
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28arm, at91: add icache supportHeiko Schocher
add at least icache support for at91 based boards. This speeds up NOR flash access on an at91sam9g15 based board from 15.2 seconds reading 8 MiB from a SPI NOR flash to 5.7 seconds. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28ARM: at91: clock: correct PRES offset for at91sam9x5Heiko Schocher
on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28arm: at91: mpddrc: add missing MPDDRC_MD definesHeiko Schocher
add missing MPDDRC_MD defines Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
2016-10-28Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini
2016-10-28pci: Move CONFIG_PCI_PNP to KconfigBin Meng
Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-10-28mmc: sdhci: assign to clk_mul when host version is upper than SD3.0Jaehoon Chung
To prevent the wrong value check the SD version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28mmc: add the device name in debugging message for supplying vmmcJaehoon Chung
If vmmc didn't supply, we didn't know which card didn't supply vmmc. And changed from "put" to "debug". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-10-28dm: mmc: socfpga: fix MMC_OPS supportSylvain Lesne
Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28mmc: refactor two core functionsMasahiro Yamada
Drop unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-28mmc: sdhci: fix the "misaligned operation at range" for cacheJaehoon Chung
This pathc is fixed the below thing. If misaligned the cache range, Just flush to CACHLINE_SIZE. "CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]" Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28mmc: introduce mmc_power_initPeng Fan
In device tree, there is vmmc-supply property for SD/MMC. Introduce mmc_power_init function to handle vmmc-supply. mmc_power_init will first invoke board_mmc_power_init to avoid break boards which already implement board_mmc_power_init. If DM_MMC and DM_REGULATOR is defined, the regulator will be enabled to power up the device. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-27drivers/pci/Kconfig: Add PCITom Rini
Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-26imx6: icorem6: Add default mtd nand partition tableJagan Teki
icorem6qdl> mtdparts device nand0 <nand>, # parts = 6 0: spl 0x00200000 0x00000000 0 1: uboot 0x00200000 0x00200000 0 2: env 0x00100000 0x00400000 0 3: kernel 0x00400000 0x00500000 0 4: dtb 0x00100000 0x00900000 0 5: rootfs 0x1f600000 0x00a00000 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6: icorem6: Enable MTD device supportJagan Teki
Enable MTD device, partition and command support. Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6: icorem6: Add NAND supportJagan Teki
Add NAND support for Engicam i.CoreM6 qdl board. Boot Log: -------- U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) Trying to boot from NAND NAND : 512 MiB U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 55C Reset cause: WDOG Model: Engicam i.CoreM6 DualLite/Solo Starter Kit DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> Cc: Scott Wood <oss@buserror.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26mtd: nand: Kconfig: Add NAND_MXS entryJagan Teki
Added kconfig for NAND_MXS driver. Cc: Scott Wood <oss@buserror.net> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/DualJagan Teki
i.CoreM6 Quad/Dual modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DQ, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: imx6q: Add pinctrl definesJagan Teki
Add imx6q pinctrl defines support from Linux. Here is the last commit: "ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ" (sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2024-12-29 13:37:38 +0000