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2018-05-20ARM: rmobile: Drop old R8A7792 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7791 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Drop old R8A7790 PFC tablesMarek Vasut
All the boards use new modern PFC framework, the old PFC tables are no longer used, so remove them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Update V2H BlancheMarek Vasut
The V2H Blanche port was broken since some time. This patch updates the V2H Blanche port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Enable DM capable RCar I2C driver on SilkMarek Vasut
Enable the DM capable driver instead of the legacy one. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20ARM: rmobile: Enable DM capable RCar I2C driver on LagerMarek Vasut
Enable the DM capable driver instead of the legacy one. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20i2c: rcar_i2c: Add DM and DT capable I2C driverMarek Vasut
Add derivative of the rcar_i2c driver which is capable of probing itself from DM and uses DT. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20i2c: rcar_i2c: Remove the driverMarek Vasut
Remove the rcar_i2c driver, since it's no longer used by any board and will be superseded by a DM and DT capable variant. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-18Fixup various SPDX tags from the latest mergeTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-18drivers: usb: dwc3: remove devm_zalloc from linux_compactMugunthan V N
devm_zalloc() is already defined in dm/device.h header, so devm_zalloc can be removed from linux_compact.h beader file. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-18usb: xhci: zynqmp: Remove support for !DM_USBMichal Simek
Switch to DM_USB was done and there is no need to keep !DM_USB code in tree. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18arm64: zynqmp: Use DWC3 generic driver and DM_USBMichal Simek
Remove harcoded XHCI lists and detect mode, speed based on DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Serial-changes: 2 - Remove also XHCI macros from hardware.h - Remove additional new line in zcu106
2018-05-18usb: xhci: zynqmp: Add support for DM_USBMichal Simek
The patch is adding support for DM_USB for xhci driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-18usb: dwc3: Add generic DWC3 glue logic driverMichal Simek
By enabling BLK by default this is the next driver which needs to get support for DM_USB. Adding generic DWC3 glue logic which only parse nodes and read device mode. Based on it probe proper host/peripheral DWC3 drivers for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-18usb: common: add support to get maximum speed from dtMugunthan V N
Add support to get maximum speed from dt so that usb drivers makes use of it for DT parsing. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> (rebase and fix errors) Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18usb: dwc3: Add dwc3_init/remove with DM_USBMugunthan V N
The patch is preparing dwc3 core for enabling DM_USB with peripheral driver with using driver model support. The driver will be bound by the DWC3 wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> (Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-18phy: add support for STM32 usb phy controllerPatrice Chotard
This patch adds phy tranceiver driver for STM32 USB PHY Controller (usbphyc) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-18gadget: f_thor: update to support more than 4GB file as thor 5.0Seung-Woo Kim
During file download, it only uses 32bit variable for file size and it limits maximum file size less than 4GB. Update to support more than 4GB file with using two 32bit variables for file size as thor protocol 5.0. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2018-05-18gadget: f_thor: fix filename overflowSeung-Woo Kim
The thor sender can send filename without null character and it is used without consideration of overflow. Actually, character array for filename is assigned with DEFINE_CACHE_ALIGN_BUFFER() and it is bigger than size of memcpy, so there was no real overflow. Fix filename overflow for code level integrity. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2018-05-18Merge git://git.denx.de/u-boot-imxTom Rini
2018-05-18arm: dts: socfpga: stratix10: update dtsi and dtsLey Foon Tan
Update dtsi and dts files for resets, phy node and other properties. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switchLey Foon Tan
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add pinmux support for Stratix10 SoCLey Foon Tan
Add pinmux driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoCLey Foon Tan
Add Reset Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoCLey Foon Tan
Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18arm: socfpga: stratix10: Add watchdog and firewall base addressesLey Foon Tan
Add the base address for watchdog and firewall. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Fix Documentation errors in scu_registersBen Kalo
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers Access Control register offset is 0x50. Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2018-05-18ARM: socfpga: Adding SoCFPGA info for both SPL and U-BootTien Fong Chee
SoC FPGA info is required in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Adding clock frequency info for U-BootTien Fong Chee
Clock frequency info is required in U-Boot because info would be erased when transition from SPL to U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Enable SPL memory allocationTien Fong Chee
Enable memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee
Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Add DRAM bank size initialization functionTien Fong Chee
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single SOCFPGA board. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Repair A10 EMAC reset handlingMarek Vasut
The EMAC reset and PHY mode configuration was never working on the Arria10 SoC, fix this. This patch pulls out the common code into misc.c and passes the SoC-specific function call in as a function pointer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoffMarek Vasut
Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest Quartus to get the new set of clock bindings in. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Synchronize Arria10 DTsMarek Vasut
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit ef8216d28a5920022cddcb694d2d75bd1f0035ca Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sort the DT MakefileMarek Vasut
Sort the Makefile entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Sync A10 clock manager binding parserMarek Vasut
The A10 clock manager parsed DT bindings generated by Quartus the bsp-editor to configure the A10 clocks. Sadly, those DT bindings changed at some point. The clock manager patch used the old ones, this patch replaces the bindings parser with one for the new set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Convert to DM serialMarek Vasut
Pull the serial port configuration from DT and use DM serial instead of having the serial configuration in two places, DT and board config. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Clean up Kconfig entriesMarek Vasut
Shuffle the default Kconfig entries around so it is not such a mess. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGETMarek Vasut
This was never used, is not used anywhere and is just in the way by adding annoying ifdeffery. Get rid of it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Put stack at the end of SRAMMarek Vasut
The global data are in the .data section, so there's no point in reserving any space for it above stack. Put stack at the end of SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18fdt: Add another Altera Arria10 clock init compatibleMarek Vasut
The DT bindings for the Arria10 clock init have changed, add another compatible to make them work with U-Boot until a proper clock driver gets written. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18arm: imx53: Add support for imx53 boards from K+PLukasz Majewski
This commit adds support for DDC and HSC boards from K+P in u-boot. Console output: U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: WDOG Model: K+P iMX53 DRAM: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Module EEPROM: ID: TQMa53-CB.0401 SN: 63152762 MAC: 00:0b:64:03:14:2a BBoard:40x0 Rev:10 Net: eth0: ethernet@63fec000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-05-18sandbox: tests: Add tests for mc34708 PMIC deviceLukasz Majewski
Following tests has been added for mc34708 device: - get_test for mc34708 PMIC - Check if proper number of registers is read - Check if default (emulated via i2c device) value is properly read - Check if value write/read operation is correct - Perform tests to check if pmic_clrsetbits() is working correctly Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18sandbox: tests: Exclude common test code (pmic_get) in test/dm/pmic.cLukasz Majewski
The common code can be excluded to be reused by tests for other PMIC. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18sandbox: Enable MC34708 PMIC supportLukasz Majewski
This MC34708 PMIC is somewhat special - it used single transfers (R/W) with 3 bytes size - up till now U-Boot's PMICs only used 1 byte. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18sandbox: Enable support for MC34708 PMIC in DTSLukasz Majewski
This commit also provides the default values of the emulated MC34708 PMIC internal registers content. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18sandbox: Rewrite i2c_pmic_emul.c to support PMIC with 3 bytes transmissionLukasz Majewski
This change enables support for MC34708 PMIC in sandbox. Now we can emulate the I2C transfers larger than 1 byte. Notable changes for this driver: - From now on the register number is not equal to index in the buffer, which emulates the PMIC registers - The PMIC register's pool is now dynamically allocated up till 64 regs * 3 bytes each = 192 B Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-25 02:02:52 +0000