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Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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since commits:
davinci: emac: add support for more than 1 PHYs
062fe7d332c28ede25626f448681e43d76bb312e
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
fb1d6332b5430b90a8fa8ebab709f33a60e9f816
I get following warning on the enbw_cmc board:
Err: serial
Net: 5 ETH PHY detected
miiphy_register: non unique device name 'KSZ8873 @ 0x01'
DaVinci-EMAC
Hit any key to stop autoboot: 0
Also I see some debug printfs:
=> run load
+ emac_close
+ emac_ch_teardown
- emac_ch_teardown
+ emac_ch_teardown
- emac_ch_teardown
- emac_close
+ emac_open
- emac_open
Using DaVinci-EMAC device
reason is 062fe7d332c28ede25626f448681e43d76bb312e new define MAX_PHY.
This is set to 3! I get on this board 5 active phys, so
this leads in wrong memory writes ...
so I changed:
- define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT to set
the MAX_PHY value, add a description in README
for the new CONFIG_SYS option.
- print an error message if more then MAX_PHYs are
detected.
- fill the active_phy_addr array in a for loop with
0xff
- changed printf() in debug_emac()
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Tom Rini <tom.rini@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds the build support for the
omap5_evm board.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.
Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Add the emif configurations required for omap5 soc.Add the
correct ddr part configurations required for omap5 evm board.
EDB8164B3PH from ELPIDA is the part used on the board.
Also changes are done to retain some part of the code
common for OMAP4/5 and keep only the remaining in the Soc
specific directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Adding the correct configurations required for
dplls, clocks, for omap5 Soc.
Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Fixing them here so that when the files are reused in
subsequent patches for omap5, avoids new checkpatch
warnings.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Much of omap4 soc support code can be reused for omap5.
Move them to the omap-common directory to facilitate
this.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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onenand_base.c: In function ‘onenand_do_lock_cmd’:
onenand_base.c:1946:6: warning: variable ‘wp_status_mask’ set but not used
[-Wunused-but-set-variable]
onenand_base.c: In function ‘onenand_check_maf’:
onenand_base.c:2229:8: warning: variable ‘name’ set but not used
[-Wunused-but-set-variable]
onenand_base.c: In function ‘flexonenand_get_boundary’:
onenand_base.c:2258:6: warning: variable ‘ret’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
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The problem was that the code, when the function was compiled with -Os, was
misgenerated. As in the function description, this is likely another
manifestation of the bug in GCC.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
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This introduces small OneNAND loader, fitting into 1kB of space (smallest
possible OneNAND RAM size). Some devices equipped with such crappy chips will
use this.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Scott Wood <scottwood@freescale.com>
V2: Introduce spl_onenand_load_image() to load data from OneNAND in SPL
V3: Cleanup, align with nand_spl. Skip whole blocks.
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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* Cleanup register definitions by introducing new regs-uart.h, compliant with
rest of U-Boot.
* Remove old register definitions from pxa-regs.h
* Convert serial_pxa to new regs-uart.h
* Cleanup serial_pxa
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Robert Schwebel <robert@schwebel.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
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m28evk has one bank of RAM.
Fix the comment.
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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Fix checkpatch warnings in generic.c.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Use proper IO accessor for GPR register.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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GPR register definition is already available at imx-regs.h, so remove the duplication.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Use generic function for configuring GPR register.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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This enables the second port, aka. the port with the USB connector on the
M28EVK.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
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This driver supports both EHCI ports on the i.MX28 CPU.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
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This code allows the DDR DRAM size to be detected at runtime. The RAM size is
stored into two scratch registers, from which it is then fetched in U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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This patch introduces proper ARM vector handling for i.MX28 CPU. This issue
wasn't addressed because the interrupts weren't enabled on any ARMv5 core,
therefore the issue wasn't noticed earlier.
In previous implementation, the vectoring code used by i.MX28 CPU when an
exception happened was that of the SPL. With this change, the branch target when
an exception happens can be reconfigured by U-Boot.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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This patch adds SPL code for the M28 board.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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This contains support for the following components:
- DUART
- MMC
- Both FEC interfaces
- NAND
- I2C (RTC, EEPROM)
- SPI (FLASH)
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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This tool can now generate proper image for "BootStream" files.
NOTE: This tool now works only for NAND.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Heiko Schocher<hs@denx.de>
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Taken from Linux kernel with minor modifications:
commit bf985969e27b507f734435a99df8bf745a3dbb2b
Author: Shawn Guo <shawn.guo@freescale.com>
Date: Mon Dec 20 22:57:43 2010 +0800
ARM: mxs: Add iomux support
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Andy Fleming <afleming@gmail.com>
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This patch supports:
- Timers
- Debug UART
- Clock
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
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Fix:
zmx25.c: In function 'board_late_init':
zmx25.c:131:25: warning: variable 'padctl' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefano Babic <sbabic@denx.de>
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add new configuration file da850_am18xxevm.h for AM18xx boards
which are based on da850 SOC. AM18xx has WINBOND spi flash which
is indicated in the config file. And make appropriate changes in
board.cfg for building.
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This is needed to support the latest kernel versions.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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The devkit8000 ships with either a 128MB or 256MB NAND chip. In
order for SPL to work with 256MB NAND CONFIG_SYS_NAND_5_ADDR_CYCLE
needs to be set. After talking with Scott Wood this should be
safe to set even for smaller NAND chips.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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This enables Vpp and disables the flash protection on the
Integrator when starting U-Boot. The integrator/AP has double
protection mechanisms: this one and the EBI protection bit
(patch earlier), the Integrator/CP has only one line of
protection in these registers.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Break out the AP system controller and CP "CP controller"
registers into a header file, it gives better overview than
hardcoding its values and other disturbing practices.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This reconfigures the EBI (External Bus Interface) on the
integrator so that chip select 1, handling the flash memory, is
set to writeable. Without this it is not possible for U-Boot to
access flash memory and it crashes on startup since CFI won't
work properly.
Since this is the first time we use the EBI, we create a header
file for its registers.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Casting around to *(volatile ulong *) doesn't look good, so include
the <asm/io.h> macros and use good old readl() instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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