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2015-12-10sunxi: dts: sun8i: Add Allwinner A83T dtsivishnupatekar
Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. This is not yet included in kernel. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add support for Allwinner A83T DRAMvishnupatekar
Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: clk: add basic clocks for A83Tvishnupatekar
Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: power: enabled support for axp818vishnupatekar
Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: power: axp818: add support for axp818 drivervishnupatekar
AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board. It's registers are different and calculating reg config is different than that of earlier axp power ICs. DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment. all other voltages can be added subsequently. AXP datasheet is uploaded to wiki: http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar
On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add Machine Support for A83T SOCvishnupatekar
Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCsHans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-12-09x86: Remove HAVE_ACPI_RESUMEBin Meng
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Clean up ivybridge/chrome Kconfig optionsBin Meng
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGEBin Meng
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09common: Remove timer_init() call for x86Bin Meng
With driver model timer support, there should not be an explict call to timer_init(). Remove this call for x86. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Move i8254_init() to x86_cpu_init_f()Bin Meng
Right now i8254_init() is called from timer_init() in the tsc timer driver. But actually i8254 and tsc are completely different things. Since tsc timer has been converted to driver model, we should find a new place that is appropriate for U-Boot to call i8254_init(), which is now x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Fix PCI UART compatible string for crownbay and galileoBin Meng
With recent ns16550 driver changes, we only changed the legacy UART (at I/O port 0x3f8) compatible string, but forgot to change the PCI UART compatible string. Now fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONEBin Meng
Currently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the return value of dev_get_addr(), it creates potential size mismatch as dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can be either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change OF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2015-12-08axs10x: add support of generic EHCI USB 2.0 controllerAlexey Brodkin
This commit adds support of USB 2.0 storage media on AXS10x boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
2015-12-07Prepare v2016.01-rc2Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-07mkimage: Fix warning from fix for generating multi and script images againMarek Vasut
Seems 6ae6e160 broke creating images in certain cases, there are two problems with that patch. First is that the expression "!x == 4 || !x == 6" is ambiguous. The intention here was "!(x == 4) || !(x == 6)" based on reading further in the file, where this was borrowed from. This however is interpreted by gcc as "(!x) == 4 || (!x) == 6" and always false. gcc-5.x will warn about this case. The second problem is that we do not want to test for the case of "(NOT x is 4) OR (NOT x is 6)" but instead "(x is not equal to 4) AND (x is not equal to 6)". This is because in those two cases we already execute the code question in another part of the file. Rewrite the expression and add parenthesis for clarity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Philippe De Swert <philippedeswert@gmail.com> Cc: Simon Glass <sjg@chromium.org> [trini: Re-word Marek's explanation]
2015-12-07CONFIG_NEEDS_MANUAL_RELOC: Fix warnings when not setTom Rini
Now that we may compile (but not link) code calling fixup_cmdtable when this is not set, we need to always have the declaration available. We should also make sure that anyone calling the function includes <command.h> as that's where the function declaration is. Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-07Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-12-07dm: core: Enable SPL_SIMPLE_BUS by defaultMichal Simek
This option is needed for all SoCs which have nodes on bus. Without enabling this drivers are not found and probed. Issue was found on Zynq MMC probe. Enable this option by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07dm: cmd: Relocate subcommands when MANUAL_RELOCMichal Simek
Subcommands contain pointers to functions which are not updated when MANUAL_RELOC is enabled. This patch fix it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07i2c: cmd: Relocate subcommands when MANUAL_RELOCMichal Simek
Subcommands contain pointers to functions which are not updated when MANUAL_RELOC is enabled. This patch fix it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07serial: zynq: Remove duplicated headerMichal Simek
debug_uart.h is included twice. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07serial: zynq: Fix incorrect reference to s5p driverMichal Simek
Remove this c&p error from s5p driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07zynq: sdhci: Move driver to DMMichal Simek
Move driver to DM Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07zynq: sdhci: Remove zynq_sdhci_of_init()Michal Simek
Prepare for using DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07zynq: sdhci: Calculate minimum frequency based on max frequencySiva Durga Prasad Paladugu
Calculate the minimum sd clock based on max clock. This will be done by add_sdhci() if we pass minimum clock as zero. It also does based on SD host contoller version. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07ARM: zynq: Remove unused SERIAL macros for serial_zynqMichal Simek
Remove unused macros when driver was moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07ARM: zynq: Extend malloc sizeMichal Simek
SPL DM MMC FAT requires more malloc space(3k fat buffers + dm) that it is available now. Extend SPL malloc space. Current OCM layout: 0xffff0000 - 0xfff2000 - Full malloc space 0xffff2000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07ARM: zynq: Fix location of stack and malloc areasMichal Simek
The patch "board_init: Change the logic to setup malloc_base" (sha1: 9ac4fc82071ce346e3885118242ff45d22f69b82) breaks SPL for Zynq because it puts early alloc area on the stack which caused that stack was decreased by CONFIG_SYS_MALLOC_F_LEN (0x400) and there was not enough space for regular stack. This patch changes memory layout to better utilize the last 64k OCM block. 0xffff0000 - 0xfff1000 - Full malloc space 0xffff1000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Moritz Fischer <moritz.fischer@ettus.com>
2015-12-07ARM: zynq: Enable debug console for zc702Michal Simek
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07ARM64: zynqmp: Enable FIT config option via KconfigMichal Simek
Remove configuration options from board file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Enable CTRL+C in wait_for_bitMichal Simek
Enable to break waiting loop at any time. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-07net: gem: Move gem to KconfigMichal Simek
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07net: gem: Read information about interface from DTMichal Simek
Do not set interface via configs. Read information from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07net: gem: Move driver to DMMichal Simek
- Enable DM_ETH by default for Zynq and ZynqMP - Remove board_eth_init code - Change miiphy_read function to return value instead of error code based on DM requirement - Do not enable EMIO DT support by default Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-07net: gem: Fix miiphy_read nameMichal Simek
Sync it with write function. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07net: gem: Remove zynq_gem_of_init()Michal Simek
This function was used for OF init before DM. Remove this function as the part of move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07net: gem: Enable MDIO bus earlierMichal Simek
Enable access to MDIO before zynq_gem_init is called. It enables read information about phy earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Check if priv->phydev is validMichal Simek
Check return value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07net: gem: Extract phy init codeMichal Simek
Move phy init code out of zynq_gem_init. DM drivers are normally calling this code from probe function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Remove phydev variableMichal Simek
Resort code to use priv->phydev variable directly. It will simplify move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Change mii function not to use eth_device structureMichal Simek
Next step to move driver to driver model. Do not use eth_device structure. Use private structure instead. Add iobase to private structure to store gem iobase. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Change mdio_wait prototype to pass regsMichal Simek
Pass regs instead of dev because this will be chagned by driver model. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07net: gem: Do not continue if phy is not foundMichal Simek
Add return value for phy detection algorithm to stop init function when phy is not found. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07ARM: zynq: Remove CONFIG_APIMichal Simek
CONFIG_API is causing compilation error when DM_ETH is enabled because eth_get_dev() is not available. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07ARM: zynq: Remove PHYLIB from config to defconfigMichal Simek
Move PHYLIB from board config to defconfig Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-06Merge git://git.denx.de/u-boot-niosTom Rini
generated by cgit (git 2.34.1) at 2024-12-29 01:33:10 +0000