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2015-12-13driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun
The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update MR5 RTT parkYork Sun
For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13driver/ddr/fsl: Update DDR4 RTT valuesYork Sun
DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-11Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2015-12-11spi: xilinx: Add new compatible stringsMichal Simek
Add xlnx,xps-spi-2.00.a/b which is compatible string listed in the Linux kernel. Remove origin one which has no real background. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-11mailmap: Update Jagan Teki's name and email addressJagan Teki
Used quite different name's and e-mail address, all of them mapped to standard name and e-mail address. Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Rename sf_ops.c to spi-flash.cJagan Teki
Since all spi-flash core operations are moved into sf_ops.c then it's better to renamed as spi-flash.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Use static for file-scope functionsJagan Teki
Used static for file-scope functions in sf_probe.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: sf_probe: Remove spi_slave pointer argumentJagan Teki
Since spi_slave is a spi pointer in spi_flash{} then assign spi_slave{} pointer to flash->spi and remove spi_slave pointer argument to - spi_flash_probe_slave - spi_flash_scan Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: ops: Fix missing break on spansion read_barJagan Teki
For assigning read_bar commands in spansion case, break is missing this patch add that break. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Remove unneeded SST_BP and SST_WPJagan Teki
SST parts added on sf_params.c supports both SST_WR which consits of both BP and WP and there is a spi controller ich which supports only BP so the relevent _write hook set based on "slave->op_mode_tx" hence there is no respective change required from flash side hance removed these. Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Remove unneeded header includesJagan Teki
Removed unneeded header includes in sf_ops and sf_probe Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Flash power up read-only based on idcode0Jagan Teki
Using macro's for flash power up read-only access code leads wrong behaviour hence use idcode0 for runtime detection, hence the flash which require this functionality gets detected at runtime. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Use simple name for register access functionsJagan Teki
Most of the register access function are static, so used simple name to represent each. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Fix MakefileJagan Teki
This patch removes unneeded ifdef and fixed accordingly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Use static for file-scope functionsJagan Teki
Use static for file-scope functions and removed them from header files. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: probe: Code cleanupJagan Teki
- Move bar read code below the bar write hance both at once place, hence it easy for #ifdef macro only once and readable. - Move read_cmd_array at top Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Move read_id code to sf_opsJagan Teki
read_id code is related to spi_flash stuff hence moved to sf_ops. Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: Move spi_flash_scan code to sf_opsJagan Teki
Intension is that sf_ops should deals all spi_flash related stuff and sf_probe (which should renamed future) should be an interface layer for spi_flash versus spi drivers. sf_ops => spi_flash interface sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11sf: spi_flash_validate_params => spi_flash_scanJagan Teki
Rename spi_flash_validate_params to spi_flash_scan as this code not only deals with params setup but also configure all spi_flash attributes. And also moved all flash related code into spi_flash_scan for future functionality addition. Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11spi: Kconfig: Fix correct target name for ZynqMPMichal Simek
ZynqMP is using different symbol. Use correct one. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11spi: zynq_spi: Add cadence compatible stringMichal Simek
Extend compatible list table for cdns,spi-r1p6 compatible string. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11imx: mx7dsabresd: Add QSPI supportPeng Fan
Support qspi flashes for mx7dsabresd 1. introduce pin mux settings 2. enable qspi clock 3. introduce related macro definitions Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9: " QSPI signals are muxed with EPDC_D[7:0] When using QSPI: de-populate R388-R391, R396-R399 populate R392-R395, R299, R300 " After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info: " => sf probe SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Read: OK => sf erase 0 0x4000000 SF: 67108864 bytes @ 0x0 Erased: OK => sf write 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Written: OK " Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-12-11spi: ti_qspi: Fix SPI_3WIRE checking using modeJagan Teki
SPI_3WIRE is spi mode not spi flags, so this patch fixed the spi-3wire checking throgh mode instead of flags. Cc: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11spi: Get spi-3wire from dtsJagan Teki
spi-3wire is used when SI/SO signals shared so get the same from dts node and assign to mode on slave plat->mode. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11Merge git://git.denx.de/u-boot-dmTom Rini
2015-12-11Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini
2015-12-11Kconfig: i2c: Fix indentationMichal Simek
Use tabs instead of space for indentation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-11Kconfig: i2c: Fix typo Suport -> SupportMichal Simek
Fix typo in command description. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-10dm: serial: Minor coding style cleanup of some commentsStefan Roese
Fix incorrect comment alignments. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-10dm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATEStefan Roese
Add a remark about SPL to this Kconfig option. Otherwise its identitcal to the non-SPL version, which is confusing. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-12-10buildman: README: add links for toolchains not available on kernel.orgThomas Chou
Add links for toolchains not available on kernel.org. The sh4 toolchains from kernel.org dose not work for some boards, so use the sh from Sourcery. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-10sunxi: Fix H3 DRAM DQ read delay configurationJens Kuske
The read delays were set incorrectly, leading to reliability issues at higher DRAM clock speeds. This commit adjusts this to match the vendor boot0 behaviour. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sun4i: clock: Cleanup some whitespace errorsOlliver Schinagl
Add some spaces around operators. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: twi: Enable clocks on sun7iOlliver Schinagl
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC but forgot to extend the range check in clock_twi_onoff, resulting in the clock not getting enabled. The range-check is not needed at all, since clock_twi_onoff only gets called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE is set and Kconfig already only allows these on sun6i / sun7i. This commit removes the range-check all together fixing i2c bus 4 and 5 not working on sun7i. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> [hdegoede@redhat.com] Remove range check instead of extending it Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: select SYS_NS16550 from KconfigHans de Goede
Select SYS_NS16550 from Kconfig instead of setting it in all our defconfig files. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add suport for A83T HomletV2 Board by Allwinnervishnupatekar
Add dts and defconfig for h8homletv2 board. H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner. It has UART, ethernet, USB, HDMI, etc ports on it. A83T patches are tested on this board. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: dts: sun8i: Add Allwinner A83T dtsivishnupatekar
Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. This is not yet included in kernel. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add support for Allwinner A83T DRAMvishnupatekar
Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: clk: add basic clocks for A83Tvishnupatekar
Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: power: enabled support for axp818vishnupatekar
Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: power: axp818: add support for axp818 drivervishnupatekar
AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board. It's registers are different and calculating reg config is different than that of earlier axp power ICs. DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment. all other voltages can be added subsequently. AXP datasheet is uploaded to wiki: http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdf Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar
On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Add Machine Support for A83T SOCvishnupatekar
Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-12-10sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCsHans de Goede
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-12-09x86: Remove HAVE_ACPI_RESUMEBin Meng
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Clean up ivybridge/chrome Kconfig optionsBin Meng
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGEBin Meng
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-12-27 21:27:17 +0000