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2020-03-31Merge tag 'arc-last-minute-fixes-for-2020.04' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc This last minute pull-request is intended to fix some drivers when used on ARC boards. The problem was introduced by https://gitlab.denx.de/u-boot/u-boot/-/commit/07906b3dad157bd58411664bcc6a2a7976d5e0a9 What happened while doing one pretty simple improvement to make U-Boot port more flexible and portable (by switching accessors from assembly-written to plain C version) we implicitly added 2 problems: 1. Downgraded accessors from being volatile which signalled to the compiler that it's now possible to do all kinds of optimizations which may easily include merge of subsequent byte reads/writes into word operations. Which is OK for accessing mormal memory but breaks operation of peripherals if we access its memory-mapped regs in such a "creative" manner. 2. As a part of assembly-written implementation we had compiler barriers in form of the following construction 'asm volatile("" : : : "memory")', and we dropped it in C implemntation. This in its turn enabled compiler to mess with instruction ordering. Guess what it gives us in the end :) So with all that we had in some corner-cases veeery funny instruction flows generated. And in particular it broke DW SPI functionality when we were writing large amount of data. Funny enough our tests which were writing small amount of data still worked and only by the chance we caught that breakage and unrolled that quite interesting loop of unexpected problems. The road to hell is paved with good intentions. Amen :)
2020-03-31ARC: IO: add MB for __raw_* memory accessorsEugeniy Paltsev
We add memory barriers for __raw_readX / __raw_writeX accessors same way as it is done for readX and writeX accessors as lots of U-boot driver uses __raw_readX / __raw_writeX instead of proper accessor with barrier. It will save us from lot's of debugging in the future and it is OK as U-Boot is not that performance oriented as real run-time software like OS or user bare-metal app so we may afford being not super fast as we only being executed once. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31ARC: IO: add compiler barriers to IO accessorsEugeniy Paltsev
We must use compiler barriers in C-version read/write IO accessors before and after operation (read or write) so it won't be reordered by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31ARC: IO: add volatile to accessorsEugeniy Paltsev
We must use 'volatile' in C-version read/write IO accessors implementation to avoid merging several reads (writes) into one read (write), or optimizing them out by compiler. Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31Merge branch '2020-03-31-master-imports'Tom Rini
- mpc8xxx GPIO, SPI bugfixes - Add VxWorks to FIT images - macb ethernet driver bugfix
2020-03-31net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.Michal Simek
When MACB_ZYNQ is enabled there is compilation warnings drivers/net/macb.c: In function ‘_macb_init’: drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function); did you mean ‘MACB_MCF’? writel((value), (port)->regs + MACB_##reg) ^~~~~ It has been caused by changing macros name by commit below. Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-31mpc8xxx_spi: implement real ->set_speedRasmus Villemoes
Not all boards have the same CSB frequency, nor do every SPI slave necessarily support running at 16.7 MHz. So implement ->set_speed; that also allows using a smaller PM (i.e., 0) for slaves that do support a higher speed. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: always use 8-bit characters, don't read or write garbageRasmus Villemoes
There are a few problems with the current driver. First, it unconditionally reads from dout/writes to din whether or not those pointers are NULL. So for example a simple "sf probe" ends up writing four bytes at address 0: => md.l 0x0 8 00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ => sf probe 0 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48 SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB => md.l 0x0 8 00000000: ff000000 45454545 05050505 05050505 ....EEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ (here I've change the first debug statement to a printf, and made it print the din/dout pointers rather than the uints they point at). Second, as we can also see above, it always writes a full 32 bits, even if a smaller amount was requested. So for example => mw.l $loadaddr 0xaabbccdd 8 => md.l $loadaddr 8 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ 02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x400 6 device 0 offset 0x400, size 0x6 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48 SF: 6 bytes @ 0x400 Read: OK => sf read 0x02000010 0x400 8 device 0 offset 0x400, size 0x8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64 SF: 8 bytes @ 0x400 Read: OK => md.l $loadaddr 8 02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE.......... 02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........ Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7 bytes), the last three bytes and up being the wrong ones, since the driver does a full 32 bit read and then shifts the wrong byte out: => mw.l $loadaddr 0xaabbccdd 4 => md.l $loadaddr 4 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x444 10 device 0 offset 0x444, size 0x10 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128 SF: 16 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0 => mw.l $loadaddr 0xaabbccdd 4 => sf read $loadaddr 0x444 0xb device 0 offset 0x444, size 0xb mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88 SF: 11 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219...... Fix all of that by always using a character size of 8, and reject transfers that are not a whole number of bytes. While it ends being more work for the CPU, we're mostly bounded by the speed of the SPI bus, and we avoid writing to the mode register in every loop. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: put max_cs to useRasmus Villemoes
Currently, max_cs is write-only; it's just set in mpc8xxx_spi_ofdata_to_platdata and not otherwise used. My mpc8309 was always resetting during an "sf probe 0". It turns out dm_gpio_set_dir_flags() was being called with garbage, since nothing had initialized priv->gpios[0] - our device tree used "cs-gpios" rather than "gpios", so gpio_request_list_by_name() had returned 0. That would have been a lot easier to figure out if the chip select index was sanity checked, so rename max_cs to cs_count, and reject a xfer with a too large cs index. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gazerbeam: add clocks property to SPI nodeRasmus Villemoes
Prepare for supporting setting different speeds in mpc8xxx_spi.c. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signalKlaus H. Sorensen
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi chip select, SPISEL_BOOT, that is used by the boot code to boot from flash. This chip select will typically be used to select a SPI boot flash. The SPISEL_BOOT signal is controlled by a single bit in the SPI_CS register. Implement a gpio driver for the spi chip select register. This allows a spi driver capable of using gpios as chip select, to bind a chip select to SPISEL_BOOT. It may be a little odd to do this as a GPIO driver, since the signal is neither GP or I, but it is quite convenient to present it to the spi driver that way. The alternative it to teach mpc8xxx_spi to handle the SPISEL_BOOT signal itself (that is how it's done in the linux kernel, see commit 69b921acae8a) Signed-off-by: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio: mpc8xxx: don't do RMW on gpdat register when setting valueRasmus Villemoes
The driver correctly handles reading back the value of an output gpio by reading from the shadow register for output, and from gpdat for inputs. Unfortunately, when setting the value of some gpio, we do a RMW cycle on the gpdat register without taking the shadow register into account, thus accidentally setting other output gpios (at least those whose value cannot be read back) to 0 at the same time. When changing a gpio from input to output, we still need to make sure it initially has the requested value. So, the procedure is - update the shadow register - compute the new gpdir register - write the bitwise and of the shadow and new gpdir register to gpdat - write the new gpdir register Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31gpio: mpc8xxx: don't modify gpdat when setting gpio as inputRasmus Villemoes
Since some chips don't support reading back the value of output gpios from the gpdat register, we should not do a RMW cycle (i.e., the clrbits_be32) on the gpdat register when setting a gpio as input, as that might accidentally change the value of some other (still configured as output) gpio. The extra indirection through mpc8xxx_gpio_set_in() does not help readability, so just fold the gpdir update into mpc8xxx_gpio_direction_input(). Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31cmd: mmc: fix typo 'a EMMC'Heinrich Schuchardt
%s/a EMMC/an eMMC/g Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-03-31image-fit: Allow loading FIT image for VxWorksLihua Zhao
This adds the check against IH_OS_VXWORKS during FIT image load, to allow loading FIT image for VxWorks. Signed-off-by: Lihua Zhao <lihua.zhao@windriver.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-31Merge tag 'efi-2020-04-rc5' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-04-rc5 This series fixes: * UEFI Python tests CONFIG_OF_CONTROL=y. * int to pointer cast warning for cmd/efidebug.c * memory reservation even if fdt node is disabled Now that the Python test is fixed reintroduce the reverted patch for vexpress_ca9x4 to enable EFI_LOADER and define the dtb file name.
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Fixes for Gen 2 V2H Blanche
2020-03-31arm: dts: agilex: Enable QSPILey Foon Tan
Enable QSPI for Agilex SoC devkit. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: arria10: Add save_boot_params()Ley Foon Tan
Add save_boot_params() to save reset status value from bootrom. Bootrom will clear the status register in reset manager and stores the reset status value in shared memory. Bootrom stores shared data at last 2KB of onchip RAM. This function save reset status provided by bootrom to rst_mgr_status. More information about reset status register value can be found in reset manager register description. When running in debugger without bootrom, r0 to r3 are random values. So, skip save the value when r0 is not bootrom shared data address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macroLey Foon Tan
Change to use SOCFPGA_PHYS_OCRAM_SIZE macro for onchip RAM size. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: Add onchip RAM size macroLey Foon Tan
Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-30Prepare v2020.04-rc4Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-03-30test/py: test_efi_grub_net() requires OF_CONTROLHeinrich Schuchardt
With CONFIG_OF_CONTROL environment variable $fdtcontroladdr is not defined and test_efi_grub_net() fails. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-03-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Fixes env variable for layerscape platforms, disable hs200. - Fixes board fixup, mux setting, enable gic, fspi on lx2160a, Fixes I2C DM Warning on ls1043a, ls1046a - Fixes RGMII port on ls1046ardb, ls1046ardb and DM_USB Warning on ls1012afrdm, ls1021aiot
2020-03-30Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- SPL SPI support R40, H6 (Andre) - eMMC boot part on a64-olinuxino (Petr)
2020-03-30ARM: rmobile: Only register ethernet on V2H Blanche if not DM_ETHMarek Vasut
If the DM_ETH is enabled, the board-specific ethernet registeration should be disabled, make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30ARM: rmobile: Implement PMIC reset on V2H BlancheMarek Vasut
Add code to reset the board through PMIC, by writing the required PMIC registers in the CPU reset handler. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30arm: dts: ls1028a: Use flexspi in octal I/O modeKuldeep Singh
Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30arm: dts: lx2160a: Use flexspi in octal I/O modeKuldeep Singh
Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: lx2160a: Access flash memory as per spi-memKuldeep Singh
MC_INIT and BOOT command currently access spi-nor flash memory directly. As per spi-mem framework, flash memory access via absolute addresses is no more possible. Use flash APIs to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: lx2160a: Define ENV_ADDR valueKuldeep Singh
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define the value as 0x20500000 for lx2160ardb and lx2160aqds. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: lx2160a: Enable FSPI supportKuldeep Singh
Enable FSPI controller support. So, flash environment can now be used. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30arm: dts: lx2160aqds: Add FSPI node propertiesKuldeep Singh
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls1012afrwy: adjust env kernel_addr_rBiwen Li
Adjust environment kernel_addr_r from 0x96000000 to 0x92000000 to fix a bug that failed to boot kernel for ls1012afrwy with 512MiB RAM, => tftpboot $kernel_addr_r Image (Image size is 36 MiB) TFTP error: trying to overwrite reserved memory... Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls1021a: Append othbootargs to bootargsAlison Wang
This patch appends othbootargs to bootargs for LS1021ATWR board. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: disable eMMC HS200 support on layerscape platformsYangbo Lu
The eMMC HS200 speed mode on Layerscape platforms has not been supported properly. The eSDHC clock tuning has not been implemented by now. So disable it until it is supported properly in case of any potential issues. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls1012ardb: secure boot: Add PFE configPriyanka Singh
Add config to enable the PFE and ETH support. Also change the pfe secure boot header address. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: arm: ls1021aiot: enable CONFIG_DM_USB supportRan Wang
Enable CONFIG_DM_USB to remove below compile warning: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: arm64: ls1012afrdm Enable CONFIG_BLKRan Wang
With DM_USB enabled, enable CONFIG_BLK to remove this compile warning for ls1012afrdm based targets: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30dm: arm64: ls1046a: add i2c DM supportBiwen Li
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30dm: arm64: ls1043a: add i2c DM supportBiwen Li
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls1012afrwy: fix wrong env of boardBiwen Li
Fix wrong environment variable of board for ls1012afrwy Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30armv8: ls1028a: clean up the environment variablesYuantian Tang
Move the environment variables from command head file to ls1028ardb specific head file so that they will not mess up with ls1028aqds board. Also updated some variable slightly. There is no function change by this patch. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30armv8: ls1028aqds: add some environmentsYuantian Tang
Add sd and emmc bootcmd environments to facilitate the boot process. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls2080aqds: support distro bootBiwen Li
Add support of distro boot for ls2080aqds Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30configs: ls1088aqds: support distro bootBiwen Li
Add support of distro boot for ls1088aqds Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30board: fsl: lx2160a: fix SDHC1_DAT4 signal routingYangbo Lu
The SDHC1_DAT4 signal could be routes to SDHC1_VS or SDHC1 adapter slot for SDHC1 usage. When SDHC1 is selected in RCW, do not force to route it to SDHC1 adapter slot if find it has already been configued for SDHC1_VS. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30pci-host-ecam-generic: access config space independent of system-wide bus idVladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI bus in the system to be probed. Therefore, the system-wide bus number allocated by U-Boot in sequence for it is going to be zero, which corresponds to the memory-mapped config spaces found within it. Reuse the logic from other PCI bus drivers, and assume that U-Boot will allocate bus numbers in sequence for all buses within the current ECAM. So the base number of the bus needs to be subtracted when indexing the correct config space. Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host controller") Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30include/configs: ls1012afrwy: fix load address of itb with bootm commandBiwen Li
The old load address of itb will overwrite uboots reserved memory on ls1012afrwy with 512 MiB ram Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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