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2020-01-02video: Avoid using #ifdef in video blitting codeSimon Glass
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: x86: Enable 32-bit graphics by defaultSimon Glass
Most x86 boards that use video make use of 32bpp graphics. Enable this by default. This fixes missing graphics output on some x86 boards. Also remove the unnecessary 'default n' while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02pci: layerscape: Manage PCIe EP compatible string via KconfigPankaj Bansal
The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal
move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-31rockchip: evb-rk3328: Enable support ATF in SPLKever Yang
Enable the ATF in SPL and adjust the SPL STACK/HEAD at the same time to support ATF entry at 0x40000. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-31rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmcKever Yang
Since mmc to sram can't do dma, add patch to prevent aborts transfering TF-A parts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-31rockchip: rk3328: add COUNTER_FREQUENCY definitionKever Yang
The arch timer needs COUNTER_FREQUENCY to get correct counter, add it to make the timer works correct. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-28Merge tag 'u-boot-imx-20191228' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - Fixes for Nitrogen6x - Fix corruption for mx51evk - colibri i.MX6: fix broken ESDHC conversion - mx6sxsabresd: fix broken mmcdev - imx6q_logic: cleanup boot sequence - update ATF for imx8mq_evk - pfuze: fix pmic_get() Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Orange Pi Zero Plus 2 support - sunxi psci, prcm fixes
2019-12-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- rk spi transfer limit fix - Gigadevice, gd25q128 support - spi-nor-core warnings
2019-12-27omap3_beagle: Change NAND ECC scheme back to OMAP_ECC_HAM1_CODE_HWPatrik Dahlström
The omap3_beagle NAND ECC scheme was changed in 4b37928d357 for unknown reasons, leading to uncorrectible ecc errors. This commit changes it back to what it was before. Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
2019-12-27rtc: rx8010js: add compatible stringRobert Beckett
Add compatible string used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: s35392a: add compatible stringsRobert Beckett
Add compatible strings used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: rx8010sj: fix DM initializationRobert Beckett
pass the udevice by reference instead of double ref Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27ARM: imx6q_logic: Cleanup boot sequence checkAdam Ford
The board_boot_order() function currenly assumes that the boot source is MMC/eMMC, but this isn't true for the NAND devices. This patch cleans up board_boot_order() to check for NAND, SD, ESD, MMC or EMMC. Anything beyond these are not supported, so it will default back to the serial downloader if any of those devices are not available. Fixes: 9fb50c68daa6 ("ARM: imx6q_logic: Fix MMC2 booting") Signed-off-by: Adam Ford <aford173@gmail.com>
2019-12-27ARM: i.MX6: TARGET_NITROGEN6X: add 'select MX6QDL'Troy Kisky
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata from i.MX6 UP system" for nitrogen6x. The above commit removed the errata for the board since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS This restores the errata configs. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-12-27nitrogen6x: prepare for CONFIG_MX6QDLTroy Kisky
The next patch adds CONFIG_MX6QDL so that errata will be enabled again. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2019-12-27spi: rk: Limit transfers to (64K - 1) bytesJagan Teki
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27mtd: spi-nor-core: Fix static checker warningsVignesh Raghavendra
Static checker warns 'ret' variable may be used uninitialized in spi_nor_erase() and spi_nor_write() in case of zero length requests. Fix these warnings by checking for zero length requests and returning early. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-27tools/imximage: share DCD information via KconfigJorge Ramirez-Ortiz
IMX based platforms can have the DCD table located on different addresses due to differences in their memory maps (ie iMX7ULP). This information is required by the user to sign the images for secure boot so continue making it accessible via mkimage. Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-12-27imx8mq_evk: Update the required ATF branchFabio Estevam
Following the README instructions leads to a non-booting U-Boot: U-Boot SPL 2020.01-rc3-00070-g9a0cbae22a (Nov 25 2019 - 13:08:24 -0300) PMIC: PFUZE100 ID=0x10 DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Trying to boot from MMC2 (It hangs here) Use the "imx_4.19.35_1.0.0" ATF branch instead, which fixes such problem and allow the boot to complete again. Suggested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2019-12-27imx8m_evk: Remove unneeded earlycon stringFabio Estevam
Passing earlycon string in the command line may be useful during bring up, but not after such phase. Remove the earlycon string to align with the other i.MX SoCs command lines. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-27imx8m: ddr_init: Move ddr_init() messages to debug levelFabio Estevam
Currently inside ddr_init() there is a mix of printf() and debug() level messages. Since this type of information is useful for debug purposes, convert all of them to debug level for consistency. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-27mx51evk: Fix U-Boot corruption after saving the environmentFabio Estevam
U-Boot binary has grown in such a way that it goes beyond the reserved area for the environment variables. Running "saveenv" followed by a "reset" causes U-Boot to hang because of this overlap. Fix this problem by increasing the CONFIG_ENV_OFFSET size. Also, in order to prevent this same problem to happen in the future, use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time. CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare CONFIG_ENV_OFFSET with its direct value instead. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-27mx6sxsabresd: Adjust the mmcdev after DM conversionFabio Estevam
After the DM conversion the boot SD card is now device 3. Adjust it so that we can boot the kernel again. While at it avoid a hardcoded mmc dev inside the finduuid script. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-27pfuze: Fix the pmic_get() parameter in the DM caseFabio Estevam
Currently the following hang is observed when booting a imx6sx-sdb board: U-Boot 2020.01-rc5-00004-g643366bcd5 (Dec 19 2019 - 14:56:23 -0300) CPU: Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 32C Reset cause: POR Model: Freescale i.MX6 SoloX SDB RevB Board Board: MX6SX SABRE SDB revA DRAM: 1 GiB initcall sequence bffd8514 failed at call 87804cc0 (err=-19) ### ERROR ### Please RESET the board ### When pmic_get() is used with DM the first parameter must be the complete node name plus the unit address. Fix the pmic_get() parameter to fix the boot regression. Tested on a imx6sx-sdb and imx6q-sabresd boards. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-12-27colibri_imx6: fix broken fsl_esdhc_imx conversionIgor Opaniuk
Not all CONFIG_FSL_ESDHC defines were properly replaced with CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on Colibri iMX6 SoMs. U-boot is stuck after this message: Commercial temperature grade DDR3 timings, 64bit bus width. Trying to boot from MMC1 Fixes: e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-12-27rockchip: mkimage: fix wrong range of rc4 encoding for boot imageJeffy Chen
The rc4 encoding should cover spl header as well, and the file_size contains spl header too. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27doc: rockchip: document packing second level loader with mkimageJeffy Chen
Add documentation about packing optional second level boot-loader with mkimage tool. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: mkimage: support packing optional second level boot-loaderJeffy Chen
Support packing optional second level boot-loader: $ ./tools/mkimage -n rk3399 -T rksd -d \ rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v Adding Image rk3399_ddr_800MHz_v1.24.bin Size 116492(pad to 116736) Adding Image rk3399_miniloader_v1.19.bin Size 88060(pad to 88064) Image Type: Rockchip RK33 (SD/MMC) boot image Init Data Size: 116736 bytes Boot Data Size: 88064 bytes Mainly parse init file and boot file from datafile option, copy them to the image with 2KB alignment. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27doc: rockchip: Fix reference the wrong defconfig name of ROC-CC-RK3308Andy Yan
The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig. Fixes: 7f08bfb74f04 ("doc: rockchip: Add documentation for rk3308 based boards") Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: rk3308: allow loading larger kernel ImageAndy Yan
When compile the curren mainline linux kernel(Linux 5.5-rc3) with defconfig, the final Image is 29M, it's much larger than Linux 5.4. On the current u-boot side on rk3308, the gap between kernel and fdt is 25M, the fdt will overwrite kernel Image, so move ftd to a higher memory to give 34M gab for them. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: add description for TPL_ROCKCHIP_COMMON_BOARDThomas Hebb
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but this one doesn't for some reason. Add a description to make the menu easier to read. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: px30-firefly add standalone dtsKever Yang
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot proper will use the dts setting to do the IOMUX init, and a separate dts is needed for px30-firefly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: firefly-px30: Fix the MACRO for CONFIG_DEBUG_UART2_CHANNELKever Yang
The Macro has update without update the defconfig, update the defconfig to make Mcaro correct. Fixes: ec4fafdf1f ("rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to...") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: make_fit_atf: explicitly use python3Jack Mitchell
On a distribution with no python2 installed and no python->python3 symlink the script will fail to execute. Specify python3 explicitly as it's already a requirement to build u-boot. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26Merge branch '2019-12-26-ti-imports'Tom Rini
- Update maintainer on omapl138_lcdk - Match TRM sequence & settings in the TI pipe3 PHY
2019-12-26board: davinci: Update OMAPL138_LCDK maintainerLokesh Vutla
As per the email discussion[0], add myself as a maintainer to OMAPL138_LCDK and drop Peter's entry. [0] http://u-boot.10912.n7.nabble.com/OMAP-L138-LCDK-giving-up-maintainership-td394211.html Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-26phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Use TRM recommended settings for SATA DPLLRoger Quadros
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26rockchip: rk3288-evb: update config to support OPTEEKever Yang
Upstream kernel and rockchip kernel has default enable PSCI which needs OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT option to pack OPTEE with U-Boot proper. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update CONFIG_NR_DRAM_BANKS to 2Kever Yang
The OPTEE will use the ram start at 0x8400000 which make the DRAM be two banks. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399Kever Yang
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for STACK and the size may not enough when loding FIT image in SPL. If the size is not enough, you can see log like this when loding FIT: U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800) Trying to boot from MMC2 And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc sending CMD16 for 'uboot' loadables binary because this step need a large stack cost(about 0x2d00). External data: dst=8400000, offset=72638, size=b3580 Image OS is Trusted Execution Environment board_fit_config_name_match: rk3288-evb Selecting config 'rk3288-evb'loadables: 'uboot' blk_find_device: if_type=6, devnum=1: dwmmc@ff0c0000.blk, 6, 0 blk_find_device: if_type=6, devnum=1: dwmmc@ff0f0000.blk, 6, 1 Sending CMD16 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: fit_spl_optee: get text and optee base from buildKever Yang
Instead of hardcode the base address, we can get them from the build output, eg. get the SYS_TEXT_BASE from .config and get optee base from DRAM_BASE. We can use this script for SoCs with DRAM base not from 0x60000000(rk3229 and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160AWasim Khan
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM for lx2160a. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape_gen4: Suffix API names with _ls_gen4Wasim Khan
Update API names for layerscape gen4 fixup. Suffix layerscape_gen4 fixup API names with _ls_gen4. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape: Suffix API names with _lsWasim Khan
Suffix layerscape fixup API names with _ls. This is required to organize device tree fixup in common, layerscape and layerscape_gen4 specific code. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26pci: layerscape: Add stream_id_cur field to ls_pcie structureWasim Khan
Add stream_id_cur field to ls_pcie structure and initialize it with 0 for all pcie controllers. This field will be used for streamId calculation. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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