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2019-05-08pinctrl: rockchip: Remove redundant spacesDavid Wu
Some files have the redundant spaces, remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Add pull-pin-default param and remove unused paramDavid Wu
Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"Kever Yang
This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: chromebook_minnie: Enable soundSimon Glass
Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3399: update defconfig for TPLKever Yang
The SPL is now running at SDRAM, and 0x10000 is used by BL31, and the ARM SPL do not support relocate now, we need reserved 0x50000 so that it won't overwrite the code when we load the bl31 to target space. We should remove this after we enable the relocate feature. The SPL need malloc 0x9000 for MMC as buffer used for transfer data to IRAM(The EMMC DMA can not transfer data to IRAM directly). Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: ram: rk3399: update for TPLKever Yang
Init the ddr sdram in TPL instead of SPL, update the code. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk3399: add tpl supportKever Yang
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add u-boot-tpl-v8.ldsKever Yang
We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08rockchip: px5: add timer0 dts node as tick timerKever Yang
Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3368: remove uart iomux init in SPLKever Yang
The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: dmc: rk3368: update rank number for evb-px5Kever Yang
evb-px5 has only 1 CS, update for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL onlyKever Yang
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5: update defconfig for TPL/SPLKever Yang
Add options to support TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5: update SPL size for spl/tplKever Yang
Use larger space for load bl31 in SPL Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: px5 update dts for spl/tplKever Yang
TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk3368: support UART2/4 in board_debug_uart_init()Kever Yang
evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: evb-rk322x: update defconfig with tpl and optee supportKever Yang
Enable all the options for TPL/SPL and OPTEE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: evb-rk3229: add README file for OP-TEE supportKever Yang
Detail of step by step to bring up the board with OP-TEE support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: evb-rk3229: remove unnecessary definesKever Yang
Prefer to use default setting like other SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: dts: enable uart2 for SPL/TPLKever Yang
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08sysreset: enable driver support in SPL/TPLKever Yang
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add tpl supportKever Yang
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add a separate stack for TPLKever Yang
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add option for TPL support in arm 32bitKever Yang
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"Kever Yang
This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: remove ARCH_ROCKCHIP macro in common codeKever Yang
This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add common header boot0.h and gpio.h for socKever Yang
boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- RZ/A1 addition. - Old board removal.
2019-05-07Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Assorted stratix10 fixes. - DDR driver DM migration.
2019-05-07ARM: dts: renesas: Add RZ/A1 GR-Peach boardChris Brandt
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07ARM: dts: renesas: Add RZ/A1 platform codeChris Brandt
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07spi: rpc: Add support for operation without clock frameworkMarek Vasut
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07net: sh_eth: Add support for operation without clock frameworkMarek Vasut
Add ifdeffery to allow operation without the clock framework enabled. This is required on RZ/A1, as it does not have clock driver yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07net: sh_eth: Add RZ/A1 supportMarek Vasut
Add support for RZ/A1 SoC specifics. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07serial: sh: Add RZ/A1 supportMarek Vasut
Add support for RZ/A1 SoC specifics. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07timer: renesas: Add RZ/A1 R7S72100 OSTM timer driverMarek Vasut
Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07pinctrl: renesas: Add RZ/A1 R7S72100 pin control driverMarek Vasut
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07gpio: renesas: Add RZ/A1 R7S72100 GPIO driverMarek Vasut
Add GPIO driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07sh: 7785: Remove CPU supportMarek Vasut
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-07sh: sh7785lcr: Remove the boardMarek Vasut
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-07sh: 7724: Remove CPU supportMarek Vasut
There are no more boards using this CPU and there is no prospect of any boards showing up soon, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-07sh: ecovec: Remove the boardMarek Vasut
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-07sh: sh7757lcr: Fix copy-paste error in READMEMarek Vasut
Update the README to use the correct defconfig. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various pinctrl / gpio fixes for R-Car
2019-05-06Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Important spi-mem fix
2019-05-06ARM: socfpga: stratix10: Probe FPGA status before bridge enableAng, Chee Hong
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure Device Manager (SDM) to get the status of FPGA and make sure the FPGA is in user mode before enable the bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-05-06ARM: socfpga: stratix10: Disable FPGA2SOC resetAng, Chee Hong
Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-05-06arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit (git 2.34.1) at 2024-12-25 15:51:41 +0000