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2014-09-09arm: vf610: lpuart: disable FIFO on initializatonStefan Agner
UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09arm: vf610: lpuart: fix status register handlingStefan Agner
The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2014-09-09imximage: Fix imximage IVT bug for EIM-NOR bootYe.Li
The load region size of EIM-NOR are defined to 0. For this case, the parameter "imximage_init_loadsize" must be calculated. The imximage tool implements the calculation in the "imximage_generate" function, but the following function "imximage_set_header" resets the value and not calculate. This bug cause some fields of IVT head are not correct, for example the boot_data and DCD overlay the application area. Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-09iMX6: Disable the L2 before chaning the PL310 latencyYe.Li
The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
2014-09-09imx: ventana: Avoid undefined behaviourThierry Reding
The leds array within struct ventana has space for 3 elements, but the setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent versions of GCC complain about that: board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio': board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations] if (gpio_cfg[board].leds[i]) ^ board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop for (i = 0; i < 4; i++) { ^ Fix this by making the upper bound of the loop match the array size. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09tools: imximage: Fix the maximum DCD size for mx53/mx6Fabio Estevam
According to mx53 and mx6 reference manuals: "The maximum size of the DCD limited to 1768 bytes." As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and excluding the first entry, which is the header leads to 220 as the maximum number for DCD size. Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
2014-09-09imx: ventana: add pci fixup for PLX PEX860x switch GPIOTim Harvey
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion. These boards use GPIO on the PLX device as PERST# for the downstream ports thus we assert this when the PLX is enumerated. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09pci: add support for board_pci_fixup_dev functionTim Harvey
Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09arm: mx6: cm_fx6: add sata supportNikita Kiryanov
Add support for SATA. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: cm_fx6: use eepromNikita Kiryanov
Use Compulab eeprom module to obtain revision number, serial number, and mac address from the EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: cm_fx6: add i2c supportNikita Kiryanov
Add support for all 3 I2C busses on Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: cm_fx6: add usb supportNikita Kiryanov
Add USB and USB OTG host support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: cm_fx6: add ethernet supportNikita Kiryanov
Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: cm_fx6: add nand supportNikita Kiryanov
Add NAND support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: add support for Compulab cm-fx6 CoMNikita Kiryanov
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: add get_cpu_type()Nikita Kiryanov
Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov
Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09arm: mx6: ddr: do not write into reserved bitNikita Kiryanov
Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: ddr: cleanupNikita Kiryanov
No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov
Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov
Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09compulab: eeprom: add support for defining eeprom i2c busNikita Kiryanov
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09mx6: add clock enabling functionsNikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09imx: ventana: added cputype env varTim Harvey
There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: add GW5520 supportTim Harvey
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as: * 2x MiniPCIe sockets * 2x USB host sockets * 2x i210 GigE * HDMI out * digital I/O expansion Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: base SPL MMDC calibration on width and size not boardTim Harvey
The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: updated notes regarding NAND boot errataTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-09Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-05CONFIGS: peach-pit: Enable display for peach_pit boardAjay Kumar
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chipAjay Kumar
This patch adds DT properties for fimd and the parade bridge chip present on peach_pit. The panel supports 1366x768 resolution. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05exynos5420: add callbacks needed for exynos_fb driverAjay Kumar
Add initialization code for peach_pit panel, parade bridge chip, and backlight. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05ARM: exynos: Add missing declaration for gpio_direction_inputAjay Kumar
This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05video: Add driver for Parade PS8625 dP to LVDS bridgeVadim Bendebury
The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05video: exynos_fimd: Add framework to disable FIMD sysmmuAjay Kumar
On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arm: exynos: Add RPLL for Exynos5420Ajay Kumar
RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05exynos_fb: Remove usage of static definesAjay Kumar
Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05sun7i: Add support for Olimex A20-OLinuXino-LIMEFUKAUMI Naoki
This patch adds support for Olimex A20-OLinuXino-LIME board. Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-09-05sunxi: Correct typo CONFIG_FTDFILE => CONFIG_FDTFILEIan Campbell
Patch is the result of: sed -i -e 's/FTDFILE/FDTFILE/g' board/sunxi/Kconfig configs/* include/configs/sunxi-common.h sed -i -e 's/ftdfile/fdtfile/g' board/sunxi/Kconfig Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> [ ijc -- s/Spotted-by/Reported-by/ and resolve conflict vs "remove redundant "SPL" from CONFIG_SYS_EXTRA_OPTIONS" ]
2014-09-05kconfig: remove redundant "SPL" from CONFIG_SYS_EXTRA_OPTIONSMasahiro Yamada
CONFIG_SPL is defined as a primary option in Kconfig. It should not be added to CONFIG_SYS_EXTRA_OPTIONS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-09-05odroid: set MPLL clock to 880MHzPrzemyslaw Marczak
This patch changes MPLL from 800MHz to 880MHz on Odroid. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05MAINTAINERS: update the maintainer of Arndale boardMasahiro Yamada
Inderpal's email address is not working any more. Chander will be a new maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05odroid: kconfig: add odroid_defconfigPrzemyslaw Marczak
This config is valid for two devices: - Odroid X2, - Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05odroid: add odroid U3/X2 device tree descriptionPrzemyslaw Marczak
This is a standard description for Odroid boards. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412Przemyslaw Marczak
This board file supports standard features of Odroid X2 and U3 boards: - Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz, - MAX77686 power regulator, - USB PHY, - enable XCL205 - power for board peripherials - check board type: U3 or X2. - enable Odroid U3 FAN cooler Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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