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2019-04-12dt: bcm63158: add gpio controllerPhilippe Reynes
Add 8 gpio controllers in the bcm63158 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12gpio: do not include <asm/arch/gpio.h> on ARCH_BCM63158Philippe Reynes
As no gpio.h is defined for this architecture, to avoid a compilation failure, do not include <asm/arch/gpio.h> for arch bcm63158. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12gpio: bcm6345: allow this driver on ARCH_BCM63158Philippe Reynes
This IP is also used on some arm SoC, so we allow to use this driver on arch bcm63158. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12bcm968580xref: enable gpio supportPhilippe Reynes
Enable the gpio support (driver and command) in the configuration of the board bcm968580xref. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12dt: bcm968580xref: enable gpio controllerPhilippe Reynes
Enable all the gpio controllers in the device tree of the board bcm968580xref. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12dt: bcm6858: add gpio controllerPhilippe Reynes
Add 8 gpio controllers in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12gpio: do not include <asm/arch/gpio.h> on ARCH_BCM6858Philippe Reynes
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for arch bcm6858. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12gpio: bcm6345: allow this driver on ARCH_BCM6858Philippe Reynes
This IP is also used on some arm SoC, so we allow to use this driver on arch bcm6858. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12bcm968380gerg: enable gpio supportPhilippe Reynes
Enable the gpio support (driver and command) in the configuration of the board bcm968380gerg Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12dt: bcm968380gerg: enable gpio controllerPhilippe Reynes
Enable the gpio controllers in the device tree of the board bcm968380gerg. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12dt: bcm6838: add gpio controllerPhilippe Reynes
Add gpio controllers in bcm6838 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12gpio: bcm6345: switch to raw I/O functionsPhilippe Reynes
This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12ag7xxx: add initial support for s17Rosy Song
S17 ethernet support is for QCA8337N, which used on AP152 (QCA9563) board. It is a 7 ports GbE switch. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more commit message for s17 Changes for v4-v5: - coding style cleanup
2019-04-12mips: add initial support for qca956x referenced boardRosy Song
QCA9563 is CPU used on AP152 board : Clock speed : 750 MHz , Arch : Mips 74Kc, Eth : SGMII interface, MIMO config : 3 * 3 450M, 2 * USB 2.0, Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2: - coding style cleanup - remove ununsed flash chip in defconfig - enable automatic icache / dcache size in defconfig Changes for v3: - add detailed information for qca956x in commit message Changes for v4: - remove pre-configured network settings in ap152.h Changes for v5: - coding style cleanup
2019-04-12mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956XRosy Song
See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet, NFRAC[17:0] So the mask of [17:5] is 0x1fff not 0x3fff. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more information for this commit Changes for v4-v5: - coding style cleanup
2019-04-12dma: bcm6348: check if driver is enabled before send/recvÁlvaro Fernández Rojas
This patch prevents errors when running tftpput. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-04-12net: mscc: ocelot: Fix reset of the physHoratiu Vultur
The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12bootm: mips: Remove boot_reloc_ramdiskHoratiu Vultur
Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm because it is relocating again the ramdisk. The function do_bootm_states() already relocates the ramdisk even if it is a legacy uImage or a FIT image. The relocation in the function do_bootm_states() was introduce in the commit c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12mips: mt76xx: gardena-smart-gateway: Correct spelling of GARDENAStefan Roese
This patch changes Gardena to the correct GARDENA spelling. Also the platform name is "GARDENA smart Gateway". This patch changes the incorrect occurrances. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12mips: mt76xx: linkit: Add mtd command supportStefan Roese
The new mtd is very useful so let's enable it on the LinkIt Smart 7688 as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jiri Kastner <cz172638@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12mips: add ethernet support for qca953x referenced boardsRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12drivers: add ethernet support for qca953x in ag7xxx driverRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12drivers: fix typo for pinctrl qca953xRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driverChristophe Kerello
The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2019-04-12dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentationChristophe Kerello
This patch adds the documentation of the device tree bindings for the STM32 FMC2 NAND controller. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-12spi: stm32_qspi: move to exec_opChristophe Kerello
We are facing issues in the driver since SPI NOR framework has moved on SPI MEM framework, and SPI NAND framework is not running properly with the current driver. To be able to solve issues met on SPI NOR Flashes and to be able to support SPI NAND Flashes, the driver has been reworked. We are now using exec_op ops instead of using xfer ops. Thanks to this rework, the driver has been successfully tested with: - mx66l51235l SPI NOR Flash on stm32f746 SOC - n25q128a SPI NOR Flash on stm32f769 SOC - mx66l51235l SPI NOR Flash on stm32mp1 SOC - mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-12ARM: dts: Add STMFX gpio expander support for stm32mp157c-ev1Patrick Delaunay
Adds alias to set the pincontrol seq id. For STMFX gpio expander, force sequence number after the last bank (GPIOZ) to avoid conflict between STM32MP and STMFX gpio bank sequence number. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12board: stm32mp1: Force pinctrl driver probe in board_init()Patrice Chotard
In order to insure that hog GPIOs are configured early during the boot process, force all pinctrl driver probing in board_init(). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12config: stm32mp15: Enable STMFX supportPatrick Delaunay
Activate PINCTRL_STMFX and needed part for generic pincontrol PINCTRL_FULL, PINCONF. Increase pre-reloc memory for MALLOC (needed for each DM pinconfig node). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverPatrick Delaunay
This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on UCLASS_PINCTRL and UCLASS_GPIO. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12ARM: dts: stm32mp1: Add adc nodesPatrice Chotard
Add adc related nodes. These nodes are used to detect the current supplied by USB type-C power in port on DK1 and DK2 boards. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12Board: stm32mp1: Add supply current boot informationPatrice Chotard
For DK1/DK2 boards, check if power supply provides enough current to allow the board to boot correctly. ADC@0 channel 18 and 19 are connected to USB type-C CC1 and CC2 signals. The table below shows the behavior for different range of CC1 or CC2: range | power supply | red led | console message (Volts) | (Amps) | blinks | --------------|--------------|---------|----------------------------------- [2.10 - 1.23[ | 3 | NO | NO [1.23 - 0.66[ | 1.5 | 3 times | WARNING 1.5A power supply detected [0.66 - 0] | 0.5 | 2 times | WARNING 500mA power supply detected If detected current is < 3A, red led is kept ON after blinking. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12board: stm32mp1: Update README filePatrice Chotard
Update README with DK1 and DK2 boards related informations Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12ARM: dts: stm32: Synchronize DT with kernel onePatrice Chotard
This patch synchronizes U-boot DT with kernel one This is based on https://patchwork.kernel.org/cover/10797115/ This patch adds initial support of STM32MP157 discovery boards: - Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1). This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios) and 512MB of DDR3. Several connections are available on this boards: 4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ... - Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2). This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a) and Murata wifi/BT combo is added. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12stpmic1: add NVM update support in fuse commandPatrick Delaunay
Add functions to read/update the non volatile memory of STPMIC1 (8 bytes-register at 0xF8 address) and allow access with fuse command (bank=1, word > 0xF8). For example: STM32MP> fuse read 1 0xf8 8 Reading bank 1: Word 0x000000f8: 000000ee 00000092 000000c0 00000002 Word 0x000000fc: 000000f2 00000080 00000002 00000033 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: dts: activate psci-1.0Patrick Delaunay
Updates the stm32mp157c devicetree to bind the U-Boot PSCI driver need for power off command; TF-A for stm32mp15x supports PSCI 1.0. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: add command poweroffPatrick Delaunay
Activate the command poweroff by default for STM32MP1: - with PCSI from TF-A for trusted boot - with PMIC sysreset request for basic boot (SYSRESET_POWER) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12pmic: stpmu1: add power switch off supportPatrick Delaunay
Add sysreset support, and support power switch off request, needed by poweroff command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stpmic1: update register namesPatrick Delaunay
Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12power: rename stpmu1 to official name stpmic1Patrick Delaunay
Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12power: stpmu1: rename files to stpmic1Patrick Delaunay
Prepare file modification for kernel alignment and rename driver to stpmic1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12regulator: stpmu1: update buck1 rangePatrick Delaunay
SW impact for Rev 1.2 of STPMIC1 in U-Boot: Buck converters output voltage change for Buck1 => Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V (see STPMIC1 datasheet / chapter 5.3 Buck converters) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: Replace OTP read by SHADOW readPatrick Delaunay
Replace STM32_BSEC_OTP() by STM32_BSEC_SHADOW() to increase read performance. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: bsec: shadow all the upper OTP (no secure) during bootPatrick Delaunay
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: bsec: use device tree new compatiblePatrick Delaunay
Update bsec driver to use the device tree provided by Kernel. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: basic boot: SPL enable access to GPIOZ bankPatrick Delaunay
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank (open security). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: align serial number on bootromPatrick Delaunay
Always use upper case for serial number. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: add syscfg initializationPatrick Delaunay
Initialize the system configuration for basic boot - update interconnect setting - disable pull-down for boot pin - enable High Speed Low Voltage Pad mode for SPI, SDMMC, ETH, QSPI - activate I/O compensation Done by SSBL = TF-A for trusted boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: add some syscon drivers for syscfg and etpzcPatrick Delaunay
Add SYSCON driver for syscfg and etpzc and reorder in alphabetics order Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: activated some configurationPatrick Delaunay
Add configuration useful for test - FIT support - MEMTEST - DFU - CACHE - TIME - TIMER Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
generated by cgit (git 2.34.1) at 2025-02-24 01:43:03 +0000