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2017-01-10microblaze: Remove hardcoded IP address from configMichal Simek
IP addresses shouldn't be hardcoded in board config. This patch removes them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10microblaze: Make the board configuration name user definableSai Pavan Boddu
Add a prompt for editing in menuconfig Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10net: gem: Use wait_for_bit() instead of private mdio_wait()Michal Simek
Using generic wait_for_bit() implementation instead of using private wait function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10lib: Add WATCHDOG_RESET to wait_bit.hMichal Simek
wait_for_bit() is missing reset watchdog in case watchdog is configured. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-09scsi: dm: Unbind all scsi based block devices before new scanMichal Simek
New scan should unbind all block devices not to be listed again. Without this patch if scsi reset or scan is called new block devices are created which point to the same id and lun. For example: ZynqMP> scsi scan scsi_scan: if_type=2, devnum=0: sdhci@ff170000.blk, 6, 0 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 0 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 1 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 2 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 3 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 4 scanning bus for devices... Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A Type: Hard Disk Capacity: 57241.8 MB = 55.9 GB (117231408 x 512) Reported-by: Ken Ma <make@marvell.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-01-09defconfig: am335x_evm: enable usb driver modelMugunthan V N
enable usb driver model for am335x bbb as musb supports driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-09am335x_evm: enable usb ether gadget as it supports DM_ETHMugunthan V N
Since usb ether gadget have support for driver model, so enable usb ether gadget. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-09am33xx: board: init usb ether gadget for rndis supportMugunthan V N
Add usb ether gadget device with usb_ether_init() when CONFIG_DM_ETH and CONFIG_USB_ETHER are defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-01-09drivers: usb: gadget: ether/rndis: convert driver to adopt device driver modelMugunthan V N
Adopt usb ether gadget and rndis driver to adopt driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2017-01-09Prepare v2017.01Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-09lib: gitignore *.elf and *.so generated by efi_loaderLadislav Michl
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
2017-01-08scripts/config_whitelist.txt: ResyncTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-08mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfigJagan Teki
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig which is missing in below commit "imx: mx6ull_14x14_evk: add plugin defconfig" (sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031) Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-08am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASEAndrew F. Davis
The SPL load address changes based on boot type in HS devices, ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs for similar reasons. Add this same logic for AM33xx devices. Also make the default value for ISW_ENTRY_ADDR correct for GP devices based on SoC, HS devices already pick the correct value in their defconfig. Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-01-08arm: mach-omap2: Fix secure file generationAndrew F. Davis
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was not generated but generate an unsigned one anyway, first fix this warning to say that it was generated but not secured. When the user then exports TI_SECURE_DEV_PKG after getting this warning, and tries to re-build, 'make' will detect the build artifacts as unchanged and so assume they do not need to be re-generated. This causes it to fail to sign the files and it will pack unsigned files into the final image, even though TI_SECURE_DEV_PKG is now correctly defined and working. Fix this by using FORCE on the targets causes them to be re-run even if the dependent files have not changed. This then causes another issue. We currently rename the signed dtb files to overwrite the non-signed ones. We do this so the 'mkimage' tool gives the packaged dtb sections the correct name. If we do not rename the files then SPL will not find them during boot. Fix this by renaming the dtb files by appending _HS to the end of the filename, after the ".dtb", this causes them to still be named correctly in the FIT blob. Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-01-04Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2017-01-04Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2017-01-04powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to KconfigYork Sun
Use Kconfig option SYS_PPC64 instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to KconfigYork Sun
Use Kconfig option to select chassis version. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: E6500: Move macro CONFIG_E6500 to KconfigYork Sun
Use Kconfig option E6500 and clean up existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Remove unused ifdef in config headerYork Sun
After most config options are moved to Kconfig, the unused ifdef or elif can be removed. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to KconfigYork Sun
Use Kconfig to select DDR version instead of using config header. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLSYork Sun
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to KconfigYork Sun
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13, SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig. Move existing macros to related Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate bk4r1] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04fsl_ddr: Move DDR config options to driver KconfigYork Sun
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDSYork Sun
Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: T2081QDS: Remove macro T2081QDSYork Sun
Use TARGET_T2081QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: T2080RDB: Remove macro CONFIG_T2080RDBYork Sun
Use TARGET_T2080RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: T2080QDS: Remove macro T2080QDSYork Sun
Use TARGET_T2080QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: T1040QDS: Remove macro CONFIG_T1040QDSYork Sun
Use TARGET_T1040QDS from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: T1024RDB: Remove macro CONFIG_T1024RDBYork Sun
Use TARGET_T1024RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Get missing hunk in board/freescale/t102xrdb/ddr.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04powerpc: T1023RDB: Remove macro CONFIG_T1023RDBYork Sun
Use TARGET_T1023RDB from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014York Sun
Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to KconfigYork Sun
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04crypto: Move SYS_FSL_SEC_COMPAT into driver KconfigYork Sun
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to KconfigYork Sun
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate 8572] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to KconfigYork Sun
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to KconfigYork Sun
Use Kconfig option for E500 and E500MC macros. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' printJagan Teki
SPL from nand will print 'NAND' in boot_from_devices based on the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver. Original behaviour: ------------------- U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19) Trying to boot from NANDNAND : 512 MiB After the fix: ------------- U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00) Trying to boot from NAND: 512 MiB Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-04spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possibleVignesh R
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface reads until the last word of an indirect transfer So, make sure that QSPI indirect reads are 32 bit sized except for the final read. If the rxbuf is unaligned then use bounce buffer, so that readsl() can be used instead of readsb() to avoid non 32-bit accesses. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possibleVignesh R
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: A64: enable SPLAndre Przywara
Now that the SPL is ready to be compiled in AArch64 and the DRAM init code is ready, enable SPL support for the A64 SoC and in the Pine64 defconfig. For now we keep the boot0 header in the U-Boot proper, as this allows to still use boot0 as an SPL replacement without hurting the SPL use case. We disable FEL support for now by making its compilation conditional and disabling it for ARM64, as the code isn't ready yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: DRAM: fix H3 DRAM size display on aarch64Andre Przywara
Fix the output of the DRAM size on AArch64 SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: H3/A64: fix non-ODT settingAndre Przywara
According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: A64: use H3 DRAM initialization code for A64 as wellJens Kuske
The A64 DRAM controller is very similar to the H3 one, so the code can be reused with some small changes. This refactoring does not change the code size for the existing H3 part. [Andre: rework from #ifdefs to using socid parameters in static functions, minor fixes, merging in fixes from Jens] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: clocks: Use the correct pattern register for PLL11Philipp Tomsich
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: H3: add DRAM controller single bit delay supportJens Kuske
So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as well) only applied coarse delay line settings, with one delay value for all the data lines in each byte lane and one value for the control lines. Instead of setting the delays for whole bytes only allow setting it for each individual bit. Also add support for address/command lane delays. For the purpose of this patch the rules for the existing coarse settings were just applied to the new scheme, so the actual register writes don't change for the H3. Other SoCs will utilize this feature later properly. With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from 2296 to 2344 Bytes. [Andre: move delay parameters into macros to ease later sharing, use defines for numbers of delay registers, extend commit message] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit (git 2.34.1) at 2025-01-05 05:12:41 +0000