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2013-02-01arm: Move tbu to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01arm: Move timer_rate_hz into arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01at91: Move at91 global data into arch_global_dataSimon Glass
Move these fields into arch_global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01Add architecture-specific global dataSimon Glass
We plan to move architecture-specific data into a separate structure so that we can make the rest of it common. As a first step, create struct arch_global_data to hold these fields. Initially it is empty. This patch applies to all archs at once. I can split it if this is really a pain. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-01-31vfat: Fix mkcksum argument sizesMarek Vasut
In case a function argument is known/fixed size array in C, the argument is still decoyed as pointer instead ( T f(U n[k]) ~= T fn(U *n) ) and therefore calling sizeof on the function argument will result in the size of the pointer, not the size of the array. The VFAT code contains such a bug, this patch fixes it. Reported-by: Aaron Williams <Aaron.Williams@cavium.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <tom.rini@gmail.com> Cc: Aaron Williams <Aaron.Williams@cavium.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2013-01-30arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach
No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
2013-01-30Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2013-01-31MIPS: qi_lb60: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. The qi_lb60 target produces a slightly different image after the change than before. The value of 'num_got_entries' symbol is different: @@ -49,7 +49,7 @@ 801000b4: 80122d00 lb s2,11520(zero) 801000b8: 80123500 lb s2,13568(zero) 801000bc: 80123ef8 lb s2,16120(zero) -801000c0: 00000139 0x139 +801000c0: 00000136 tne zero,zero,0x4 801000c4 <in_ram>: 801000c4: 8d0bfffc lw t3,-4(t0) This is caused by the different placement of the '__got_start' and '__got_end' symbols between the board specific scrip and the unified script. board specific script: __got_start = .; .got : { *(.got) } __got_end = .; unified script: .got : { __got_start = .; *(.got) __got_end = .; } Despite this difference, the resulting images are functionally identical. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-31MIPS: dbau1x00: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All dbau1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: incaip: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All incaip targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de>
2013-01-31MIPS: vct: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All vct targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: pb1x00: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All pb1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: qemu-mips: use the unified u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All qemu_mips targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: add unified u-boot.lds fileGabor Juhos
The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net> Acked-by: Stefan Roese <sr@denx.de>
2013-01-30MIPS: remove OUTPUT_FORMAT from linker scriptsGabor Juhos
The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30MIPS: xburst: simplify relocation offset calculationGabor Juhos
The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30MIPS: simplify relocated _G_O_T_ address calculationGabor Juhos
The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30corenet: Disable video on P2020DSAndy Fleming
The P2020DS build had grown too large, and video support isn't enabled in almost any other Freescale board. Disabling it allows us to keep building, and provides options for reenabling it later. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30board/common: Add support for QIXIS read/write using i2cPrabhakar Kushwaha
QIXIS FPGA is accessable via both i2c and flash controller. Only flash controller access is supported. Add support of i2c based access. It is quite useful in the scenario where either flash controller path is broken or not present. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu
When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg
If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUEAnatolij Gustschin
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in the board config file doesn't work and memory is always initialized to the value 0xdeadbeef. Only use this default value if a board doesn't define CONFIG_MEM_INIT_VALUE. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood
e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/85xx: Add BSC9132QDS supportPrabhakar Kushwaha
BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha
The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commandsJames Yang
This patch adds the ability for the FSL DDR interactive debugger to automatically run the sequence of commands stored in the ddr_interactive environment variable. Commands are separated using ';'. ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30README.fsl-ddr typos and update to reflect hotkeyJames Yang
Documentation fix to README.fsl-ddr to fix typos and to reflect use of 'd' hotkey to enter the FSL DDR debugger. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30Add copy command to FSL DDR interactiveJames Yang
Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30Fix data stage name matching issueJames Yang
This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30Move DDR command parsing to separate functionJames Yang
Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun
Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDBValentin Longchamp
In order to be able to build a u-boot.pbl image, both the CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be defined. This patch sets these two files for the P2041RDB board. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/p2041: add RCW file for P2041RDBValentin Longchamp
All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board. This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240qds: Print FPGA detail versionPrabhakar Kushwaha
Qixis FPGA has tag data contains image name and build date. It is helpful to identify the FPGA image precisely. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240qds: Add support to dump switch settings on t4240qds boardShaveta Leekha
This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/b4860qds: Add support to dump switch settings on b4860qds boardShaveta Leekha
This function is called by "qixis_reset switch" command and switch settings are calculated from FPGA/qixis registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/qixis: enable qixis dump command and add switch dumping commandShaveta Leekha
Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/b4860qds: Added Support for B4860QDSYork Sun
B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor. B4860QDS Overview ------------------ - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB of memory in two ranks of 2 GB. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch VSC3316 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. - B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for AMC mode. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The RCW source is set by appropriate DIP-switches: - 16-bit NOR Flash / PROMJet - QIXIS 8-bit NOR Flash Emulator - 8-bit NAND Flash - 24-bit SPI Flash - Long address I2C EEPROM - Available debug interfaces are: - On-board eCWTAP controller with ETH and USB I/F - JTAG/COP 16-pin header for any external TAP controller - External JTAG source over AMC to support B2B configuration - 70-pin Aurora debug connector - QIXIS (FPGA) logic: - 2 KB internal memory space including - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1, 2 and RTCCLK. - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks - total four refclk, including CPRI clock scheme Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha
Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30board/freescale/common:Add support of QTAG registerPrabhakar Kushwaha
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE fields. These fields have FPGA build version, image name and build date information. Add support to parse these fields to have complete FPGA image information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal
- Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc8544ds: Add USB controller support for MPC8544DSHongtao Jia
USB controller in uboot is a required feature for MPC8544DS. Without this support there is no 'usb' command in uboot. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMsHongtao Jia
The controller interleaving only takes the usable memory mapped to cs0. In the case of bank interleaving not enabled, only half of dual-rank DIMM will be used. For single-rank DIMM bank interleaving will be auto disabled. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240qds: Update IFC timing for NOR flashYork Sun
Relax parameters to give address latching more time to setup. Tighten parameters to make it overall faster. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30boards/T4240qds:Fix IFC AMASK init as per FPGA register spacePrabhakar Kushwaha
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's Address Mask Registers is initialised 64K size. So Fix the Address Mask Register initilisation as 4K Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30board/T4240qds:Fix TLB and LAW size of NAND flashPrabhakar Kushwaha
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's Address Mask Registers is initialised with the same. So Update TLB and LAW size of NAND flash accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/mpc85xx: Reserve default boot pageYork Sun
The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.cTimur Tabi
Static variables should be defined in C files, not header files, because otherwise every C file that #includes the header file will generate a duplicate of the variables. Since the vsc3316_xxx[] arrays are only used by t4qds.c anyway, just put the variables there. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/p2041: move Lanes mux to board early initShaohui Xie
Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit (git 2.34.1) at 2024-12-26 18:08:33 +0000