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AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.
Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Because there isn't the implementation of gpio_set/get_value()
and gpio_set/get_value() after the at91 gpio driver is converted
to support the driver model, use at91_set_gpio_value() and
at91_get_gpio_value()
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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When the CONFIG_ATMEL_LEGACY is undefined, according to the following
defines, at91_set_gpio_value() references to at91_set_pio_value(x, y)
with two parameters.
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
But there isn't the implementation of at91_set_pio_value(x, y) with
two parameters in U-Boot. This is an error.
Same as at91_get_gpio_value(x) define.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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One of these has crept in in this commit:
40a808f1 ARCv2: SLC: Make sure busy bit is set properly on SLC flushing
Adjust buildman to handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Not force to use python from PATH. Issue was noted when building with
Yocto, because python from the distro is always taken instead of
python-native built during Yocto process.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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There is a strange interaction with drivers which use DMA if the cache
starts off in a dirty state. Buffer space which the driver reads (but has
not previously written) can contain zero bytes from alloc_priv(). This can
cause corruption of the memory used by DMA for incoming data.
Fix this and add a comment to explain the problem.
This allows the dwc2 driver to work correctly with driver model, for
example.
Signed-off-by: Simon Glass <sjg@chromium.org>
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uclass_find_device_by_seq() prints seq and req_seq when debugging is
enabled, but this information is not very useful by itself. Add the
name of he driver to this information. This improves debugging as it
shows which devices are being considered.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Simon Glass <sjg@chromium.org>
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With skeleton.dtsi being dropped it is more likely that the /aliases node
will be last in the device tree. Update fdtgrep to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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With Python 3.5.2 encode will throw an exception if val is a byte array.
Decode it to a string first. This assumes it's utf-8, if it's not valid
utf-8 it will throw an exception.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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os.read() returns a byte array in Python 3.5.2 and needs to be converted
into a string. Check if the returned value is an instance of bytes and
if it is decode it as a utf-8 string. If it is not a utf-8 encoded string
the decoding may fail with an exception.
Prior to this fix the comparisions check data == "" would fail when data
was b'' and would cause an infinite memory leaking loop. joins would
also fail with an exception below but due to the infinite loop it never
made it that far.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Do not condition the compilation of the U_BOOT_DRIVER by !OF_PLATDATA.
This is inconsistent with the majority of other drivers. This also
blocks OF_PLATDATA boards with an 16550-compatible serial from using
serial in SPL.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added tweak for rock to avoid a TPL build failure:
Signed-off-by: Simon Glass <sjg@chromium.org>
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As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)
Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.
Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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For some reason Python 3 seems to think it does not need to build
the library. Using the --force parameter makes sure that the library
gets built always. This is especially important since we move the
library in the next step of the Makefile, hence forcing a rebuild
every time the higher level Makefile triggers a rebuild is required
to make sure the library is always there.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This a few minor changes down from upstream since the last sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Since Binutils 1a9ccd70f9a7[1] u-boot will not link targets that set
CONFIG_SYS_TEXT_BASE=0 with the following error:
LD u-boot
arm-linux-gnueabi-ld.bfd: u-boot: Not enough room for program headers, try
linking with -N
arm-linux-gnueabi-ld.bfd: final link failed: Bad value
The issue can be reproduced with the bad binutils and the rock2_defconfig
target.
This issue was also encountered by the powerpc kernel[2], with the fix
being to pass --no-dynamic-linker for linkers newer than 2.26 when this
flag was introduced. The option tells ld that the PIE or shared lib does
not need loaded program headers.
Ubuntu Zesty's Binutils 2.27.51.20161202 hits this error.
[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0a
Signed-off-by: Joel Stanley <joel@jms.id.au>
[AF: Apply to LDFLAGS_$(SPL_BIN) as well, suggested by Tom Rini]
Signed-off-by: Andreas Färber <afaerber@suse.de>
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We disable this specific board as it does not link with the gcc-4.9.x
that we use today in travis-ci.
Signed-off-by: Tom Rini <trini@konsulko.com>
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This simple PMU driver allows to tyrn power on and off for selected
devices. In particularly Intel Tangier needs to power on SDHCI
controllers in order to access to them during board initialization.
In the future it might be expanded to cover other Intel MID platforms,
that's why it's located under arch/x86/lib and called pmu.c.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Intel MID platforms have few microcontrollers inside SoC, one of them
is so called System Controller Unit (SCU).
Here is the driver to communicate with microcontroller.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL / UART_DIV
The baudrate is calculated as
baud rate = UART clock / UART_PS / DLAB
Initialize fractional divider correctly for Intel Edison platform.
For backward compatibility we have to set initial DLAB value to 16
and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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With recent changes, some x86-specific rom tests of binman fail to
run. Fix it by adding missing filenames in corresponding entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Checking 'is_zimage' at this time will always fail and therefore booting
a FIT style image will always lead to this error message:
"## Kernel loading failed (missing x86 kernel setup) ..."
This change now removes this check and booting of FIT images works just
fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Now that we have added file names from Kconfig in x86 u-boot.dtsi,
update binman to avoid using hard-coded names.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Since we now have the file names configurable via Kconfig for the flash
descriptor and intel-me files, add these from Kconfig in the corresponding
dts nodes.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This introduces two Kconfig options to enable board specific filenames
for the Intel binary blobs to be used to generate the SPI flash image.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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At present there are only 8-bit and 32-bit read/write routines in
the rtc uclass driver. This adds the 16-bit support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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There is option which is not used:
CONFIG_ZBOOT_32
Remove it from default x86 config and from whitelist.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Move the OPTEE load address to 0xbdb00000 in order to avoid
overlap with the memory regions used in radio and RVC usecases.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Move the OPTEE load address to 0xbdb00000 in order to avoid
overlap with the memory regions used in radio and RVC usecases.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Enable SPL_USB_HOST_SUPPORT in the default defconfig to allow
booting from USB peripherals. Unlike the non-HS boards, we
already load SPL to a 0x4030_0000+ address, so no other changes
are needed.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Enable CONFIG_SPL_USBETH_SUPPORT in the default defconfig to allow
booting as a USB RNDIS peripheral.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Enable Eth/Net boot support in the default defconfig to allow
network booting.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Sync new additions to non-HS defconfig with HS defconfig. Also add SPL
NAND support, this was disabled before due to size constraints, enable
this now at the expense of the less used GPT partition support.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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FIT support in the net boot case is much like the RAM boot case in that
we load our image to "load_addr" and pass a dummy read function into
"spl_load_simple_fit()". As the load address is no longer hard-coded to
the final execution address, legacy image loading will require load_addr
to be set correctly in the image header.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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TI K2G secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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TI K2HK secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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TI K2E secure devices have to be built with TI_SECURE_DEVICE, FIT, and
FIT_IMAGE_POST_PROCESS enabled. Add a dedicated defconfig for this.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This patch makes SYS_TEXT_BASE a config option for Keystone2
so that it can be used to load u-boot at different addresses
on secure and non-secure Keystone2 devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add a section describing the secure boot image used on
Keystone2 secure devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Adds an additional image type needed for supporting secure keystone
devices. The build generates u-boot_HS_MLO which can be used to boot
from all media on secure keystone devices.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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As K2 can directly boot U-Boot, add u-boot_HS_MLO as the secure image
name for secure K2 devices, for all boot modes other than SPI flash.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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Like the OMAP54xx, AM43xx, & AM33xx family SoCs, the keystone family
of SoCs also have high security enabled models. Allow K2E devices to
be built with HS Device Type Support.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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This commit implements the board_fit_image_post_process() function for
the keystone architecture. This function calls into the secure boot
monitor for secure authentication/decryption of the image. All needed
work is handled by the boot monitor and, depending on the keystone
platform, the security functions may be offloaded to other secure
processing elements in the SoC.
The boot monitor acts as the gateway to these secure functions and the
boot monitor for secure devices is available as part of the SECDEV
package for KS2. For more details refer doc/README.ti-secure
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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The function 'board_fit_image_post_process' is defined only when the
config option CONFIG_FIT_IMAGE_POST_PROCESS is enabled. For secure
systems that do not use SPL but do use FIT kernel images, only
CONFIG_FIT_IMAGE_POST_PROCESS will be defined, which will result in an
implicit declaration of function 'board_fit_image_post_process' warning
while building u-boot. Fix this warning.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
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The most common name for a FIT image containing a bootable kernel is
"fitImage", as our builds now use this name also, change this to the
default in our U-Boot environment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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Various commands to NAND flash results in the NAND flash becoming busy.
For those commands the SoC should wait until the NAND indicates it is
no longer busy before sending further commands. However, there is a delay
between the time the SoC sends its last command and when the NAND flash
sets its Ready/Busy Pin. This delay (tWB) must be respected or the SoC may
falsely assume the flash is ready when in reality it just hasn't had enough
time to indicate that it is busy.
Properly delaying by tWB is already done for nand_command/nand_command_lp
in nand_base.c including the version of it in the Linux kernel. Therefore,
this patch brings the handling of tWB delay inline to nand_base.c
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[trini: Reformat comments slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
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