| Age | Commit message (Collapse) | Author |
|---|
|
Introduce a structure for accessing the General Power Controller block (GPC)
registers.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.
After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.
So revert it until a more complete and useful device tree could be provided.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
|
|
filesystem independent
nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic
'load' command instead of 'fatload'. It allows to use ext filesystem and keep
compatibilty with fat filesystem.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stefano Babic <sbabic@denx.de>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
|
|
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.
This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.
Signed-off-by: Stefan Agner <stefan@agner.ch>
|
|
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Signed-off-by: Stefan Agner <stefan@agner.ch>
|
|
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
|
|
The load region size of EIM-NOR are defined to 0. For this case,
the parameter "imximage_init_loadsize" must be calculated.
The imximage tool implements the calculation in the "imximage_generate"
function, but the following function "imximage_set_header" resets the value
and not calculate. This bug cause some fields of IVT head are not
correct, for example the boot_data and DCD overlay the application area.
Signed-off-by: Ye.Li <B37916@freescale.com>
|
|
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
|
|
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
if (gpio_cfg[board].leds[i])
^
board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
for (i = 0; i < 4; i++) {
^
Fix this by making the upper bound of the loop match the array size.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
|
|
According to mx53 and mx6 reference manuals:
"The maximum size of the DCD limited to 1768 bytes."
As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
excluding the first entry, which is the header leads to 220 as the maximum
number for DCD size.
Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
|
|
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
Add support for SATA.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add ethernet support for Compulab CM-FX6 CoM
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add NAND support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Define get_cpu_type(). Reuse it in is_cpu_type().
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Refactor the calculation.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
|
|
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
No functional changes.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
|
|
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.
This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
|
|
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
|
|
KBuild abuses the asm statement to write to a file and
clang chokes about these invalid asm statements. Hack it
even more by fooling this is actual valid asm code.
cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]
Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.
[1] http://clang.llvm.org/docs/UsersManual.html
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
By default clang will echo a warning if a warning option is
unknown. Turning warnings into errors when polling for options
also catches such cases and prevents passing arguments to the
compiler which cause warnings.
cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
Just before calling board_init_f, crt0.S has already
reserved space for the initial gd on the stack. There
should be no need to allocate it again.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
For ARM / ARM64 the relocation routines already updated
gd to the new value. Don't set it again. This allows
compilation with clang as it cannot update gd directly.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
|
|
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined
type.
For detailed explanation see similar patch for the nios2 arch:
"nios2: Fix printf size_t format related warnings (again...)"
(sha1: 00a2517fcb5159ed016b25130184638b1dbf2f02)
Signed-off-by: Vasili Galka <vvv444@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
|
|
|
|
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
|
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
|
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
|
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
|
|
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for instance.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
|
|
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
