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2019-07-20rockchip: Kconfig: move rk3368 config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk3288 config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: Kconfig: move rk322x config into its KconfigKever Yang
Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: fixup board choice in KconfigKever Yang
Kconfig for board target select is choice option, fixup for rk3036, rk3288 and rv1108. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: remove redundant pinctrl header includingKever Yang
No code is using this header file, remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3288: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3188: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: rk3399: remove pinctrl init in spl_board_initKever Yang
The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsiJagan Teki
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board. All these timings are processed during TPL stage of rock-pi-4 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsiJagan Teki
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsiJagan Teki
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board. All these timings are processed during TPL stage of rockpro64 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: Add LPDDR4-100 timingsJagan Teki
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file. all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin Associated LPDDR4 board -u-boot.dtsi can include this to make these timings available during SPL or TPL stages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21configs: rock-pi-4: Enable LPDDR4 supportJagan Teki
Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rock-PI-4 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21configs: rockpro64: Enable LPDDR4 supportJagan Teki
Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rockpro64 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 set rate supportJagan Teki
Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add set_rate sdram rk3399 opsJagan Teki
DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDDR4-800 timings incJagan Teki
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDDR4-400 timings incJagan Teki
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmuJagan Teki
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi so-that SPL can access pmu. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21rockchip: rk3399: syscon: Add pmu supportJagan Teki
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399 via syscon rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21arm: include: rockchip: Add rk3399 pmu fileJagan Teki
Add pmu header file for rk3399 SoC, this will help to configure pmu in sdram driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDR4 mr detectionJagan Teki
Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held. Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization. So, add code to support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Handle data training via opsJagan Teki
data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Simplify data training first argumentJagan Teki
data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition. This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref_mode_acJagan Teki
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8% Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 mode_sel based on io settingsJagan Teki
The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref based on io settingsJagan Teki
The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Get lpddr4 tsel_rd_en from io settingsJagan Teki
For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure soc odt supportJagan Teki
CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399. These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Add tsel control clock driveJagan Teki
tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: sdram: Configure lpddr4 tsel rd, wr based on IO settingsJagan Teki
Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Add IO settingsJagan Teki
Add IO settings for dram ctl and phy. IO settings are useful for configuring ctl, phy odt, vref, mr5, mode select and other needed input output operations for lpddr4 or any other dramtype sdram. Right now, this patch added IO setting for all supported sdram frequencies. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1Jagan Teki
The hardware for LPDDR4 with - CLK0P/N connect to lower 16-bits - CLK1P/N connect to higher 16-bits and usually dfi dram clk is configured via CLK1P/N, so disabling dfi dram clk will disable the CLK1P/N as well. So, add patch to not to disable dfi dram clk for lpddr4, with rank 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure tsel write ca for lpddr4Jagan Teki
tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt. Configure the same PHY register for lpddr4 would require a mask value of (300 << 8). Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Map chipselect for lpddr4Jagan Teki
Assign desired cs_map values for lpddr4 during set memory map. Initial cs_map values is based on the sdram parameters, so the same will adjusted based dramtype as LPDDR4. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4Jagan Teki
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4Jagan Teki
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4Jagan Teki
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure PHY_898, PHY_919 for lpddr4Jagan Teki
PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4. So, configure the same in pctl_cfg for LPDDR4. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Avoid two channel ZQ Cal Start at the same timeJagan Teki
It is possible in lpddr4 dram, where both the channels would start at same time with ZQ Cal Start. If it uses ZQ Call start then it will use RZQ. For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe connect to both channel. If ZQ Cal Start at the same time, it will use the same RZQ. It is not a problem of using RZQ in both the channels, but can not use at the same time. So, to avoid this, we have an option of dram tINIT3 value for increasing the frequency for channel 1. This patch increase the available tINIT3 with existing running dram frequency. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Don't wait for PLL lock in lpddr4Jagan Teki
lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Move mode_sel assignmentJagan Teki
mode_sel assignment is based on dram type. In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 rank mask for wdql trainingJagan Teki
Add rank_mask based on the rank number for lpddr4. This would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 rank mask for ca trainingJagan Teki
Add rank_mask based on the rank number for lpddr4. This would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rockchip: Kconfig: Add RK3399 LPDDR4 entryJagan Teki
Supporting LPDDR4 code support in RK3399 would increases the size of SPL/TPL. So add kconfig entry for RK3399 LPDDR4 code so-that the boards have LPDDR4 can enable them via defconfig. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure phy IO in ds odtJagan Teki
Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt. For those cases the set_ds_odt would be an initial call to setup the phy. To satisfy all the cases, trigger phy IO from set_ds_odt. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add DdrModeJagan Teki
Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddrtimingC0Jagan Teki
Add DdrTimingC0 structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2024-12-29 03:08:22 +0000